From 35fd1e8f5bc6270b884e7728ebf255254b565cc3 Mon Sep 17 00:00:00 2001 From: Enrik Berkhan Date: Wed, 23 Jan 2008 12:12:01 +0100 Subject: Fix/Adapt settings for version 2 of IPE337 Signed-Off-By: Enrik Berkhan --- arch/blackfin/cpu-bf561/init_sdram.S | 53 +++++++++++++++++++++++++++++++++++- include/configs/ipe337.h | 16 +++++++---- 2 files changed, 62 insertions(+), 7 deletions(-) diff --git a/arch/blackfin/cpu-bf561/init_sdram.S b/arch/blackfin/cpu-bf561/init_sdram.S index f16bb28bad..84fda76bcd 100644 --- a/arch/blackfin/cpu-bf561/init_sdram.S +++ b/arch/blackfin/cpu-bf561/init_sdram.S @@ -27,7 +27,7 @@ init_sdram: */ p0.h = hi(PLL_LOCKCNT); p0.l = lo(PLL_LOCKCNT); - r0 = 0x300(Z); + r0 = 0x640(Z); w[p0] = r0.l; ssync; @@ -41,6 +41,44 @@ init_sdram: [P2] = R0; SSYNC; + /* Make sure PLL wakeup is enabled as BOOT ROM seems to disable + * it. (R7 and R6 used to store original value!) + */ + p0.h = hi(SIC_IWR); + p0.l = lo(SIC_IWR); + r7 = [p0]; + r0 = 1; + [p0] = r0; +#ifdef SICA_IWR1 + p0.h = hi(SICA_IWR1); + p0.l = lo(SICA_IWR1); + r6 = [p0]; + r0 = 0; + [p0] = r0; +#endif + ssync; + +#ifdef CONFIG_VSEL + /* + * + * Set Voltage Regulator. + */ + + p2.h = hi(VR_CTL); + p2.l = lo(VR_CTL); + r0 = w[p2]; + r1 = ~0xf0; + r0 = r0 & r1; + r1 = CONFIG_VSEL & 0x0f; + r1 = r1 << 4; + r0 = r0 | r1; + cli r2; + ssync; + w[p2] = r0.l; + idle; + sti r2; +#endif + /* * Set PLL_CTL with the value that we calculate in R0 * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors @@ -159,6 +197,19 @@ skip: SSYNC; nop; + /* + * Restore wakeup + */ + p0.h = hi(SIC_IWR); + p0.l = lo(SIC_IWR); + [p0] = r7; +#ifdef SICA_IWR1 + p0.h = hi(SICA_IWR1); + p0.l = lo(SICA_IWR1); + [p0] = r6; +#endif + ssync; + (P5:0) = [SP++]; (R7:0) = [SP++]; RETS = [SP++]; diff --git a/include/configs/ipe337.h b/include/configs/ipe337.h index 47e4c2c2e5..9ff6297e6b 100644 --- a/include/configs/ipe337.h +++ b/include/configs/ipe337.h @@ -11,7 +11,7 @@ */ /* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 +#define CONFIG_CLKIN_HZ 40000000 /* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ /* 1=CLKIN/2 */ #define CONFIG_CLKIN_HALF 0 @@ -20,19 +20,23 @@ #define CONFIG_PLL_BYPASS 0 /* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ /* Values can range from 1-64 */ -#define CONFIG_VCO_MULT 24 +#define CONFIG_VCO_MULT 10 /* POR default */ /* CONFIG_CCLK_DIV controls what the core clock divider is */ /* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 +#define CONFIG_CCLK_DIV 1 /* POR default */ /* CONFIG_SCLK_DIV controls what the peripheral clock divider is */ /* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 9 +#define CONFIG_SCLK_DIV 5 /* POR default */ + +/* Frequencies selected: 400MHz CCLK / 80MHz SCLK ^= 12.5ns cycle time*/ #define AMGCTLVAL 0x1F -#define AMBCTL0VAL 0x14407BB0 + +/* no need for speed, currently, leave at defaults */ +#define AMBCTL0VAL 0xFFC2FFC2 #define AMBCTL1VAL 0xFFC2FFC2 #define CONFIG_MEM_MT48LC16M16A2TG_75 1 -#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */ +#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */ #define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */ -- cgit v1.2.3