From fa8a8ec88668a43874220cad21a2fa95bac054e5 Mon Sep 17 00:00:00 2001 From: Michael Grzeschik Date: Fri, 5 May 2017 17:49:18 +0200 Subject: i.MX: fec: also enable optional clocks This will also enable two more optional clocks. They can be found on mx6ul, mx6sx and mx28. Signed-off-by: Michael Grzeschik Signed-off-by: Sascha Hauer --- drivers/net/fec_imx.c | 29 +++++++++++++++++++++++++++++ drivers/net/fec_imx.h | 8 ++++++++ 2 files changed, 37 insertions(+) diff --git a/drivers/net/fec_imx.c b/drivers/net/fec_imx.c index e2b25fe375..8cf7c4fbda 100644 --- a/drivers/net/fec_imx.c +++ b/drivers/net/fec_imx.c @@ -662,6 +662,14 @@ static int fec_clk_enable(struct fec_priv *fec) return err; } + for (i = 0; i < ARRAY_SIZE(fec->opt_clk); i++) { + if (!IS_ERR_OR_NULL(fec->opt_clk[i])) { + const int err = clk_enable(fec->opt_clk[i]); + if (err < 0) + return err; + } + } + return 0; } @@ -673,6 +681,12 @@ static void fec_clk_disable(struct fec_priv *fec) if (!IS_ERR_OR_NULL(fec->clk[i])) clk_disable(fec->clk[i]); } + + for (i = 0; i < ARRAY_SIZE(fec->opt_clk); i++) { + if (!IS_ERR_OR_NULL(fec->opt_clk[i])) { + clk_disable(fec->opt_clk[i]); + } + } } static void fec_clk_put(struct fec_priv *fec) @@ -683,6 +697,11 @@ static void fec_clk_put(struct fec_priv *fec) if (!IS_ERR_OR_NULL(fec->clk[i])) clk_put(fec->clk[i]); } + + for (i = 0; i < ARRAY_SIZE(fec->opt_clk); i++) { + if (!IS_ERR_OR_NULL(fec->opt_clk[i])) + clk_put(fec->opt_clk[i]); + } } static int fec_clk_get(struct fec_priv *fec) @@ -691,6 +710,9 @@ static int fec_clk_get(struct fec_priv *fec) static const char *clk_names[ARRAY_SIZE(fec->clk)] = { "ipg", "ahb", "ptp" }; + static const char *opt_clk_names[ARRAY_SIZE(fec->opt_clk)] = { + "enet_clk_ref", "enet_out", + }; for (i = 0; i < ARRAY_SIZE(fec->clk); i++) { fec->clk[i] = clk_get(fec->edev.parent, clk_names[i]); @@ -701,6 +723,13 @@ static int fec_clk_get(struct fec_priv *fec) } } + for (i = 0; i < ARRAY_SIZE(fec->opt_clk); i++) { + fec->opt_clk[i] = clk_get(fec->edev.parent, opt_clk_names[i]); + if (IS_ERR(fec->opt_clk[i])) { + fec->opt_clk[i] = NULL; + } + } + return err; } diff --git a/drivers/net/fec_imx.h b/drivers/net/fec_imx.h index 85d51bad60..561de0890b 100644 --- a/drivers/net/fec_imx.h +++ b/drivers/net/fec_imx.h @@ -137,6 +137,13 @@ enum fec_clock { FEC_CLK_NUM }; +enum fec_opt_clock { + FEC_OPT_CLK_REF, + FEC_OPT_CLK_OUT, + + FEC_OPT_CLK_NUM +}; + /** * @brief i.MX27-FEC private structure */ @@ -153,6 +160,7 @@ struct fec_priv { struct mii_bus miibus; void (*phy_init)(struct phy_device *dev); struct clk *clk[FEC_CLK_NUM]; + struct clk *opt_clk[FEC_OPT_CLK_NUM]; enum fec_type type; }; -- cgit v1.2.3 From ed073bcac38d69347d7fa31c5c2674aa562d6b0f Mon Sep 17 00:00:00 2001 From: Michael Grzeschik Date: Fri, 5 May 2017 17:49:19 +0200 Subject: ARM: phytec-som-imx6: the ethernet clocks get enabled by fec_imx All necessary clocks get already enabled through the fec_imx driver configured by the devicetree. Signed-off-by: Michael Grzeschik Signed-off-by: Sascha Hauer --- arch/arm/boards/phytec-som-imx6/board.c | 27 +-------------------------- 1 file changed, 1 insertion(+), 26 deletions(-) diff --git a/arch/arm/boards/phytec-som-imx6/board.c b/arch/arm/boards/phytec-som-imx6/board.c index 31b2761024..b93fd1be60 100644 --- a/arch/arm/boards/phytec-som-imx6/board.c +++ b/arch/arm/boards/phytec-som-imx6/board.c @@ -31,7 +31,6 @@ #include #include #include -#include #include #include @@ -97,32 +96,14 @@ int ksz8081_phy_fixup(struct phy_device *phydev) return 0; } -static int imx6ul_setup_fec(void) +static void imx6ul_setup_fec(void) { void __iomem *gprbase = IOMEM(MX6_IOMUXC_BASE_ADDR) + 0x4000; uint32_t val; - struct clk *clk; phy_register_fixup_for_uid(PHY_ID_KSZ8081, MICREL_PHY_ID_MASK, ksz8081_phy_fixup); - clk = clk_lookup("enet_ptp"); - if (IS_ERR(clk)) - goto err; - - clk_enable(clk); - - clk = clk_lookup("enet_ref"); - if (IS_ERR(clk)) - goto err; - clk_enable(clk); - - clk = clk_lookup("enet_ref_125m"); - if (IS_ERR(clk)) - goto err; - - clk_enable(clk); - val = readl(gprbase + IOMUXC_GPR1); /* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]*/ val &= ~(1 << 13); @@ -131,12 +112,6 @@ static int imx6ul_setup_fec(void) val &= ~(1 << 14); val |= (1 << 18); writel(val, gprbase + IOMUXC_GPR1); - - return 0; -err: - pr_err("Setting up DFEC\n"); - - return -EIO; } static int physom_imx6_devices_init(void) -- cgit v1.2.3 From c2b01502e0faf0562bb5319021e36d9125b2b7c8 Mon Sep 17 00:00:00 2001 From: Michael Grzeschik Date: Fri, 5 May 2017 17:49:20 +0200 Subject: ARM: mx6sx-sabresdb: the ethernet clocks get enabled by fec_imx All necessary clocks get already enabled through the fec_imx driver configured by the devicetree. Signed-off-by: Michael Grzeschik Signed-off-by: Sascha Hauer --- arch/arm/boards/freescale-mx6sx-sabresdb/board.c | 27 +----------------------- 1 file changed, 1 insertion(+), 26 deletions(-) diff --git a/arch/arm/boards/freescale-mx6sx-sabresdb/board.c b/arch/arm/boards/freescale-mx6sx-sabresdb/board.c index ca22eba393..028b1dddbe 100644 --- a/arch/arm/boards/freescale-mx6sx-sabresdb/board.c +++ b/arch/arm/boards/freescale-mx6sx-sabresdb/board.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include @@ -181,11 +180,10 @@ int ar8031_phy_fixup(struct phy_device *phydev) #define PHY_ID_AR8031 0x004dd074 #define AR_PHY_ID_MASK 0xffffffff -static int imx6sx_sdb_setup_fec(void) +static void imx6sx_sdb_setup_fec(void) { void __iomem *gprbase = (void *)MX6_IOMUXC_BASE_ADDR + 0x4000; uint32_t val; - struct clk *clk; phy_register_fixup_for_uid(PHY_ID_AR8031, AR_PHY_ID_MASK, ar8031_phy_fixup); @@ -193,23 +191,6 @@ static int imx6sx_sdb_setup_fec(void) /* Active high for ncp692 */ gpio_direction_output(IMX_GPIO_NR(4, 16), 1); - clk = clk_lookup("enet_ptp_25m"); - if (IS_ERR(clk)) - goto err; - - clk_enable(clk); - - clk = clk_lookup("enet_ref"); - if (IS_ERR(clk)) - goto err; - clk_enable(clk); - - clk = clk_lookup("enet2_ref_125m"); - if (IS_ERR(clk)) - goto err; - - clk_enable(clk); - val = readl(gprbase + IOMUXC_GPR1); /* Use 125M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ val &= ~(1 << 13); @@ -226,12 +207,6 @@ static int imx6sx_sdb_setup_fec(void) gpio_direction_output(IMX_GPIO_NR(2, 7), 0); udelay(500); gpio_set_value(IMX_GPIO_NR(2, 7), 1); - - return 0; -err: - pr_err("Setting up DFEC\n"); - - return -EIO; } static int imx6sx_sdb_coredevices_init(void) -- cgit v1.2.3 From 7dd5deb8bf04db1ecffff65647475554d99cc830 Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Mon, 8 May 2017 15:25:20 +0200 Subject: ARM: i.MX: HAB: update documentation of command sequence files (CSF) Signed-off-by: Marc Kleine-Budde Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/include/mach/habv3-imx25-gencsf.h | 11 ++++++++--- arch/arm/mach-imx/include/mach/habv4-imx6-gencsf.h | 9 +++++---- 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-imx/include/mach/habv3-imx25-gencsf.h b/arch/arm/mach-imx/include/mach/habv3-imx25-gencsf.h index f4804fe63f..60f730f8ec 100644 --- a/arch/arm/mach-imx/include/mach/habv3-imx25-gencsf.h +++ b/arch/arm/mach-imx/include/mach/habv3-imx25-gencsf.h @@ -4,8 +4,8 @@ * are expected in these config variables: * * CONFIG_HABV3_SRK_PEM - * CONFIG_HABV3_SRK_PEM - * CONFIG_HABV3_IMG_CRT_PEM + * CONFIG_HABV3_CSF_CRT_DER + * CONFIG_HABV3_IMG_CRT_DER */ super_root_key CONFIG_HABV3_SRK_PEM @@ -23,21 +23,26 @@ hab [Install SRK] hab File = "not-used" hab [Install CSFK] +/* target key index in keystore 1 */ hab File = CONFIG_HABV3_CSF_CRT_DER hab [Authenticate CSF] -/* below is the command that unlock the access to the DryIce registers */ +/* unlock the access to the DryIce registers */ hab [Write Data] hab Width = 4 hab Address Data = 0x53FFC03C 0xCA693569 hab [Install Key] +/* verification key index in key store (1...4) */ +/* in contrast to documentation 0 seems to be valid, too */ hab Verification index = 1 +/* target key index in key store (1...4) */ hab Target index = 2 hab File = CONFIG_HABV3_IMG_CRT_DER hab [Authenticate Data] +/* verification key index in key store (2...4) */ hab Verification index = 2 hab_blocks diff --git a/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf.h b/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf.h index 1a143a8b18..0649caa0cb 100644 --- a/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf.h +++ b/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf.h @@ -22,6 +22,7 @@ hab # SRK index within SRK-Table 0..3 hab Source index = 0 hab [Install CSFK] +/* target key index in keystore 1 */ hab File = CONFIG_HABV4_CSF_CRT_PEM hab [Authenticate CSF] @@ -31,14 +32,14 @@ hab Engine = CAAM hab Features = RNG hab [Install Key] -/* verification key index in key store (0, 2...5) */ +/* verification key index in key store (0, 2...4) */ hab Verification index = 0 -/* target key index in key store (2...5) */ +/* target key index in key store (2...4) */ hab Target index = 2 hab File = CONFIG_HABV4_IMG_CRT_PEM hab [Authenticate Data] -/* verification key index in key store (2...5) */ +/* verification key index in key store (2...4) */ hab Verification index = 2 -hab_blocks \ No newline at end of file +hab_blocks -- cgit v1.2.3 From 366d0ce037eeae98778f89229f31b13f3a959207 Mon Sep 17 00:00:00 2001 From: Stefan Riedmueller Date: Thu, 11 May 2017 11:09:26 +0200 Subject: ARM: i.MX: Add i.MX6 ULL support Signed-off-by: Stefan Riedmueller Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/imx.c | 2 ++ arch/arm/mach-imx/imx6.c | 3 +++ arch/arm/mach-imx/include/mach/imx6.h | 2 ++ 3 files changed, 7 insertions(+) diff --git a/arch/arm/mach-imx/imx.c b/arch/arm/mach-imx/imx.c index 19907397f9..9400105c66 100644 --- a/arch/arm/mach-imx/imx.c +++ b/arch/arm/mach-imx/imx.c @@ -67,6 +67,8 @@ static int imx_soc_from_dt(void) return IMX_CPU_IMX6; if (of_machine_is_compatible("fsl,imx6ul")) return IMX_CPU_IMX6; + if (of_machine_is_compatible("fsl,imx6ull")) + return IMX_CPU_IMX6; if (of_machine_is_compatible("fsl,imx7s")) return IMX_CPU_IMX7; if (of_machine_is_compatible("fsl,imx7d")) diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c index 44a8dbefd0..7b3fc1da27 100644 --- a/arch/arm/mach-imx/imx6.c +++ b/arch/arm/mach-imx/imx6.c @@ -160,6 +160,9 @@ int imx6_init(void) case IMX6_CPUTYPE_IMX6UL: cputypestr = "i.MX6 UltraLite"; break; + case IMX6_CPUTYPE_IMX6ULL: + cputypestr = "i.MX6 ULL"; + break; default: cputypestr = "unknown i.MX6"; break; diff --git a/arch/arm/mach-imx/include/mach/imx6.h b/arch/arm/mach-imx/include/mach/imx6.h index 327676bc69..6ad53433cb 100644 --- a/arch/arm/mach-imx/include/mach/imx6.h +++ b/arch/arm/mach-imx/include/mach/imx6.h @@ -18,6 +18,7 @@ void imx6_init_lowlevel(void); #define IMX6_CPUTYPE_IMX6D 0x263 #define IMX6_CPUTYPE_IMX6Q 0x463 #define IMX6_CPUTYPE_IMX6UL 0x164 +#define IMX6_CPUTYPE_IMX6ULL 0x165 #define SCU_CONFIG 0x04 @@ -82,6 +83,7 @@ DEFINE_MX6_CPU_TYPE(mx6d, IMX6_CPUTYPE_IMX6D); DEFINE_MX6_CPU_TYPE(mx6sx, IMX6_CPUTYPE_IMX6SX); DEFINE_MX6_CPU_TYPE(mx6sl, IMX6_CPUTYPE_IMX6SL); DEFINE_MX6_CPU_TYPE(mx6ul, IMX6_CPUTYPE_IMX6UL); +DEFINE_MX6_CPU_TYPE(mx6ull, IMX6_CPUTYPE_IMX6ULL); static inline int __imx6_cpu_revision(void) { -- cgit v1.2.3 From efdd506a595f72f5e5567ed9a5d0b8fe1c0a63d2 Mon Sep 17 00:00:00 2001 From: Stefan Riedmueller Date: Thu, 11 May 2017 11:09:27 +0200 Subject: ARM: i.MX6ul: Add Clock support for i.MX6ull From linux-4.10 clock support, only skipped some unnecessary clocks Signed-off-by: Stefan Riedmueller Signed-off-by: Sascha Hauer --- drivers/clk/imx/clk-imx6ul.c | 73 +++++++++++++++++++++++++++++++++++++------- 1 file changed, 62 insertions(+), 11 deletions(-) diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c index f28660d6ea..b0a6bb0e8d 100644 --- a/drivers/clk/imx/clk-imx6ul.c +++ b/drivers/clk/imx/clk-imx6ul.c @@ -66,10 +66,24 @@ static const char *perclk_sels[] = { "ipg", "osc", }; static const char *lcdif_sels[] = { "lcdif_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", }; static const char *csi_sels[] = { "osc", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", }; static const char *sim_sels[] = { "sim_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", }; +/* epdc_pre_sels, epdc_sels, esai_sels only exists on i.MX6ULL */ +static const char *epdc_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd2_508m", }; +static const char *esai_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", }; +static const char *epdc_sels[] = { "epdc_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", }; static struct clk *clks[IMX6UL_CLK_END]; static struct clk_onecell_data clk_data; +static inline int clk_on_imx6ul(void) +{ + return of_machine_is_compatible("fsl,imx6ul"); +} + +static inline int clk_on_imx6ull(void) +{ + return of_machine_is_compatible("fsl,imx6ull"); +} + static int const clks_init_on[] __initconst = { IMX6UL_CLK_AIPSTZ1, IMX6UL_CLK_AIPSTZ2, IMX6UL_CLK_AIPSTZ3, IMX6UL_CLK_AXI, IMX6UL_CLK_ARM, IMX6UL_CLK_ROM, @@ -206,12 +220,19 @@ static int imx6_ccm_probe(struct device_d *dev) clks[IMX6UL_CLK_QSPI1_SEL] = imx_clk_mux("qspi1_sel", base + 0x1c, 7, 3, qspi1_sels, ARRAY_SIZE(qspi1_sels)); clks[IMX6UL_CLK_PERCLK_SEL] = imx_clk_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels)); clks[IMX6UL_CLK_CAN_SEL] = imx_clk_mux("can_sel", base + 0x20, 8, 2, can_sels, ARRAY_SIZE(can_sels)); + if (clk_on_imx6ull()) + clks[IMX6ULL_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, esai_sels, ARRAY_SIZE(esai_sels)); clks[IMX6UL_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels)); clks[IMX6UL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 15, 3, enfc_sels, ARRAY_SIZE(enfc_sels)); clks[IMX6UL_CLK_LDB_DI0_SEL] = imx_clk_mux("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di0_sels, ARRAY_SIZE(ldb_di0_sels)); clks[IMX6UL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, spdif_sels, ARRAY_SIZE(spdif_sels)); - clks[IMX6UL_CLK_SIM_PRE_SEL] = imx_clk_mux("sim_pre_sel", base + 0x34, 15, 3, sim_pre_sels, ARRAY_SIZE(sim_pre_sels)); - clks[IMX6UL_CLK_SIM_SEL] = imx_clk_mux("sim_sel", base + 0x34, 9, 3, sim_sels, ARRAY_SIZE(sim_sels)); + if (clk_on_imx6ul()) { + clks[IMX6UL_CLK_SIM_PRE_SEL] = imx_clk_mux("sim_pre_sel", base + 0x34, 15, 3, sim_pre_sels, ARRAY_SIZE(sim_pre_sels)); + clks[IMX6UL_CLK_SIM_SEL] = imx_clk_mux("sim_sel", base + 0x34, 9, 3, sim_sels, ARRAY_SIZE(sim_sels)); + } else if (clk_on_imx6ull()) { + clks[IMX6ULL_CLK_EPDC_PRE_SEL] = imx_clk_mux("epdc_pre_sel", base + 0x34, 15, 3, epdc_pre_sels, ARRAY_SIZE(epdc_pre_sels)); + clks[IMX6ULL_CLK_EPDC_SEL] = imx_clk_mux("epdc_sel", base + 0x34, 9, 3, epdc_sels, ARRAY_SIZE(epdc_sels)); + } clks[IMX6UL_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels)); clks[IMX6UL_CLK_LCDIF_PRE_SEL] = imx_clk_mux("lcdif_pre_sel", base + 0x38, 15, 3, lcdif_pre_sels, ARRAY_SIZE(lcdif_pre_sels)); clks[IMX6UL_CLK_LCDIF_SEL] = imx_clk_mux("lcdif_sel", base + 0x38, 9, 3, lcdif_sels, ARRAY_SIZE(lcdif_sels)); @@ -244,6 +265,10 @@ static int imx6_ccm_probe(struct device_d *dev) clks[IMX6UL_CLK_SAI3_PODF] = imx_clk_divider("sai3_podf", "sai3_pred", base + 0x28, 16, 6); clks[IMX6UL_CLK_SAI1_PRED] = imx_clk_divider("sai1_pred", "sai1_sel", base + 0x28, 6, 3); clks[IMX6UL_CLK_SAI1_PODF] = imx_clk_divider("sai1_podf", "sai1_pred", base + 0x28, 0, 6); + if (clk_on_imx6ull()) { + clks[IMX6ULL_CLK_ESAI_PRED] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3); + clks[IMX6ULL_CLK_ESAI_PODF] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3); + } clks[IMX6UL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3); clks[IMX6UL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); clks[IMX6UL_CLK_SAI2_PRED] = imx_clk_divider("sai2_pred", "sai2_sel", base + 0x2c, 6, 3); @@ -264,9 +289,15 @@ static int imx6_ccm_probe(struct device_d *dev) clks[IMX6UL_CLK_AIPSTZ1] = imx_clk_gate2("aips_tz1", "ahb", base + 0x68, 0); clks[IMX6UL_CLK_AIPSTZ2] = imx_clk_gate2("aips_tz2", "ahb", base + 0x68, 2); clks[IMX6UL_CLK_APBHDMA] = imx_clk_gate2("apbh_dma", "bch_podf", base + 0x68, 4); - clks[IMX6UL_CLK_CAAM_MEM] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8); - clks[IMX6UL_CLK_CAAM_ACLK] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10); - clks[IMX6UL_CLK_CAAM_IPG] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12); + if (clk_on_imx6ul()) { + clks[IMX6UL_CLK_CAAM_MEM] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8); + clks[IMX6UL_CLK_CAAM_ACLK] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10); + clks[IMX6UL_CLK_CAAM_IPG] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12); + } else if (clk_on_imx6ull()) { + clks[IMX6ULL_CLK_DCP_CLK] = imx_clk_gate2("dcp", "ahb", base + 0x68, 10); + clks[IMX6UL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x68, 12); + clks[IMX6UL_CLK_ENET_AHB] = imx_clk_gate2("enet_ahb", "ahb", base + 0x68, 12); + } clks[IMX6UL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); clks[IMX6UL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_podf", base + 0x68, 16); clks[IMX6UL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18); @@ -275,7 +306,10 @@ static int imx6_ccm_probe(struct device_d *dev) clks[IMX6UL_CLK_GPT2_SERIAL] = imx_clk_gate2("gpt2_serial", "perclk", base + 0x68, 26); clks[IMX6UL_CLK_UART2_IPG] = imx_clk_gate2("uart2_ipg", "ipg", base + 0x68, 28); clks[IMX6UL_CLK_UART2_SERIAL] = imx_clk_gate2("uart2_serial", "uart_podf", base + 0x68, 28); - clks[IMX6UL_CLK_AIPSTZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x68, 30); + if (clk_on_imx6ul()) + clks[IMX6UL_CLK_AIPSTZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x68, 30); + else if (clk_on_imx6ull()) + clks[IMX6UL_CLK_AIPSTZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x80, 18); /* CCGR1 */ clks[IMX6UL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_podf", base + 0x6c, 0); @@ -294,6 +328,11 @@ static int imx6_ccm_probe(struct device_d *dev) clks[IMX6UL_CLK_UART4_SERIAL] = imx_clk_gate2("uart4_serail", "uart_podf", base + 0x6c, 24); /* CCGR2 */ + if (clk_on_imx6ull()) { + clks[IMX6ULL_CLK_ESAI_EXTAL] = imx_clk_gate2("esai_extal", "esai_podf", base + 0x70, 0); + clks[IMX6ULL_CLK_ESAI_IPG] = imx_clk_gate2("esai_ipg", "ahb", base + 0x70, 0); + clks[IMX6ULL_CLK_ESAI_MEM] = imx_clk_gate2("esai_mem", "ahb", base + 0x70, 0); + } clks[IMX6UL_CLK_CSI] = imx_clk_gate2("csi", "csi_podf", base + 0x70, 2); clks[IMX6UL_CLK_I2C1] = imx_clk_gate2("i2c1", "perclk", base + 0x70, 6); clks[IMX6UL_CLK_I2C2] = imx_clk_gate2("i2c2", "perclk", base + 0x70, 8); @@ -306,8 +345,13 @@ static int imx6_ccm_probe(struct device_d *dev) /* CCGR3 */ clks[IMX6UL_CLK_UART5_IPG] = imx_clk_gate2("uart5_ipg", "ipg", base + 0x74, 2); clks[IMX6UL_CLK_UART5_SERIAL] = imx_clk_gate2("uart5_serial", "uart_podf", base + 0x74, 2); - clks[IMX6UL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x74, 4); - clks[IMX6UL_CLK_ENET_AHB] = imx_clk_gate2("enet_ahb", "ahb", base + 0x74, 4); + if (clk_on_imx6ul()) { + clks[IMX6UL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x74, 4); + clks[IMX6UL_CLK_ENET_AHB] = imx_clk_gate2("enet_ahb", "ahb", base + 0x74, 4); + } else if (clk_on_imx6ull()) { + clks[IMX6ULL_CLK_EPDC_ACLK] = imx_clk_gate2("epdc_aclk", "axi", base + 0x74, 4); + clks[IMX6ULL_CLK_EPDC_PIX] = imx_clk_gate2("epdc_pix", "epdc_podf", base + 0x74, 4); + } clks[IMX6UL_CLK_UART6_IPG] = imx_clk_gate2("uart6_ipg", "ipg", base + 0x74, 6); clks[IMX6UL_CLK_UART6_SERIAL] = imx_clk_gate2("uart6_serial", "uart_podf", base + 0x74, 6); clks[IMX6UL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_podf", base + 0x74, 10); @@ -343,8 +387,10 @@ static int imx6_ccm_probe(struct device_d *dev) clks[IMX6UL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); clks[IMX6UL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); clks[IMX6UL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); - clks[IMX6UL_CLK_SIM1] = imx_clk_gate2("sim1", "sim_sel", base + 0x80, 6); - clks[IMX6UL_CLK_SIM2] = imx_clk_gate2("sim2", "sim_sel", base + 0x80, 8); + if (clk_on_imx6ul()) { + clks[IMX6UL_CLK_SIM1] = imx_clk_gate2("sim1", "sim_sel", base + 0x80, 6); + clks[IMX6UL_CLK_SIM2] = imx_clk_gate2("sim2", "sim_sel", base + 0x80, 8); + } clks[IMX6UL_CLK_EIM] = imx_clk_gate2("eim", "eim_slow_podf", base + 0x80, 10); clks[IMX6UL_CLK_PWM8] = imx_clk_gate2("pwm8", "perclk", base + 0x80, 16); clks[IMX6UL_CLK_UART8_IPG] = imx_clk_gate2("uart8_ipg", "ipg", base + 0x80, 14); @@ -397,7 +443,12 @@ static int imx6_ccm_probe(struct device_d *dev) } clk_set_parent(clks[IMX6UL_CLK_CAN_SEL], clks[IMX6UL_CLK_PLL3_60M]); - clk_set_parent(clks[IMX6UL_CLK_SIM_PRE_SEL], clks[IMX6UL_CLK_PLL3_USB_OTG]); + if (clk_on_imx6ul()) + clk_set_parent(clks[IMX6UL_CLK_SIM_PRE_SEL], + clks[IMX6UL_CLK_PLL3_USB_OTG]); + else if (clk_on_imx6ull()) + clk_set_parent(clks[IMX6ULL_CLK_EPDC_PRE_SEL], + clks[IMX6UL_CLK_PLL3_PFD2]); clk_set_parent(clks[IMX6UL_CLK_ENFC_SEL], clks[IMX6UL_CLK_PLL2_PFD2]); -- cgit v1.2.3 From 4dc4e613eab3219d0699471678aadf6bb801efdc Mon Sep 17 00:00:00 2001 From: Stefan Riedmueller Date: Thu, 11 May 2017 11:09:28 +0200 Subject: ARCH: ARM: Add support for phytec-phycore-imx6ull Created imx6ull devicetree to support Phytec phyCORE-i.MX6ULL. - 256 MB RAM - 128 MB NAND - 10/100 Mbit Ethernet Signed-off-by: Stefan Riedmueller Signed-off-by: Sascha Hauer --- .../flash-header-phytec-pcl063-256mb.imxcfg | 9 ++ arch/arm/boards/phytec-som-imx6/lowlevel.c | 7 +- arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx6ul-phytec-phycore-som.dts | 146 +---------------- arch/arm/dts/imx6ul-phytec-phycore-som.dtsi | 178 +++++++++++++++++++++ arch/arm/dts/imx6ull-phytec-phycore-som.dts | 41 +++++ images/Makefile.imx | 5 + 7 files changed, 241 insertions(+), 148 deletions(-) create mode 100644 arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-256mb.imxcfg create mode 100644 arch/arm/dts/imx6ul-phytec-phycore-som.dtsi create mode 100644 arch/arm/dts/imx6ull-phytec-phycore-som.dts diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-256mb.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-256mb.imxcfg new file mode 100644 index 0000000000..4a827e4dfa --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-256mb.imxcfg @@ -0,0 +1,9 @@ + +#define SETUP_MDCFG0 \ + wm 32 0x021B000C 0x676B52F3 + +#define SETUP_MDASP_MDCTL \ + wm 32 0x021B0040 0x00000047; \ + wm 32 0x021B0000 0x83180000 + +#include "flash-header-phytec-pcl063.h" diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c b/arch/arm/boards/phytec-som-imx6/lowlevel.c index 3ab88f4a52..07ac4437ab 100644 --- a/arch/arm/boards/phytec-som-imx6/lowlevel.c +++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c @@ -54,7 +54,8 @@ static void __noreturn start_imx6_phytec_common(uint32_t size, int cpu_type = __imx6_cpu_type(); void *fdt; - if (cpu_type == IMX6_CPUTYPE_IMX6UL) { + if (cpu_type == IMX6_CPUTYPE_IMX6UL + || cpu_type == IMX6_CPUTYPE_IMX6ULL) { arm_cpu_lowlevel_init(); /* OCRAM Free Area is 0x00907000 to 0x00918000 (68KB) */ arm_setup_stack(0x00910000 - 8); @@ -69,7 +70,8 @@ static void __noreturn start_imx6_phytec_common(uint32_t size, fdt = fdt_blob_fixed_offset - get_runtime_offset(); - if (cpu_type == IMX6_CPUTYPE_IMX6UL) + if (cpu_type == IMX6_CPUTYPE_IMX6UL + || cpu_type == IMX6_CPUTYPE_IMX6ULL) barebox_arm_entry(0x80000000, size, fdt); else barebox_arm_entry(0x10000000, size, fdt); @@ -111,3 +113,4 @@ PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_1gib, imx6q_phytec_phycore_som_ PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_2gib, imx6q_phytec_phycore_som_emmc, SZ_2G, true); PHYTEC_ENTRY(start_phytec_phycore_imx6ul_som_512mb, imx6ul_phytec_phycore_som, SZ_512M, false); +PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_256mb, imx6ull_phytec_phycore_som, SZ_256M, false); diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 2342d35a4b..ec291ce6bf 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -53,7 +53,8 @@ pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-pbaa03.dtb.o \ imx6q-phytec-phycore-som-emmc.dtb.o \ imx6dl-phytec-phycore-som-nand.dtb.o \ imx6dl-phytec-phycore-som-emmc.dtb.o \ - imx6ul-phytec-phycore-som.dtb.o + imx6ul-phytec-phycore-som.dtb.o \ + imx6ull-phytec-phycore-som.dtb.o pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += kirkwood-openblocks_a6-bb.dtb.o pbl-dtb-$(CONFIG_MACH_RADXA_ROCK) += rk3188-radxarock.dtb.o diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dts b/arch/arm/dts/imx6ul-phytec-phycore-som.dts index 65a936551e..73f7dbe9a6 100644 --- a/arch/arm/dts/imx6ul-phytec-phycore-som.dts +++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dts @@ -13,173 +13,29 @@ /dts-v1/; #include +#include "imx6ul-phytec-phycore-som.dtsi" / { model = "Phytec phyCORE-i.MX6 Ultra Lite SOM"; compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul"; - - chosen { - linux,stdout-path = &uart1; - - environment-nand { - compatible = "barebox,environment"; - device-path = &gpmi, "partname:barebox-environment"; - status = "disabled"; - }; - - environment-sd1 { - compatible = "barebox,environment"; - device-path = &usdhc1, "partname:barebox-environment"; - status = "disabled"; - }; - }; }; &fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@1 { - reg = <1>; - }; - }; }; &gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - fsl,no-blockmark-swap; status = "okay"; - - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "barebox"; - reg = <0x0 0x400000>; - }; - - partition@400000 { - label = "barebox-environment"; - reg = <0x400000 0x100000>; - }; - - partition@500000 { - label = "root"; - reg = <0x500000 0x0>; - }; }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 =<&pinctrl_i2c1>; - clock-frequency = <100000>; status = "okay"; - - eeprom@52 { - compatible = "cat,24c32"; - reg = <0x52>; - }; }; &uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; &usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; status = "okay"; - - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "barebox"; - reg = <0x0 0xe0000>; - }; - - partition@e0000 { - label = "barebox-environment"; - reg = <0xe0000 0x20000>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - - imx6ul-phytec-phycore-som { - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 - MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 - MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 - MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 - MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 - MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 - MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 - MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 - MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 - MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 - MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 - MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 - MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 - MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 - MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 - >; - }; - - pinctrl_i2c1: i2cgrp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ - >; - }; - }; }; diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi new file mode 100644 index 0000000000..96beef4e72 --- /dev/null +++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi @@ -0,0 +1,178 @@ +/* + * Copyright (C) 2016 PHYTEC Messtechnik GmbH + * Author: Christian Hemp + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/ { + chosen { + linux,stdout-path = &uart1; + + environment-nand { + compatible = "barebox,environment"; + device-path = &gpmi, "partname:barebox-environment"; + status = "disabled"; + }; + + environment-sd1 { + compatible = "barebox,environment"; + device-path = &usdhc1, "partname:barebox-environment"; + status = "disabled"; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "disabled"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + reg = <1>; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + fsl,no-blockmark-swap; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x400000>; + }; + + partition@400000 { + label = "barebox-environment"; + reg = <0x400000 0x100000>; + }; + + partition@500000 { + label = "root"; + reg = <0x500000 0x0>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 =<&pinctrl_i2c1>; + clock-frequency = <100000>; + status = "disabled"; + + eeprom@52 { + compatible = "cat,24c32"; + reg = <0x52>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx6ul-phytec-phycore-som { + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 + >; + }; + + pinctrl_i2c1: i2cgrp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ + >; + }; + }; +}; diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som.dts b/arch/arm/dts/imx6ull-phytec-phycore-som.dts new file mode 100644 index 0000000000..de04132a02 --- /dev/null +++ b/arch/arm/dts/imx6ull-phytec-phycore-som.dts @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2017 PHYTEC Messtechnik GmbH + * Author: Stefan Riedmueller + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6ul-phytec-phycore-som.dtsi" + +/ { + model = "Phytec phyCORE-i.MX6 ULL SOM"; + compatible = "phytec,imx6ul-pcl063", "fsl,imx6ull"; +}; + +&fec1 { + status = "okay"; +}; + +&gpmi { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; diff --git a/images/Makefile.imx b/images/Makefile.imx index cdad2e0b88..6ee44f2e90 100644 --- a/images/Makefile.imx +++ b/images/Makefile.imx @@ -435,6 +435,11 @@ CFG_start_phytec_phycore_imx6ul_som_512mb.pblx.imximg = $(board)/phytec-som-imx6 FILE_barebox-phytec-phycore-imx6ul-512mb.img = start_phytec_phycore_imx6ul_som_512mb.pblx.imximg image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-phycore-imx6ul-512mb.img +pblx-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_phycore_imx6ull_som_256mb +CFG_start_phytec_phycore_imx6ull_som_256mb.pblx.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pcl063-256mb.imxcfg +FILE_barebox-phytec-phycore-imx6ull-256mb.img = start_phytec_phycore_imx6ull_som_256mb.pblx.imximg +image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-phycore-imx6ull-256mb.img + pblx-$(CONFIG_MACH_GW_VENTANA) += start_imx6q_gw54xx_1gx64 CFG_start_imx6q_gw54xx_1gx64.pblx.imximg = $(board)/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg FILE_barebox-gateworks-imx6q-ventana-1gx64.img = start_imx6q_gw54xx_1gx64.pblx.imximg -- cgit v1.2.3 From e41410467318c9601446fae1390104488b2bd7c8 Mon Sep 17 00:00:00 2001 From: Christian Hemp Date: Fri, 19 May 2017 16:02:37 +0200 Subject: imx-bbu-nand-fcb: add support for imx6ull The i.MX 6ull secures the fcb with bch 40. This is identical to i.MX 6ul. Signed-off-by: Christian Hemp Signed-off-by: Sascha Hauer --- common/imx-bbu-nand-fcb.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/common/imx-bbu-nand-fcb.c b/common/imx-bbu-nand-fcb.c index 5d3d3f7e93..7218c5e1cc 100644 --- a/common/imx-bbu-nand-fcb.c +++ b/common/imx-bbu-nand-fcb.c @@ -441,7 +441,7 @@ static int read_fcb(struct mtd_info *mtd, int num, struct fcb_block **retfcb) goto err; } - if (cpu_is_mx6ul()) + if (cpu_is_mx6ul() || cpu_is_mx6ull()) fcb = read_fcb_bch(rawpage, 40); else fcb = read_fcb_hamming_13_8(rawpage); @@ -899,8 +899,8 @@ static int imx_bbu_write_fcbs_dbbts(struct mtd_info *mtd, struct fcb_block *fcb) fcb_raw_page = xzalloc(mtd->writesize + mtd->oobsize); - if (cpu_is_mx6ul()) { - /* 40 bit BCH, for i.MX6UL */ + if (cpu_is_mx6ul() || cpu_is_mx6ull()) { + /* 40 bit BCH, for i.MX6UL(L) */ encode_bch_ecc(fcb_raw_page + 32, fcb, 40); } else { memcpy(fcb_raw_page + 12, fcb, sizeof(struct fcb_block)); -- cgit v1.2.3 From 4fd1c4aa8a6ccd15d391543c98d1b2863766d4f4 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 29 May 2017 22:02:41 +0200 Subject: ARM: imx6: gw54xx: add function to retrieve board revision from GSC This parses the board revision from the GSC EEPROm model string. Signed-off-by: Lucas Stach Signed-off-by: Sascha Hauer --- arch/arm/boards/gateworks-ventana/gsc.c | 14 ++++++++++++++ arch/arm/boards/gateworks-ventana/gsc.h | 2 ++ 2 files changed, 16 insertions(+) diff --git a/arch/arm/boards/gateworks-ventana/gsc.c b/arch/arm/boards/gateworks-ventana/gsc.c index 3614230482..92244d12da 100644 --- a/arch/arm/boards/gateworks-ventana/gsc.c +++ b/arch/arm/boards/gateworks-ventana/gsc.c @@ -65,3 +65,17 @@ int gsc_i2c_write(struct i2c_client *client, u32 addr, const u8 *buf, u16 count) return ret; } + +char gsc_get_rev(struct i2c_client *client) +{ + int i; + u8 model[16]; + + gsc_i2c_read(client, 0x30, model, 16); + for (i = sizeof(model) - 1; i > 0; i--) { + if (model[i] >= 'A') + return model[i]; + } + + return 'A'; +} diff --git a/arch/arm/boards/gateworks-ventana/gsc.h b/arch/arm/boards/gateworks-ventana/gsc.h index a6e7e2232d..13f226265c 100644 --- a/arch/arm/boards/gateworks-ventana/gsc.h +++ b/arch/arm/boards/gateworks-ventana/gsc.h @@ -56,3 +56,5 @@ */ int gsc_i2c_read(struct i2c_client *client, u32 addr, u8 *buf, u16 count); int gsc_i2c_write(struct i2c_client *client, u32 addr, const u8 *buf, u16 count); + +char gsc_get_rev(struct i2c_client *client); -- cgit v1.2.3 From 80585aec967ab753f63fd9fc84906640a4b63655 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 29 May 2017 22:02:42 +0200 Subject: ARM: imx6: gw54xx: fixup watchdog nodes on pre rev E boards Older boards before revision E don't have the external watchdog signal wired up to the PMIC, so they must use watchdog 1, which is able to reset the SoC internally. Signed-off-by: Lucas Stach Signed-off-by: Sascha Hauer --- arch/arm/boards/gateworks-ventana/board.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boards/gateworks-ventana/board.c b/arch/arm/boards/gateworks-ventana/board.c index 82dba7c93d..3ff142ee42 100644 --- a/arch/arm/boards/gateworks-ventana/board.c +++ b/arch/arm/boards/gateworks-ventana/board.c @@ -24,6 +24,19 @@ #include "gsc.h" +static int gw54xx_wdog_of_fixup(struct device_node *root, void *context) +{ + struct device_node *np; + + /* switch to the watchdog with internal reset capabilities */ + np = of_find_node_by_name(root, "wdog@020c0000"); + of_device_disable(np); + np = of_find_node_by_name(root, "wdog@020bc000"); + of_device_enable(np); + + return 0; +} + static int gw54xx_devices_init(void) { struct i2c_client client; @@ -60,6 +73,10 @@ static int gw54xx_devices_init(void) of_eth_register_ethaddr(dnode, mac); } + /* boards before rev E don't have the external watchdog signal */ + if (gsc_get_rev(&client) < 'E') + of_register_fixup(gw54xx_wdog_of_fixup, NULL); + imx6_bbu_nand_register_handler("nand", BBU_HANDLER_FLAG_DEFAULT); barebox_set_hostname("gw54xx"); -- cgit v1.2.3 From 0d53a13cb36e579485c9ade7b8b1cd9c213690f1 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 29 May 2017 22:17:46 +0200 Subject: ARM: imx6: gw54xx: use wdog1 for barebox As Barebox isn't changing the external PMIC power rails the internal watchdog reset is fine for the Barebox reset purposes. Watchdog 2 is only usable on boards with revision E or later, as this on is incapable of executing an internal reset. Signed-off-by: Lucas Stach Signed-off-by: Sascha Hauer --- arch/arm/dts/imx6q-gw54xx.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/imx6q-gw54xx.dts b/arch/arm/dts/imx6q-gw54xx.dts index 8113542c66..ec0f3632ba 100644 --- a/arch/arm/dts/imx6q-gw54xx.dts +++ b/arch/arm/dts/imx6q-gw54xx.dts @@ -22,3 +22,11 @@ &sata { status = "okay"; }; + +&wdog1 { + status = "okay"; +}; + +&wdog2 { + status = "disabled"; +}; -- cgit v1.2.3 From 9b0d878e34b7c4912661e5938a4bbf5d364e88ef Mon Sep 17 00:00:00 2001 From: Michael Grzeschik Date: Fri, 2 Jun 2017 15:18:06 +0200 Subject: ARM: i.MX: setup ENET_TX_CLK_DIR in imx6_init for every imx6ul We generically enable the output of ENET_TX_CLK. It will be output if ENET_REF_CLK is selected. Signed-off-by: Michael Grzeschik Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/imx6.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c index 7b3fc1da27..5afbf6b30f 100644 --- a/arch/arm/mach-imx/imx6.c +++ b/arch/arm/mach-imx/imx6.c @@ -121,6 +121,16 @@ void imx6_setup_ipu_qos(void) } } +void imx6ul_enet_clk_init(void) +{ + void __iomem *gprbase = IOMEM(MX6_IOMUXC_BASE_ADDR) + 0x4000; + uint32_t val; + + val = readl(gprbase + IOMUXC_GPR1); + val |= (0x3 << 17); + writel(val, gprbase + IOMUXC_GPR1); +} + int imx6_init(void) { const char *cputypestr; @@ -159,6 +169,7 @@ int imx6_init(void) break; case IMX6_CPUTYPE_IMX6UL: cputypestr = "i.MX6 UltraLite"; + imx6ul_enet_clk_init(); break; case IMX6_CPUTYPE_IMX6ULL: cputypestr = "i.MX6 ULL"; -- cgit v1.2.3 From 83538c10291d0e93de954d2b18887981c72df620 Mon Sep 17 00:00:00 2001 From: Michael Grzeschik Date: Fri, 2 Jun 2017 15:18:07 +0200 Subject: ARM: phytec-som-imx6: remove needles enet refclk setup All REF_CLK output setup now is generically prepared for imx6ul. The handling of the ENET_CLK_SEL (gpr[13]|gpr[14]) bits is not necessary, as 0 is their reset value. Signed-off-by: Michael Grzeschik Signed-off-by: Sascha Hauer --- arch/arm/boards/phytec-som-imx6/board.c | 23 ++++------------------- 1 file changed, 4 insertions(+), 19 deletions(-) diff --git a/arch/arm/boards/phytec-som-imx6/board.c b/arch/arm/boards/phytec-som-imx6/board.c index b93fd1be60..cb397779c4 100644 --- a/arch/arm/boards/phytec-som-imx6/board.c +++ b/arch/arm/boards/phytec-som-imx6/board.c @@ -96,24 +96,6 @@ int ksz8081_phy_fixup(struct phy_device *phydev) return 0; } -static void imx6ul_setup_fec(void) -{ - void __iomem *gprbase = IOMEM(MX6_IOMUXC_BASE_ADDR) + 0x4000; - uint32_t val; - - phy_register_fixup_for_uid(PHY_ID_KSZ8081, MICREL_PHY_ID_MASK, - ksz8081_phy_fixup); - - val = readl(gprbase + IOMUXC_GPR1); - /* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]*/ - val &= ~(1 << 13); - val |= (1 << 17); - /* Use 50M anatop loopback REF_CLK1 for ENET2, clear gpr1[14], set gpr1[18]*/ - val &= ~(1 << 14); - val |= (1 << 18); - writel(val, gprbase + IOMUXC_GPR1); -} - static int physom_imx6_devices_init(void) { int ret; @@ -153,7 +135,10 @@ static int physom_imx6_devices_init(void) barebox_set_hostname("phyCORE-i.MX6UL"); default_environment_path = "/chosen/environment-nand"; default_envdev = "NAND flash"; - imx6ul_setup_fec(); + + phy_register_fixup_for_uid(PHY_ID_KSZ8081, MICREL_PHY_ID_MASK, + ksz8081_phy_fixup); + } else return 0; -- cgit v1.2.3 From cd79610404ef65fc77cac3359cb9b9f4c1d87b39 Mon Sep 17 00:00:00 2001 From: Michael Grzeschik Date: Wed, 7 Jun 2017 12:34:21 +0200 Subject: i.MX: fec: add post PHY reset delay DT property Some PHY require to wait for a bit after the reset GPIO has been toggled. This adds support for the DT property `phy-reset-post-delay` which gives the delay in milliseconds to wait after reset. If the DT property is not given, no delay is observed. Post reset delay greater than 1000ms are invalid. Signed-off-by: Michael Grzeschik Signed-off-by: Sascha Hauer --- drivers/net/fec_imx.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/net/fec_imx.c b/drivers/net/fec_imx.c index 8cf7c4fbda..d506fd64f1 100644 --- a/drivers/net/fec_imx.c +++ b/drivers/net/fec_imx.c @@ -743,7 +743,7 @@ static int fec_probe(struct device_d *dev) int ret; enum fec_type type; int phy_reset; - u32 msec = 1; + u32 msec = 1, phy_post_delay = 0; u64 start; ret = dev_get_drvdata(dev, (const void **)&type); @@ -781,6 +781,11 @@ static int fec_probe(struct device_d *dev) phy_reset = of_get_named_gpio(dev->device_node, "phy-reset-gpios", 0); if (gpio_is_valid(phy_reset)) { of_property_read_u32(dev->device_node, "phy-reset-duration", &msec); + of_property_read_u32(dev->device_node, "phy-reset-post-delay", + &phy_post_delay); + /* valid reset duration should be less than 1s */ + if (phy_post_delay > 1000) + goto release_res; ret = gpio_request(phy_reset, "phy-reset"); if (ret) @@ -792,6 +797,9 @@ static int fec_probe(struct device_d *dev) mdelay(msec); gpio_set_value(phy_reset, 1); + + if (phy_post_delay) + mdelay(phy_post_delay); } /* Reset chip. */ -- cgit v1.2.3 From 5f7e0d15333e016100a37b7d38c50d5d4a3b3c85 Mon Sep 17 00:00:00 2001 From: Michael Grzeschik Date: Wed, 7 Jun 2017 12:34:22 +0200 Subject: ARM: i.MX6: add Technexion Pico Hobbit support This adds support for the i.MX6UL Technexion Pico Hobbit. The board comes with different amounts of RAM. We create one image for the 256MB and one for the 512MB variant. Signed-off-by: Michael Grzeschik --- v1 -> v2: - removed already prepared clock setup v2 -> v3: - added phy-reset-post-delay as the support is now available Signed-off-by: Michael Grzeschik Signed-off-by: Sascha Hauer --- arch/arm/boards/Makefile | 1 + arch/arm/boards/technexion-pico-hobbit/Makefile | 7 ++ arch/arm/boards/technexion-pico-hobbit/board.c | 63 +++++++++++++++++ .../defaultenv-pico-hobbit/init/automount | 11 +++ .../defaultenv-pico-hobbit/network/eth1 | 18 +++++ .../flash-header-imx6ul-pico-hobbit-256.imxcfg | 64 ++++++++++++++++++ .../flash-header-imx6ul-pico-hobbit-512.imxcfg | 65 ++++++++++++++++++ arch/arm/boards/technexion-pico-hobbit/lowlevel.c | 78 ++++++++++++++++++++++ arch/arm/configs/imx_v7_defconfig | 1 + arch/arm/dts/Makefile | 1 + arch/arm/dts/imx6ul-pico-hobbit.dts | 35 ++++++++++ arch/arm/mach-imx/Kconfig | 6 ++ images/Makefile.imx | 10 +++ 13 files changed, 360 insertions(+) create mode 100644 arch/arm/boards/technexion-pico-hobbit/Makefile create mode 100644 arch/arm/boards/technexion-pico-hobbit/board.c create mode 100644 arch/arm/boards/technexion-pico-hobbit/defaultenv-pico-hobbit/init/automount create mode 100644 arch/arm/boards/technexion-pico-hobbit/defaultenv-pico-hobbit/network/eth1 create mode 100644 arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-256.imxcfg create mode 100644 arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-512.imxcfg create mode 100644 arch/arm/boards/technexion-pico-hobbit/lowlevel.c create mode 100644 arch/arm/dts/imx6ul-pico-hobbit.dts diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index 0ecfb3e4b3..f2d4d38785 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -115,6 +115,7 @@ obj-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += terasic-de0-nano-soc/ obj-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += terasic-sockit/ obj-$(CONFIG_MACH_SOLIDRUN_CUBOX) += solidrun-cubox/ obj-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += solidrun-microsom/ +obj-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += technexion-pico-hobbit/ obj-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += technexion-wandboard/ obj-$(CONFIG_MACH_TNY_A9260) += tny-a926x/ obj-$(CONFIG_MACH_TNY_A9263) += tny-a926x/ diff --git a/arch/arm/boards/technexion-pico-hobbit/Makefile b/arch/arm/boards/technexion-pico-hobbit/Makefile new file mode 100644 index 0000000000..b60dcd2bc1 --- /dev/null +++ b/arch/arm/boards/technexion-pico-hobbit/Makefile @@ -0,0 +1,7 @@ +obj-y += board.o +lwl-y += lowlevel.o +extra-y += flash-header-imx6ul-pico-hobbit-256.dcd.S \ + flash-header-imx6ul-pico-hobbit-256.dcd \ + flash-header-imx6ul-pico-hobbit-512.dcd.S \ + flash-header-imx6ul-pico-hobbit-512.dcd +bbenv-y += defaultenv-pico-hobbit diff --git a/arch/arm/boards/technexion-pico-hobbit/board.c b/arch/arm/boards/technexion-pico-hobbit/board.c new file mode 100644 index 0000000000..d3109fc390 --- /dev/null +++ b/arch/arm/boards/technexion-pico-hobbit/board.c @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2017 Michael Grzeschik, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +static int ksz8081_phy_fixup(struct phy_device *dev) +{ + phy_write(dev, 0x1f, 0x8190); + phy_write(dev, 0x16, 0x202); + + return 0; +} + +static int pico_hobbit_device_init(void) +{ + if (!of_machine_is_compatible("technexion,imx6ul-pico-hobbit")) + return 0; + + phy_register_fixup_for_uid(PHY_ID_KSZ8081, MICREL_PHY_ID_MASK, + ksz8081_phy_fixup); + + imx6_bbu_internal_mmc_register_handler("emmc", "/dev/mmc0.barebox", + BBU_HANDLER_FLAG_DEFAULT); + + barebox_set_hostname("pico-hobbit"); + + defaultenv_append_directory(defaultenv_pico_hobbit); + + return 0; +} +device_initcall(pico_hobbit_device_init); diff --git a/arch/arm/boards/technexion-pico-hobbit/defaultenv-pico-hobbit/init/automount b/arch/arm/boards/technexion-pico-hobbit/defaultenv-pico-hobbit/init/automount new file mode 100644 index 0000000000..fdcfa36045 --- /dev/null +++ b/arch/arm/boards/technexion-pico-hobbit/defaultenv-pico-hobbit/init/automount @@ -0,0 +1,11 @@ +#!/bin/sh + +# automount tftp server based on $eth1.serverip + +mkdir -p /mnt/tftp +automount /mnt/tftp 'ifup eth1 && mount -t tftp $eth1.serverip /mnt/tftp' + +# automount nfs server's nfsroot + +mkdir -p /mnt/nfs +automount /mnt/nfs 'ifup eth1 && mount -t nfs ${eth1.serverip}:/home/${global.user}/nfsroot/${global.hostname} /mnt/nfs' diff --git a/arch/arm/boards/technexion-pico-hobbit/defaultenv-pico-hobbit/network/eth1 b/arch/arm/boards/technexion-pico-hobbit/defaultenv-pico-hobbit/network/eth1 new file mode 100644 index 0000000000..dfe63971df --- /dev/null +++ b/arch/arm/boards/technexion-pico-hobbit/defaultenv-pico-hobbit/network/eth1 @@ -0,0 +1,18 @@ +#!/bin/sh + +# ip setting (static/dhcp) +ip=dhcp +global.dhcp.vendor_id=barebox-${global.hostname} + +# static setup used if ip=static +ipaddr= +netmask= +gateway= +serverip= + +# MAC address if needed +#ethaddr=xx:xx:xx:xx:xx:xx + +# put code to discover eth1 (i.e. 'usb') to /env/network/eth1-discover + +exit 0 diff --git a/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-256.imxcfg b/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-256.imxcfg new file mode 100644 index 0000000000..12cda04e60 --- /dev/null +++ b/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-256.imxcfg @@ -0,0 +1,64 @@ +loadaddr 0x80000000 +soc imx6 +dcdofs 0x400 + +wm 32 0x020c4068 0xffffffff +wm 32 0x020c406c 0xffffffff +wm 32 0x020c4070 0xffffffff +wm 32 0x020c4074 0xffffffff +wm 32 0x020c4078 0xffffffff +wm 32 0x020c407c 0xffffffff +wm 32 0x020c4080 0xffffffff + +wm 32 0x020E04B4 0x000C0000 +wm 32 0x020E04AC 0x00000000 +wm 32 0x020E027C 0x00000030 +wm 32 0x020E0250 0x00000030 +wm 32 0x020E024C 0x00000030 +wm 32 0x020E0490 0x00000030 +wm 32 0x020E0288 0x00000030 +wm 32 0x020E0270 0x00000000 +wm 32 0x020E0260 0x00000030 +wm 32 0x020E0264 0x00000030 +wm 32 0x020E04A0 0x00000030 +wm 32 0x020E0494 0x00020000 +wm 32 0x020E0280 0x00000030 +wm 32 0x020E0284 0x00000030 +wm 32 0x020E04B0 0x00020000 +wm 32 0x020E0498 0x00000030 +wm 32 0x020E04A4 0x00000030 +wm 32 0x020E0244 0x00000030 +wm 32 0x020E0248 0x00000030 +wm 32 0x021B001C 0x00008000 +wm 32 0x021B0800 0xA1390003 +wm 32 0x021B080C 0x00000000 +wm 32 0x021B083C 0x01380134 +wm 32 0x021B0848 0x40404244 +wm 32 0x021B0850 0x40405050 +wm 32 0x021B081C 0x33333333 +wm 32 0x021B0820 0x33333333 +wm 32 0x021B082C 0xf3333333 +wm 32 0x021B0830 0xf3333333 +wm 32 0x021B08C0 0x00921012 +wm 32 0x021B08b8 0x00000800 +wm 32 0x021B0004 0x0002002D +wm 32 0x021B0008 0x00333030 +wm 32 0x021B000C 0x676B52F3 +wm 32 0x021B0010 0xB66D8B63 +wm 32 0x021B0014 0x01FF00DB +wm 32 0x021B0018 0x00201740 +wm 32 0x021B001C 0x00008000 +wm 32 0x021B002C 0x000026D2 +wm 32 0x021B0030 0x006B1023 +wm 32 0x021B0040 0x00000047 +wm 32 0x021B0000 0x83180000 +wm 32 0x021B001C 0x02008032 +wm 32 0x021B001C 0x00008033 +wm 32 0x021B001C 0x00048031 +wm 32 0x021B001C 0x15208030 +wm 32 0x021B001C 0x04008040 +wm 32 0x021B0020 0x00000800 +wm 32 0x021B0818 0x00000227 +wm 32 0x021B0004 0x0002552D +wm 32 0x021B0404 0x00011006 +wm 32 0x021B001C 0x00000000 diff --git a/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-512.imxcfg b/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-512.imxcfg new file mode 100644 index 0000000000..0a1915b982 --- /dev/null +++ b/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-512.imxcfg @@ -0,0 +1,65 @@ +loadaddr 0x80000000 +soc imx6 +dcdofs 0x400 + +wm 32 0x020c4068 0xffffffff +wm 32 0x020c406c 0xffffffff +wm 32 0x020c4070 0xffffffff +wm 32 0x020c4074 0xffffffff +wm 32 0x020c4078 0xffffffff +wm 32 0x020c407c 0xffffffff +wm 32 0x020c4080 0xffffffff + +wm 32 0x020E04B4 0x000C0000 +wm 32 0x020E04AC 0x00000000 +wm 32 0x020E027C 0x00000030 +wm 32 0x020E0250 0x00000030 +wm 32 0x020E024C 0x00000030 +wm 32 0x020E0490 0x00000030 +wm 32 0x020E0288 0x00000030 +wm 32 0x020E0270 0x00000000 +wm 32 0x020E0260 0x00000030 +wm 32 0x020E0264 0x00000030 +wm 32 0x020E04A0 0x00000030 +wm 32 0x020E0494 0x00020000 +wm 32 0x020E0280 0x00000030 +wm 32 0x020E0284 0x00000030 +wm 32 0x020E04B0 0x00020000 +wm 32 0x020E0498 0x00000030 +wm 32 0x020E04A4 0x00000030 +wm 32 0x020E0244 0x00000030 +wm 32 0x020E0248 0x00000030 +wm 32 0x021B001C 0x00008000 +wm 32 0x021B0800 0xA1390003 +wm 32 0x021B080C 0x00000000 +wm 32 0x021B083C 0x41570155 +wm 32 0x021B0848 0x4040474A +wm 32 0x021B0850 0x40405550 +wm 32 0x021B081C 0x33333333 +wm 32 0x021B0820 0x33333333 +wm 32 0x021B082C 0xf3333333 +wm 32 0x021B0830 0xf3333333 +wm 32 0x021B08C0 0x00921012 +wm 32 0x021B08b8 0x00000800 +wm 32 0x021B0004 0x0002002D +wm 32 0x021B0008 0x1b333030 +wm 32 0x021B000C 0x676B52F3 +wm 32 0x021B0010 0xB66D0B63 +wm 32 0x021B0014 0x01FF00DB +wm 32 0x021B0018 0x00201740 +wm 32 0x021B001C 0x00008000 +wm 32 0x021B002C 0x000026D2 +wm 32 0x021B0030 0x006B1023 +wm 32 0x021B0040 0x0000004f +wm 32 0x021B0000 0x84180000 +wm 32 0x021B0890 0x23400a38 +wm 32 0x021B001C 0x02008032 +wm 32 0x021B001C 0x00008033 +wm 32 0x021B001C 0x00048031 +wm 32 0x021B001C 0x15208030 +wm 32 0x021B001C 0x04008040 +wm 32 0x021B0020 0x00000800 +wm 32 0x021B0818 0x00000227 +wm 32 0x021B0004 0x0002552D +wm 32 0x021B0404 0x00011006 +wm 32 0x021B001C 0x00000000 diff --git a/arch/arm/boards/technexion-pico-hobbit/lowlevel.c b/arch/arm/boards/technexion-pico-hobbit/lowlevel.c new file mode 100644 index 0000000000..aad55127bf --- /dev/null +++ b/arch/arm/boards/technexion-pico-hobbit/lowlevel.c @@ -0,0 +1,78 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MX6_UART6_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x7C000) + +static inline void setup_uart(void) +{ + void __iomem *iomuxbase = IOMEM(MX6_IOMUXC_BASE_ADDR); + void __iomem *uart = IOMEM(MX6_UART6_BASE_ADDR); + + imx6_ungate_all_peripherals(); + + writel(0x8, iomuxbase + 0x1d4); + writel(0x1b0b1, iomuxbase + 0x0460); + writel(0x8, iomuxbase + 0x1d8); + writel(0x1b0b1, iomuxbase + 0x0460); + + imx6_uart_setup(uart); + pbl_set_putc(imx_uart_putc, uart); + + putc_ll('>'); +} + +static void __noreturn start_imx6_pico_hobbit_common(uint32_t size, + bool do_early_uart_config, + void *fdt_blob_fixed_offset) +{ + void *fdt; + + arm_cpu_lowlevel_init(); + + arm_setup_stack(0x00910000 - 8); + + arm_early_mmu_cache_invalidate(); + + relocate_to_current_adr(); + setup_c(); + barrier(); + + if (do_early_uart_config && IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(); + + /* disable all watchdog powerdown counters */ + writew(0x0, 0x020bc008); + writew(0x0, 0x020c0008); + writew(0x0, 0x021e4008); + + fdt = fdt_blob_fixed_offset - get_runtime_offset(); + + imx6ul_barebox_entry(fdt); +} + +BAREBOX_IMD_TAG_STRING(pico_hobbit_mx6_memsize_SZ_256M, IMD_TYPE_PARAMETER, "memsize=256", 0); +BAREBOX_IMD_TAG_STRING(pico_hobbit_mx6_memsize_SZ_512M, IMD_TYPE_PARAMETER, "memsize=512", 0); + +#define EDM1_ENTRY(name, fdt_name, memory_size, do_early_uart_config) \ + ENTRY_FUNCTION(name, r0, r1, r2) \ + { \ + extern char __dtb_##fdt_name##_start[]; \ + \ + IMD_USED(pico_hobbit_mx6_memsize_##memory_size); \ + \ + start_imx6_pico_hobbit_common(memory_size, do_early_uart_config, \ + __dtb_##fdt_name##_start); \ + } + +EDM1_ENTRY(start_imx6ul_pico_hobbit_256mb, imx6ul_pico_hobbit, SZ_256M, true); +EDM1_ENTRY(start_imx6ul_pico_hobbit_512mb, imx6ul_pico_hobbit, SZ_512M, true); diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig index ab837cc55f..7bbd93240d 100644 --- a/arch/arm/configs/imx_v7_defconfig +++ b/arch/arm/configs/imx_v7_defconfig @@ -23,6 +23,7 @@ CONFIG_MACH_SABRESD=y CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB=y CONFIG_MACH_NITROGEN6=y CONFIG_MACH_SOLIDRUN_MICROSOM=y +CONFIG_MACH_TECHNEXION_PICO_HOBBIT=y CONFIG_MACH_TECHNEXION_WANDBOARD=y CONFIG_MACH_EMBEST_RIOTBOARD=y CONFIG_MACH_UDOO=y diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ec291ce6bf..806d386001 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -75,6 +75,7 @@ pbl-dtb-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += imx6dl-hummingboard.dtb.o imx6q-humm imx6dl-hummingboard2.dtb.o imx6q-hummingboard2.dtb.o \ imx6q-h100.dtb.o pbl-dtb-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += imx6q-wandboard.dtb.o imx6dl-wandboard.dtb.o +pbl-dtb-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += imx6ul-pico-hobbit.dtb.o pbl-dtb-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += tegra20-colibri-iris.dtb.o pbl-dtb-$(CONFIG_MACH_TOSHIBA_AC100) += tegra20-paz00.dtb.o pbl-dtb-$(CONFIG_MACH_TQMA53) += imx53-mba53.dtb.o diff --git a/arch/arm/dts/imx6ul-pico-hobbit.dts b/arch/arm/dts/imx6ul-pico-hobbit.dts new file mode 100644 index 0000000000..478b2411b4 --- /dev/null +++ b/arch/arm/dts/imx6ul-pico-hobbit.dts @@ -0,0 +1,35 @@ +#include + +/ { + chosen { + linux,stdout-path = &uart1; + + environment@0 { + compatible = "barebox,environment"; + device-path = &environment_usdhc1; + }; + }; + + memory { + /delete-property/ device_type; + }; +}; + +&usdhc1 { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xc0000>; + }; + + environment_usdhc1: partition@c0000 { + label = "barebox-environment"; + reg = <0xc0000 0x40000>; + }; +}; + +&fec2 { + phy-reset-post-delay = <1>; +}; diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 80f53ce124..6110924af6 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -343,6 +343,12 @@ config MACH_SOLIDRUN_MICROSOM bool "SolidRun MicroSOM based devices" select ARCH_IMX6 +config MACH_TECHNEXION_PICO_HOBBIT + bool "Technexion Pico Hobbit" + select ARCH_IMX6 + select ARCH_IMX6UL + select ARM_USE_COMPRESSED_DTB + config MACH_TECHNEXION_WANDBOARD bool "Technexion Wandboard" select ARCH_IMX6 diff --git a/images/Makefile.imx b/images/Makefile.imx index 6ee44f2e90..88d3e5e339 100644 --- a/images/Makefile.imx +++ b/images/Makefile.imx @@ -315,6 +315,16 @@ CFG_start_h100_microsom_i2ex.pblx.imximg = $(board)/solidrun-microsom/flash-head FILE_barebox-auvidea-h100-microsom-i2eX.img = start_h100_microsom_i2ex.pblx.imximg image-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += barebox-auvidea-h100-microsom-i2eX.img +pblx-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += start_imx6ul_pico_hobbit_256mb +CFG_start_imx6ul_pico_hobbit_256mb.pblx.imximg = $(board)/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-256.imxcfg +FILE_barebox-imx6ul-pico-hobbit-256mb.img = start_imx6ul_pico_hobbit_256mb.pblx.imximg +image-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += barebox-imx6ul-pico-hobbit-256mb.img + +pblx-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += start_imx6ul_pico_hobbit_512mb +CFG_start_imx6ul_pico_hobbit_512mb.pblx.imximg = $(board)/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-512.imxcfg +FILE_barebox-imx6ul-pico-hobbit-512mb.img = start_imx6ul_pico_hobbit_512mb.pblx.imximg +image-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += barebox-imx6ul-pico-hobbit-512mb.img + pblx-$(CONFIG_MACH_NITROGEN6) += start_imx6q_nitrogen6x_1g CFG_start_imx6q_nitrogen6x_1g.pblx.imximg = $(board)/boundarydevices-nitrogen6/flash-header-nitrogen6q-1g.imxcfg FILE_barebox-boundarydevices-imx6q-nitrogen6x-1g.img = start_imx6q_nitrogen6x_1g.pblx.imximg -- cgit v1.2.3 From 8b1b75441d415de7c73b6f68dd2e29b7e0ead9fb Mon Sep 17 00:00:00 2001 From: Juergen Borleis Date: Wed, 7 Jun 2017 12:45:42 +0200 Subject: i.MX/WD: setup the watchdog according to its datasheet From earlier SoCs like the i.MX21 up to i.MX7 their datasheets states after reset the watchdog timer has to be set first prior enabling the watchdog itself. This change do it this way. Signed-off-by: Juergen Borleis Signed-off-by: Sascha Hauer --- drivers/watchdog/imxwd.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/watchdog/imxwd.c b/drivers/watchdog/imxwd.c index b920c7234b..5cc178f3e8 100644 --- a/drivers/watchdog/imxwd.c +++ b/drivers/watchdog/imxwd.c @@ -114,6 +114,12 @@ static int imx21_watchdog_set_timeout(struct imx_wd *priv, unsigned timeout) if (priv->ext_reset) val |= IMX21_WDOG_WCR_WDT; + /* + * set time and some write once bits first prior enabling the + * watchdog according to the datasheet + */ + writew(val, priv->base + IMX21_WDOG_WCR); + writew(IMX21_WDOG_WCR_WDE | val, priv->base + IMX21_WDOG_WCR); /* Write Service Sequence */ -- cgit v1.2.3 From 46078f8d9917164a148cd2ad156e7e061505f8d4 Mon Sep 17 00:00:00 2001 From: Alexander Kurz Date: Thu, 8 Jun 2017 20:41:34 +0200 Subject: ARM: i.MX6 Wandboard: dont do MMDC Write Leveling Calibration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The hardware requirements to perform a write leveling calibration are not fulfilled by the Wandboard modules. IMX6DQRM ยง44.11.6 "Write leveling Calibration" Note2 states that the first bit of each data byte group (D0, D8, ..., D56) from memory must be connected to the same data bus bit on the controller, which is not given on the Wandboard modules, resulting in unpredictable calib results and breaking the WBQUAD 2GiB SDRAM setup. Similar restrictions exist for the i.MX6SD. Remove this calibration and use the MPWLDECTRL defaults. Signed-off-by: Alexander Kurz Signed-off-by: Sascha Hauer --- arch/arm/boards/technexion-wandboard/lowlevel.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boards/technexion-wandboard/lowlevel.c b/arch/arm/boards/technexion-wandboard/lowlevel.c index d3eb9a03e9..ff5ae6d510 100644 --- a/arch/arm/boards/technexion-wandboard/lowlevel.c +++ b/arch/arm/boards/technexion-wandboard/lowlevel.c @@ -276,7 +276,6 @@ static unsigned long wandboard_dram_init(void) __udelay(100); - mmdc_do_write_level_calibration(); mmdc_do_dqs_calibration(); #ifdef DEBUG mmdc_print_calibration_results(); -- cgit v1.2.3 From f3d0bf23329bb0f4f20189b82e87c839056e4299 Mon Sep 17 00:00:00 2001 From: Alexander Kurz Date: Thu, 8 Jun 2017 20:41:35 +0200 Subject: ARM: i.MX6 Wandboard Quad: fix PBL UART MUX Three variants of the Wandboard exist: WBSOLO, WBDUAL and WBQUAD. For all variants, the external serial port is connected to UART1 via PAD_CSI0_DATA10 (TX) and PAD_CSI0_DATA11 (RX). Unfortunately, the IOMUX register adresses for this mux differ between i.MX6Q (WBQUAD) and others. Make the UART IOMUX for PBL compatible for WBQUAD. Signed-off-by: Alexander Kurz Signed-off-by: Sascha Hauer --- arch/arm/boards/technexion-wandboard/lowlevel.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/arch/arm/boards/technexion-wandboard/lowlevel.c b/arch/arm/boards/technexion-wandboard/lowlevel.c index ff5ae6d510..9aae429d45 100644 --- a/arch/arm/boards/technexion-wandboard/lowlevel.c +++ b/arch/arm/boards/technexion-wandboard/lowlevel.c @@ -285,11 +285,25 @@ static unsigned long wandboard_dram_init(void) static void setup_uart(void) { + int cpu_type = __imx6_cpu_type(); void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR; - /* mux the uart */ - writel(0x00000003, iomuxbase + 0x4c); - writel(0x00000000, iomuxbase + 0x8fc); + /* mux UART1 TX on PAD_CSI0_DATA10 */ + switch (cpu_type) { + case IMX6_CPUTYPE_IMX6S: + case IMX6_CPUTYPE_IMX6DL: + writel(0x00000003, iomuxbase + 0x4c); + writel(0x0001b0b1, iomuxbase + 0x360); + writel(0x00000000, iomuxbase + 0x8fc); + break; + case IMX6_CPUTYPE_IMX6Q: + writel(0x00000003, iomuxbase + 0x280); + writel(0x0001b0b1, iomuxbase + 0x650); + writel(0x00000001, iomuxbase + 0x920); + break; + default: + return; + } imx6_ungate_all_peripherals(); imx6_uart_setup((void *)MX6_UART1_BASE_ADDR); -- cgit v1.2.3 From 9e99b950e6cd2e8a52929d4c9444f5d40df2a1c5 Mon Sep 17 00:00:00 2001 From: Alexander Kurz Date: Thu, 8 Jun 2017 20:41:36 +0200 Subject: ARM: i.MX6 Wandboard: enable Wandboard Quad Extend the DT compatibility check to actually use the Wandboard Quad. Signed-off-by: Alexander Kurz Signed-off-by: Sascha Hauer --- arch/arm/boards/technexion-wandboard/board.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boards/technexion-wandboard/board.c b/arch/arm/boards/technexion-wandboard/board.c index e7b51cc728..2e1f6254c2 100644 --- a/arch/arm/boards/technexion-wandboard/board.c +++ b/arch/arm/boards/technexion-wandboard/board.c @@ -63,7 +63,8 @@ static int ar8031_phy_fixup(struct phy_device *dev) static int wandboard_device_init(void) { - if (!of_machine_is_compatible("wand,imx6dl-wandboard")) + if (!of_machine_is_compatible("wand,imx6dl-wandboard") && + !of_machine_is_compatible("wand,imx6q-wandboard")) return 0; phy_register_fixup_for_uid(PHY_ID_AR8031, AR_PHY_ID_MASK, ar8031_phy_fixup); -- cgit v1.2.3 From 332eedd6e75c57c3f4acea1b3045f628a7a2f349 Mon Sep 17 00:00:00 2001 From: Alexander Kurz Date: Thu, 8 Jun 2017 20:41:37 +0200 Subject: ARM: i.MX6 Wandboard: add Documentation Signed-off-by: Alexander Kurz Signed-off-by: Sascha Hauer --- Documentation/boards/imx/Wandboard.rst | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 Documentation/boards/imx/Wandboard.rst diff --git a/Documentation/boards/imx/Wandboard.rst b/Documentation/boards/imx/Wandboard.rst new file mode 100644 index 0000000000..574318a009 --- /dev/null +++ b/Documentation/boards/imx/Wandboard.rst @@ -0,0 +1,21 @@ +Wandboard +========= + +The Wandboard is a carrier board available with three different +System-on-Module options, the Wandboard Solo (i.MX6S, 512MiB DDR3), +the Wandboard Dual (i.MX6DL, 1GiB DDR3) and Wandboard Quad (i.MX6Q, 2GiB DDR3). + +The device boots from the SD card slot on the System-on-Module board, it +will not boot from the slot on the carrier board. + +To boot barebox on any wandboard, build imx_v7_defconfig +and copy the barebox imx-image to the i.MX boot location of a SD card, e.g. +dd bs=1024 skip=1 seek=1 if=images/barebox-imx6-wandboard.img of=/dev/mmcblk0 + +Only one image exists, supporting all three Wandboard variants, barebox will +detect the Wandboard variant depending on the SoC variant. +This image is only usable for SD-boot. It will not boot via imx-usb-loader. + +Connect to the serial port using a null-modem cable to get console access. + +For further documentation, including board schematics see http://wandboard.org/ -- cgit v1.2.3