From 6350676e551000836b2fd1235a18a34a708f6eec Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 17 Feb 2014 21:27:39 +0100 Subject: tegra: add lowlevel DVC Allows to talk to external PMIC devices to bring up CPU rail. Signed-off-by: Lucas Stach Signed-off-by: Sascha Hauer --- arch/arm/mach-tegra/include/mach/lowlevel-dvc.h | 72 +++++++++++++++++++++++++ arch/arm/mach-tegra/include/mach/lowlevel.h | 7 ++- arch/arm/mach-tegra/include/mach/tegra20-car.h | 8 +++ 3 files changed, 86 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-tegra/include/mach/lowlevel-dvc.h diff --git a/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h b/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h new file mode 100644 index 0000000000..f7f6328f65 --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2014 Lucas Stach + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include "mach/tegra20-car.h" +#include "mach/lowlevel.h" + +static __always_inline +void tegra_dvc_init(void) +{ + int div; + u32 reg; + + /* reset DVC controller and enable clock */ + writel(CRC_RST_DEV_H_DVC, TEGRA_CLK_RESET_BASE + CRC_RST_DEV_H_SET); + reg = readl(TEGRA_CLK_RESET_BASE + CRC_CLK_OUT_ENB_H); + reg |= CRC_CLK_OUT_ENB_H_DVC; + writel(reg, TEGRA_CLK_RESET_BASE + CRC_CLK_OUT_ENB_H); + + /* set DVC I2C clock source to CLK_M and aim for 100kHz I2C clock */ + div = ((tegra_get_osc_clock() * 3) >> 22) - 1; + writel((div) | (3 << 30), + TEGRA_CLK_RESET_BASE + CRC_CLK_SOURCE_DVC); + + /* clear DVC reset */ + tegra_ll_delay_usec(3); + writel(CRC_RST_DEV_H_DVC, TEGRA_CLK_RESET_BASE + CRC_RST_DEV_H_CLR); +} + +#define TEGRA_I2C_CNFG 0x00 +#define TEGRA_I2C_CMD_ADDR0 0x04 +#define TEGRA_I2C_CMD_DATA1 0x0c +#define TEGRA_I2C_SEND_2_BYTES 0x0a02 + +static __always_inline +void tegra_dvc_write_addr(u32 addr, u32 config) +{ + writel(addr, TEGRA_DVC_BASE + TEGRA_I2C_CMD_ADDR0); + writel(config, TEGRA_DVC_BASE + TEGRA_I2C_CNFG); +} + +static __always_inline +void tegra_dvc_write_data(u32 data, u32 config) +{ + writel(data, TEGRA_DVC_BASE + TEGRA_I2C_CMD_DATA1); + writel(config, TEGRA_DVC_BASE + TEGRA_I2C_CNFG); +} + +static inline __attribute__((always_inline)) +void tegra30_tps65911_cpu_rail_enable(void) +{ + tegra_dvc_write_addr(0x5a, 2); + /* reg 28, 600mV + (35-3) * 12,5mV = 1,0V */ + tegra_dvc_write_data(0x2328, TEGRA_I2C_SEND_2_BYTES); + tegra_ll_delay_usec(1000); + /* reg 27, VDDctrl enable */ + tegra_dvc_write_data(0x0127, TEGRA_I2C_SEND_2_BYTES); + tegra_ll_delay_usec(10 * 1000); +} diff --git a/arch/arm/mach-tegra/include/mach/lowlevel.h b/arch/arm/mach-tegra/include/mach/lowlevel.h index 935559a4bb..cc346a023d 100644 --- a/arch/arm/mach-tegra/include/mach/lowlevel.h +++ b/arch/arm/mach-tegra/include/mach/lowlevel.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Lucas Stach + * Copyright (C) 2013-2014 Lucas Stach * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -21,6 +21,9 @@ * be used by both the main CPU complex (ARMv7) and the AVP (ARMv4). */ +#ifndef __TEGRA_LOWLEVEL_H +#define __TEGRA_LOWLEVEL_H + #include #include #include @@ -237,3 +240,5 @@ void tegra_avp_reset_vector(uint32_t boarddata); /* reset vector for the main CPU complex */ void tegra_maincomplex_entry(void); + +#endif /* __TEGRA_LOWLEVEL_H */ diff --git a/arch/arm/mach-tegra/include/mach/tegra20-car.h b/arch/arm/mach-tegra/include/mach/tegra20-car.h index 64873d79b9..a5441de0a9 100644 --- a/arch/arm/mach-tegra/include/mach/tegra20-car.h +++ b/arch/arm/mach-tegra/include/mach/tegra20-car.h @@ -46,6 +46,9 @@ #define CRC_CLK_OUT_ENB_L_AC97 (1 << 3) #define CRC_CLK_OUT_ENB_L_CPU (1 << 0) +#define CRC_CLK_OUT_ENB_H 0x014 +#define CRC_CLK_OUT_ENB_H_DVC (1 << 15) + #define CRC_CCLK_BURST_POLICY 0x020 #define CRC_CCLK_BURST_POLICY_SYS_STATE_SHIFT 28 #define CRC_CCLK_BURST_POLICY_SYS_STATE_FIQ 8 @@ -273,6 +276,11 @@ #define CRC_RST_DEV_L_CLR 0x304 +#define CRC_RST_DEV_H_SET 0x308 +#define CRC_RST_DEV_H_DVC (1 << 15) + +#define CRC_RST_DEV_H_CLR 0x30c + #define CRC_RST_CPU_CMPLX_SET 0x340 #define CRC_RST_CPU_CMPLX_CLR 0x344 -- cgit v1.2.3