From 6f58e5cac9742a48ef9e1022eaf6e6b1dbae9b96 Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Thu, 20 Oct 2016 15:40:06 +0200 Subject: nand: imx6: Changed default NAND clock The Barebox recognized false bad erase blocks while booting from a Spansion NAND (1). This error occurred due a to high clock. The Kernel sets the default NAND clock to 22Mhz. So, to fix this error and to be more identical with the Kernel, the Barebox should be too. 1: nand: NAND device: Manufacturer ID: 0x01, Chip ID: 0xd3 (AMD/Spansion S34ML08G2), 1024MiB, page size: 2048, OOB size: 128 Signed-off-by: Daniel Schultz Tested-by: Stefan Lengfeld Signed-off-by: Christian Hemp Signed-off-by: Sascha Hauer --- drivers/mtd/nand/nand_mxs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/nand_mxs.c b/drivers/mtd/nand/nand_mxs.c index 01aa06333a..fe955e8af4 100644 --- a/drivers/mtd/nand/nand_mxs.c +++ b/drivers/mtd/nand/nand_mxs.c @@ -2145,7 +2145,7 @@ static int mxs_nand_probe(struct device_d *dev) if (mxs_nand_is_imx6(nand_info)) { clk_disable(nand_info->clk); - clk_set_rate(nand_info->clk, 96000000); + clk_set_rate(nand_info->clk, 22000000); clk_enable(nand_info->clk); nand_info->dma_channel_base = 0; } else { -- cgit v1.2.3