From 978f2c8becb9bb76712e274814ab01bd9a0f4f62 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Thu, 20 Sep 2018 23:01:00 -0700 Subject: ARM: nxp-imx8mq-evk: Add FEC's PHY configuration code Add appropriate DT and PHY fixup code needed for i.MX8MQ EVK board. Signed-off-by: Andrey Smirnov Signed-off-by: Sascha Hauer --- arch/arm/boards/nxp-imx8mq-evk/board.c | 24 ++++++++++++++++++++++++ arch/arm/dts/imx8mq-evk.dts | 1 + 2 files changed, 25 insertions(+) diff --git a/arch/arm/boards/nxp-imx8mq-evk/board.c b/arch/arm/boards/nxp-imx8mq-evk/board.c index 3645e5e71b..aae6970d8c 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/board.c +++ b/arch/arm/boards/nxp-imx8mq-evk/board.c @@ -21,8 +21,30 @@ #include #include #include +#include #include +#include + +#define PHY_ID_AR8031 0x004dd074 +#define AR_PHY_ID_MASK 0xffffffff + +static int ar8031_phy_fixup(struct phy_device *phydev) +{ + /* + * Enable 1.8V(SEL_1P5_1P8_POS_REG) on + * Phy control debug reg 0 + */ + phy_write(phydev, 0x1d, 0x1f); + phy_write(phydev, 0x1e, 0x8); + + /* rgmii tx clock delay enable */ + phy_write(phydev, 0x1d, 0x05); + phy_write(phydev, 0x1e, 0x100); + + return 0; +} + static int imx8mq_evk_mem_init(void) { if (!of_machine_is_compatible("fsl,imx8mq-evk")) @@ -45,6 +67,8 @@ static int nxp_imx8mq_evk_init(void) imx8mq_bbu_internal_mmc_register_handler("eMMC", "/dev/mmc0", 0); + phy_register_fixup_for_uid(PHY_ID_AR8031, AR_PHY_ID_MASK, + ar8031_phy_fixup); return 0; } device_initcall(nxp_imx8mq_evk_init); diff --git a/arch/arm/dts/imx8mq-evk.dts b/arch/arm/dts/imx8mq-evk.dts index 3ac13baa18..d6d5d843ca 100644 --- a/arch/arm/dts/imx8mq-evk.dts +++ b/arch/arm/dts/imx8mq-evk.dts @@ -43,6 +43,7 @@ <&pinctrl_fec1_data_tx>, <&pinctrl_fec1_data_rx>, <&pinctrl_fec1_phy_reset>; phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; status = "okay"; }; -- cgit v1.2.3