From a6b696108ce99d375c8f2ee03d77c7ecefb1b948 Mon Sep 17 00:00:00 2001 From: Stefan Müller-Klieser Date: Tue, 7 Oct 2014 10:40:36 +0200 Subject: boards: Add phytec-phyflex-am335x MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for PHYTEC's phyFLEX-AM335x. Signed-off-by: Stefan Müller-Klieser [clean ups] Signed-off-by: Teresa Gámez Signed-off-by: Sascha Hauer --- arch/arm/boards/Makefile | 1 + arch/arm/boards/phytec-phyflex-am335x/Makefile | 3 + arch/arm/boards/phytec-phyflex-am335x/board.c | 100 ++++++ .../defaultenv-phyflex-am335x/boot/mmc | 8 + .../defaultenv-phyflex-am335x/boot/nand | 8 + .../defaultenv-phyflex-am335x/boot/spi | 8 + .../defaultenv-phyflex-am335x/config-board | 17 + arch/arm/boards/phytec-phyflex-am335x/lowlevel.c | 180 +++++++++++ arch/arm/dts/Makefile | 1 + arch/arm/dts/am335x-phytec-phyflex.dts | 356 +++++++++++++++++++++ arch/arm/mach-omap/Kconfig | 5 + images/Makefile.am33xx | 12 + 12 files changed, 699 insertions(+) create mode 100644 arch/arm/boards/phytec-phyflex-am335x/Makefile create mode 100644 arch/arm/boards/phytec-phyflex-am335x/board.c create mode 100644 arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/boot/mmc create mode 100644 arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/boot/nand create mode 100644 arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/boot/spi create mode 100644 arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/config-board create mode 100644 arch/arm/boards/phytec-phyflex-am335x/lowlevel.c create mode 100644 arch/arm/dts/am335x-phytec-phyflex.dts diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index c80b9c920a..25045ac6ad 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -79,6 +79,7 @@ obj-$(CONFIG_MACH_PCM038) += phytec-phycore-imx27/ obj-$(CONFIG_MACH_PCM043) += phytec-phycore-imx35/ obj-$(CONFIG_MACH_PCM049) += phytec-phycore-omap4460/ obj-$(CONFIG_MACH_PCM051) += phytec-phycore-am335x/ +obj-$(CONFIG_MACH_PFLA03) += phytec-phyflex-am335x/ obj-$(CONFIG_MACH_PHYTEC_PFLA02) += phytec-phyflex-imx6/ obj-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += plathome-openblocks-ax3/ obj-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += plathome-openblocks-a6/ diff --git a/arch/arm/boards/phytec-phyflex-am335x/Makefile b/arch/arm/boards/phytec-phyflex-am335x/Makefile new file mode 100644 index 0000000000..54734b5736 --- /dev/null +++ b/arch/arm/boards/phytec-phyflex-am335x/Makefile @@ -0,0 +1,3 @@ +lwl-y += lowlevel.o +obj-y += board.o +bbenv-y += defaultenv-phyflex-am335x diff --git a/arch/arm/boards/phytec-phyflex-am335x/board.c b/arch/arm/boards/phytec-phyflex-am335x/board.c new file mode 100644 index 0000000000..12fad8f998 --- /dev/null +++ b/arch/arm/boards/phytec-phyflex-am335x/board.c @@ -0,0 +1,100 @@ +/* + * pfla03 - phyFLEX-AM335x Board Initalization Code + * + * Copyright (C) 2014 Stefan Müller-Klieser, Phytec Messtechnik GmbH + * + * Based on arch/arm/boards/omap/board-beagle.c + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int ksz9031rn_phy_fixup(struct phy_device *dev) +{ + phy_write_mmd_indirect(dev, 6, 2, 0); + phy_write_mmd_indirect(dev, 8, 2, 0x003ff); + + return 0; +} + +static int pfla03_coredevice_init(void) +{ + if (!of_machine_is_compatible("phytec,phyflex-am335x-som")) + return 0; + + phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK, + ksz9031rn_phy_fixup); + am33xx_register_ethaddr(0, 0); + am33xx_register_ethaddr(1, 1); + + return 0; +} +coredevice_initcall(pfla03_coredevice_init); + +static struct omap_barebox_part pfla03_barebox_part = { + .nand_offset = SZ_512K, + .nand_size = SZ_512K, + .nor_offset = SZ_128K, + .nor_size = SZ_512K, +}; + +static char *xloadslots[] = { + "/dev/nand0.xload.bb", + "/dev/nand0.xload_backup1.bb", + "/dev/nand0.xload_backup2.bb", + "/dev/nand0.xload_backup3.bb" +}; + +static int pfla03_devices_init(void) +{ + if (!of_machine_is_compatible("phytec,phyflex-am335x-som")) + return 0; + + switch (bootsource_get()) { + case BOOTSOURCE_SPI: + of_device_enable_path("/chosen/environment-spi"); + break; + case BOOTSOURCE_MMC: + omap_set_bootmmc_devname("mmc0"); + break; + default: + of_device_enable_path("/chosen/environment-nand"); + break; + } + + omap_set_barebox_part(&pfla03_barebox_part); + armlinux_set_architecture(MACH_TYPE_PFLA03); + defaultenv_append_directory(defaultenv_phyflex_am335x); + + am33xx_bbu_spi_nor_mlo_register_handler("MLO.spi", "/dev/m25p0.xload"); + am33xx_bbu_spi_nor_register_handler("spi", "/dev/m25p0.barebox"); + am33xx_bbu_nand_xloadslots_register_handler("MLO.nand", + xloadslots, ARRAY_SIZE(xloadslots)); + am33xx_bbu_nand_register_handler("nand", "/dev/nand0.barebox.bb"); + + return 0; +} +device_initcall(pfla03_devices_init); diff --git a/arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/boot/mmc b/arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/boot/mmc new file mode 100644 index 0000000000..6a6076101e --- /dev/null +++ b/arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/boot/mmc @@ -0,0 +1,8 @@ +#!/bin/sh + +global.bootm.image=/boot/linuximage +#global.bootm.oftree=/boot/oftree + +bootargs-ip + +global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootfstype=ext3 rw rootwait" diff --git a/arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/boot/nand b/arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/boot/nand new file mode 100644 index 0000000000..d9ef1455ee --- /dev/null +++ b/arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/boot/nand @@ -0,0 +1,8 @@ +#!/bin/sh + +global.bootm.image="/dev/nand0.kernel.bb" +#global.bootm.oftree="/env/oftree" + +bootargs-ip + +global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root,2048 rw rootfstype=ubifs" diff --git a/arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/boot/spi b/arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/boot/spi new file mode 100644 index 0000000000..c87299a9ea --- /dev/null +++ b/arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/boot/spi @@ -0,0 +1,8 @@ +#!/bin/sh + +global.bootm.image="/dev/m25p0.kernel" + +bootargs-ip + +# Use rootfs form NAND for now as rootfs partition < 4MB +global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root,2048 rw rootfstype=ubifs" diff --git a/arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/config-board b/arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/config-board new file mode 100644 index 0000000000..b620ac1aba --- /dev/null +++ b/arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/config-board @@ -0,0 +1,17 @@ +#!/bin/sh + +# board defaults, do not change in running system. Change /env/config +# instead + +global.hostname=pfla03 +global.linux.bootargs.base="console=ttyO0,115200" + +if [ $bootsource = mmc ]; then + global.boot.default="mmc nand spi net" +elif [ $boosource = nand ]; then + global.boot.default="nand spi mmc net" +elif [ $boosource = spi ]; then + global.boot.default="spi nand mmc net" +elif [ $boosource = net ]; then + global.boot.default="net nand spi mmc" +fi diff --git a/arch/arm/boards/phytec-phyflex-am335x/lowlevel.c b/arch/arm/boards/phytec-phyflex-am335x/lowlevel.c new file mode 100644 index 0000000000..4d34968a0b --- /dev/null +++ b/arch/arm/boards/phytec-phyflex-am335x/lowlevel.c @@ -0,0 +1,180 @@ +/* + * pfla03 - phyFLEX-AM335x lowlevel code + * + * Copyright (C) 2014 Stefan Müller-Klieser, Phytec Messtechnik GmbH + * + * Based on arch/arm/boards/omap/board-beagle.c + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CLK_M_OSC_MHZ 25 +#define DDR_IOCTRL 0x18B + +static const struct am33xx_cmd_control pfla03_cmd = { + .slave_ratio0 = 0x80, + .dll_lock_diff0 = 0x0, + .invert_clkout0 = 0x0, + .slave_ratio1 = 0x80, + .dll_lock_diff1 = 0x0, + .invert_clkout1 = 0x0, + .slave_ratio2 = 0x80, + .dll_lock_diff2 = 0x0, + .invert_clkout2 = 0x0, +}; + +struct pfla03_sdram_timings { + struct am33xx_emif_regs regs; + struct am33xx_ddr_data data; +}; + +enum { + MT41K128M16JT_256MB, + MT41K256M16HA_512MB, +}; + +struct pfla03_sdram_timings pfla03_timings[] = { + /* 256 MB */ + [MT41K128M16JT_256MB] = { + .regs = { + .emif_read_latency = 0x7, + .emif_tim1 = 0x0AAAD4DB, + .emif_tim2 = 0x26437FDA, + .emif_tim3 = 0x501F83FF, + .sdram_config = 0x61C052B2, + .zq_config = 0x50074BE4, + .sdram_ref_ctrl = 0x00000C30, + }, + .data = { + .rd_slave_ratio0 = 0x34, + .wr_dqs_slave_ratio0 = 0x47, + .fifo_we_slave_ratio0 = 0x9a, + .wr_slave_ratio0 = 0x7e, + .use_rank0_delay = 0x0, + .dll_lock_diff0 = 0x0, + }, + }, + /* 512 MB */ + [MT41K256M16HA_512MB] = { + .regs = { + .emif_read_latency = 0x7, + .emif_tim1 = 0x0AAAE4DB, + .emif_tim2 = 0x266B7FDA, + .emif_tim3 = 0x501F867F, + .sdram_config = 0x61C05332, + .zq_config = 0x50074BE4, + .sdram_ref_ctrl = 0x00000C30, + }, + .data = { + .rd_slave_ratio0 = 0x36, + .wr_dqs_slave_ratio0 = 0x47, + .fifo_we_slave_ratio0 = 0x95, + .wr_slave_ratio0 = 0x7f, + .use_rank0_delay = 0x0, + .dll_lock_diff0 = 0x0, + }, + }, +}; + +extern char __dtb_am335x_phytec_phyflex_start[]; + +/** + * @brief The basic entry point for board initialization. + * + * This is called as part of machine init (after arch init). + * This is again called with stack in SRAM, so not too many + * constructs possible here. + * + * @return void + */ +static noinline void pfla03_board_init(int sdram) +{ + void *fdt; + struct pfla03_sdram_timings *timing = &pfla03_timings[sdram]; + + /* + * WDT1 is already running when the bootloader gets control + * Disable it to avoid "random" resets + */ + writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR)); + while (readl(AM33XX_WDT_REG(WWPS)) != 0x0); + + writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR)); + while (readl(AM33XX_WDT_REG(WWPS)) != 0x0); + + am33xx_pll_init(MPUPLL_M_600, CLK_M_OSC_MHZ, DDRPLL_M_400); + + am335x_sdram_init(DDR_IOCTRL, &pfla03_cmd, + &timing->regs, + &timing->data); + + am33xx_uart_soft_reset((void *)AM33XX_UART0_BASE); + am33xx_enable_uart0_pin_mux(); + omap_uart_lowlevel_init((void *)AM33XX_UART0_BASE); + putc_ll('>'); + + fdt = __dtb_am335x_phytec_phyflex_start - get_runtime_offset(); + + am335x_barebox_entry(fdt); +} + +static noinline void pfla03_board_entry(unsigned long bootinfo, int sdram) +{ + am33xx_save_bootinfo((void *)bootinfo); + + arm_cpu_lowlevel_init(); + + /* + * Setup C environment, the board init code uses global variables. + * Stackpointer has already been initialized by the ROM code. + */ + relocate_to_current_adr(); + setup_c(); + + pfla03_board_init(sdram); +} + +ENTRY_FUNCTION(start_am33xx_phytec_phyflex_sram_256mb, bootinfo, r1, r2) +{ + pfla03_board_entry(bootinfo, MT41K128M16JT_256MB); +} + +ENTRY_FUNCTION(start_am33xx_phytec_phyflex_sram_512mb, bootinfo, r1, r2) +{ + pfla03_board_entry(bootinfo, MT41K256M16HA_512MB); +} + +ENTRY_FUNCTION(start_am33xx_phytec_phyflex_sdram, r0, r1, r2) +{ + void *fdt; + + fdt = __dtb_am335x_phytec_phyflex_start - get_runtime_offset(); + + am335x_barebox_entry(fdt); +} diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 3fcd5f1cc0..e9e74d19de 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -27,6 +27,7 @@ pbl-dtb-$(CONFIG_MACH_PCA100) += imx27-phytec-phycard-s-rdk-bb.dtb.o pbl-dtb-$(CONFIG_MACH_PCAAXL3) += imx6q-phytec-pbaa03.dtb.o pbl-dtb-$(CONFIG_MACH_PCM038) += imx27-phytec-phycore-rdk.dtb.o pbl-dtb-$(CONFIG_MACH_PCM051) += am335x-phytec-phycore.dtb.o +pbl-dtb-$(CONFIG_MACH_PFLA03) += am335x-phytec-phyflex.dtb.o pbl-dtb-$(CONFIG_MACH_PHYTEC_PFLA02) += imx6s-phytec-pbab01.dtb.o imx6dl-phytec-pbab01.dtb.o imx6q-phytec-pbab01.dtb.o pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += kirkwood-openblocks_a6-bb.dtb.o diff --git a/arch/arm/dts/am335x-phytec-phyflex.dts b/arch/arm/dts/am335x-phytec-phyflex.dts new file mode 100644 index 0000000000..4dde3286cb --- /dev/null +++ b/arch/arm/dts/am335x-phytec-phyflex.dts @@ -0,0 +1,356 @@ +/dts-v1/; + +#include "am33xx.dtsi" + +/ { + model = "Phytec phyFLEX AM335x"; + compatible = "phytec,phyflex-am335x-som", "ti,am33xx"; + + chosen { + linux,stdout-path = &uart0; + + environment-spi { + compatible = "barebox,environment"; + device-path = &flash, "partname:bareboxenv"; + status = "disabled"; + }; + + environment-nand { + compatible = "barebox,environment"; + device-path = &nand, "partname:bareboxenv"; + status = "disabled"; + }; + }; + + vcc5v: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; + + vcc3v3: fixedregulator@1 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; +}; + +&am33xx_pinmux { + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda */ + 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl */ + >; + }; + + spi0_pins: pinmux_spi0_pins { + pinctrl-single,pins = < + 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_clk.spi0_clk */ + 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_d0.spi0_d0 */ + 0x158 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */ + 0x15c (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd */ + 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + 0x0f0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3 */ + 0x0f4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2 */ + 0x0f8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1 */ + 0x0fc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0 */ + 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk */ + 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd */ + >; + }; + + emac_rgmii1_pins: pinmux_emac_rgmii1_pins { + pinctrl-single,pins = < + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_tx_en.rgmii1_tctl */ + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rx_dv.rgmii1_rctl */ + 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ + 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ + 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_tx_clk.rgmii1_tclk */ + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rx_clk.rgmii1_rclk */ + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ + >; + }; + + emac_rmii2_pins: pinmux_emac_rmii2_pins { + pinctrl-single,pins = < + 0x040 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a0.rmii2_txen */ + 0x050 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a4.rmii2_txd1 */ + 0x054 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a5.rmii2_txd0 */ + 0x068 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* gpmc_a10.rmii2_rxd1 */ + 0x06c (PIN_INPUT_PULLDOWN | MUX_MODE3) /* gpmc_a11.rmii2_rxd0 */ + 0x074 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wpn.rmii2_rxer */ + 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_col.rmii2_refclk */ + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data */ + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk */ + >; + }; + + nandflash_pins_s0: nandflash_pins_s0 { + pinctrl-single,pins = < + 0x000 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0 */ + 0x004 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1 */ + 0x008 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2 */ + 0x00c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3 */ + 0x010 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4 */ + 0x014 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5 */ + 0x018 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6 */ + 0x01c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7 */ + 0x070 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */ + 0x07c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_csn0 */ + 0x090 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_advn_ale */ + 0x094 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_oen_ren */ + 0x098 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_wen */ + 0x09c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_be0n_cle */ + >; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + clock-frequency = <400000>; + + tps: pmic@2d { + reg = <0x2d>; + }; + + at24c32: eeprom@52 { + compatible = "atmel,24c32"; + byte_len = <4096>; + pagesize = <32>; + reg = <0x52>; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + status = "okay"; + flash: m25p80 { + compatible = "m25p80"; + spi-max-frequency = <48000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + m25p,fast-read; + + partition@0 { + label = "xload"; + reg = <0x0 0x20000>; + }; + + partition@1 { + label = "barebox"; + reg = <0x20000 0x80000>; + }; + + partition@2 { + label = "bareboxenv"; + reg = <0xa0000 0x20000>; + }; + + partition@3 { + label = "oftree"; + reg = <0xc0000 0x20000>; + }; + + partition@4 { + label = "kernel"; + reg = <0xe0000 0x400000>; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + status = "okay"; +}; + +&phy_sel { + rmii-clock-ext; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <1>; + phy-mode = "rgmii"; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <2>; + phy-mode = "rmii"; + dual_emac_res_vlan = <2>; +}; + +&mac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii1_pins &emac_rmii2_pins>; + dual_emac; + status = "okay"; +}; + +&elm { + status = "okay"; +}; + +&gpmc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nandflash_pins_s0>; + ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ + nand: nand@0,0 { + reg = <0 0 0>; /* CS0, offset 0 */ + nand-bus-width = <8>; + ti,nand-ecc-opt = "bch8"; + gpmc,device-nand = "true"; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <30>; + gpmc,cs-wr-off-ns = <30>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <30>; + gpmc,adv-wr-off-ns = <30>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <20>; + gpmc,oe-on-ns = <10>; + gpmc,oe-off-ns = <30>; + gpmc,access-ns = <30>; + gpmc,rd-cycle-ns = <30>; + gpmc,wr-cycle-ns = <30>; + gpmc,wait-pin = <1>; + gpmc,wait-on-read = "true"; + gpmc,wait-on-write = "true"; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <50>; + gpmc,clk-activation-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,wr-access-ns = <0>; + gpmc,wr-data-mux-bus-ns = <0>; + + #address-cells = <1>; + #size-cells = <1>; + elm_id = <&elm>; + + partition@0 { + label = "xload"; + reg = <0x0 0x20000>; + }; + + partition@1 { + label = "xload_backup1"; + reg = <0x20000 0x20000>; + }; + + partition@2 { + label = "xload_backup2"; + reg = <0x40000 0x20000>; + }; + + partition@3 { + label = "xload_backup3"; + reg = <0x60000 0x20000>; + }; + + partition@4 { + label = "barebox"; + reg = <0x80000 0x80000>; + }; + + partition@5 { + label = "bareboxenv"; + reg = <0x100000 0x20000>; + }; + + partition@6 { + label = "oftree"; + reg = <0x120000 0x20000>; + }; + + partition@7 { + label = "kernel"; + reg = <0x140000 0x800000>; + }; + + partition@8 { + label = "root"; + reg = <0x940000 0x0>; + }; + }; +}; + +/include/ "tps65217.dtsi" +&tps { + vcc1-supply = <&vcc5v>; + vcc2-supply = <&vcc5v>; + vcc3-supply = <&vcc5v>; + vcc4-supply = <&vcc5v>; + vcc5-supply = <&vcc5v>; + vcc6-supply = <&vcc5v>; + vcc7-supply = <&vcc5v>; + vccio-supply = <&vcc5v>; + + regulators { + vdd1_reg: regulator@2 { + /* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1378000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + }; +}; diff --git a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig index e30027ef2e..f9b5ec338f 100644 --- a/arch/arm/mach-omap/Kconfig +++ b/arch/arm/mach-omap/Kconfig @@ -143,6 +143,11 @@ config MACH_PCM051 help Say Y here if you are using Phytecs phyCORE pcm051 board +config MACH_PFLA03 + bool "Phytec phyFLEX am335x pfla03" + select ARCH_AM33XX + help + Say Y here if you are using Phytecs phyFLEX pfla03 board endif choice diff --git a/images/Makefile.am33xx b/images/Makefile.am33xx index 92dd61a5f9..e385135842 100644 --- a/images/Makefile.am33xx +++ b/images/Makefile.am33xx @@ -35,6 +35,18 @@ pblx-$(CONFIG_MACH_PCM051) += start_am33xx_phytec_phycore_sram_2x512mb FILE_barebox-am33xx-phytec-phycore-mlo-2x512mb.img = start_am33xx_phytec_phycore_sram_2x512mb.pblx.mlo am33xx-mlo-$(CONFIG_MACH_PCM051) += barebox-am33xx-phytec-phycore-mlo-2x512mb.img +pblx-$(CONFIG_MACH_PFLA03) += start_am33xx_phytec_phyflex_sdram +FILE_barebox-am33xx-phytec-phyflex.img = start_am33xx_phytec_phyflex_sdram.pblx +am33xx-barebox-$(CONFIG_MACH_PFLA03) += barebox-am33xx-phytec-phyflex.img + +pblx-$(CONFIG_MACH_PFLA03) += start_am33xx_phytec_phyflex_sram_256mb +FILE_barebox-am33xx-phytec-phyflex-mlo-256mb.img = start_am33xx_phytec_phyflex_sram_256mb.pblx.mlo +am33xx-mlo-$(CONFIG_MACH_PFLA03) += barebox-am33xx-phytec-phyflex-mlo-256mb.img + +pblx-$(CONFIG_MACH_PFLA03) += start_am33xx_phytec_phyflex_sram_512mb +FILE_barebox-am33xx-phytec-phyflex-mlo-512mb.img = start_am33xx_phytec_phyflex_sram_512mb.pblx.mlo +am33xx-mlo-$(CONFIG_MACH_PFLA03) += barebox-am33xx-phytec-phyflex-mlo-512mb.img + pblx-$(CONFIG_MACH_BEAGLEBONE) += start_am33xx_beaglebone_sdram FILE_barebox-am33xx-beaglebone.img = start_am33xx_beaglebone_sdram.pblx am33xx-barebox-$(CONFIG_MACH_BEAGLEBONE) += barebox-am33xx-beaglebone.img -- cgit v1.2.3