From 55b6eb741118b2a9f9b577ef150f0007d4bbfc1b Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 27 Apr 2020 11:31:13 +0200 Subject: net: fec_imx: Make ptp clock optional The ptp clock doesn't exist on all SoCs, make it optional. In fact it was optional before due to a bug in the driver. Signed-off-by: Sascha Hauer --- drivers/net/fec_imx.c | 4 ++-- drivers/net/fec_imx.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/fec_imx.c b/drivers/net/fec_imx.c index f814b3b960..585cdcb24c 100644 --- a/drivers/net/fec_imx.c +++ b/drivers/net/fec_imx.c @@ -705,10 +705,10 @@ static int fec_clk_get(struct fec_priv *fec) { int i, err = 0; static const char *clk_names[ARRAY_SIZE(fec->clk)] = { - "ipg", "ahb", "ptp" + "ipg", "ahb", }; static const char *opt_clk_names[ARRAY_SIZE(fec->opt_clk)] = { - "enet_clk_ref", "enet_out", + "enet_clk_ref", "enet_out", "ptp" }; for (i = 0; i < ARRAY_SIZE(fec->clk); i++) { diff --git a/drivers/net/fec_imx.h b/drivers/net/fec_imx.h index d1ac92f0e3..316eefe48f 100644 --- a/drivers/net/fec_imx.h +++ b/drivers/net/fec_imx.h @@ -121,7 +121,6 @@ enum fec_type { enum fec_clock { FEC_CLK_IPG, FEC_CLK_AHB, - FEC_CLK_PTP, FEC_CLK_NUM }; @@ -129,6 +128,7 @@ enum fec_clock { enum fec_opt_clock { FEC_OPT_CLK_REF, FEC_OPT_CLK_OUT, + FEC_OPT_CLK_PTP, FEC_OPT_CLK_NUM }; -- cgit v1.2.3 From 0759f42e35f275e0ead7a63e497b09f8f5ab3395 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 27 Apr 2020 11:31:21 +0200 Subject: net: fec_imx: Return with an error when mandatory clock is missing When a mandatory clock is missing we have to return with an error. Just breaking out of the loop results in ignoring the error. Signed-off-by: Sascha Hauer --- drivers/net/fec_imx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/fec_imx.c b/drivers/net/fec_imx.c index 585cdcb24c..772f930f0d 100644 --- a/drivers/net/fec_imx.c +++ b/drivers/net/fec_imx.c @@ -716,7 +716,7 @@ static int fec_clk_get(struct fec_priv *fec) if (IS_ERR(fec->clk[i])) { err = PTR_ERR(fec->clk[i]); fec_clk_put(fec); - break; + return err; } } -- cgit v1.2.3 From cff8ddcb0ba37a184819e7a50951fe383dd52884 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 27 Apr 2020 16:34:18 +0200 Subject: clk: mxs: Do not enable enet_out clock The enet_out clock gate is wrongly abstracted. The bit it is controlling is not just a bit to enable the clock, it also controls the direction of the ethernet reference clock. When the bit is cleared, the ethernet reference clock must be fed into the SoC from an external oscillator; when it's set then the ethernet reference clock is generated internally. The correct setting depends on the board, so we must not set the bit unconditionally during probe of the clock driver. Whether or not the clock is enabled can be selected by the board by removing the clock from the FEC in its dts. Signed-off-by: Sascha Hauer --- drivers/clk/mxs/clk-imx28.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c index 4adb1c6866..aedd8d4a7c 100644 --- a/drivers/clk/mxs/clk-imx28.c +++ b/drivers/clk/mxs/clk-imx28.c @@ -131,7 +131,6 @@ static int __init mx28_clocks_init(void __iomem *regs) clk_set_rate(clks[ssp2], 96000000); clk_set_rate(clks[ssp3], 96000000); clk_set_parent(clks[lcdif_sel], clks[ref_pix]); - clk_enable(clks[enet_out]); clkdev_add_physbase(clks[ssp0], IMX_SSP0_BASE, NULL); clkdev_add_physbase(clks[ssp1], IMX_SSP1_BASE, NULL); -- cgit v1.2.3 From 222091adb4a738c90fcc2c3c1a664e5252c09bfd Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 28 Apr 2020 12:13:58 +0200 Subject: arm: mxs: Add Kconfig option for device tree boards Boards supporting device tree have to make sure OFTREE and OFDEVICE are selected. Add a convenience option pulling in the right options and select it from the boards. Signed-off-by: Sascha Hauer --- arch/arm/mach-mxs/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig index b3a7c6259c..f7d13569ea 100644 --- a/arch/arm/mach-mxs/Kconfig +++ b/arch/arm/mach-mxs/Kconfig @@ -9,6 +9,11 @@ config ARCH_TEXT_BASE default 0x47000000 if MACH_MX28EVK default 0x47000000 if MACH_CFA10036 +config ARCH_MXS_OF_SUPPORT + bool + select OFTREE + select OFDEVICE + comment "Freescale i.MX System-on-Chip" choice @@ -57,12 +62,14 @@ config MACH_TX28 config MACH_MX28EVK bool "mx28-evk" select MXS_OCOTP + select ARCH_MXS_OF_SUPPORT help Say Y here if you are using the Freescale i.MX28-EVK board config MACH_DUCKBILL bool "Duckbill" select MXS_OCOTP + select ARCH_MXS_OF_SUPPORT help Say Y here if you are using the I2SE Duckbill board -- cgit v1.2.3 From d76f885ee3d9ace2d075cb0638e77d8358d422cf Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 27 Apr 2020 11:31:00 +0200 Subject: clk: mxs: Use device tree provided clock lookups When probing from the device tree use the device tree provided clock lookups. So far we only used the clock lookups based on the physical base address of the device, but these should go sooner or later. Signed-off-by: Sascha Hauer --- arch/arm/mach-mxs/Kconfig | 1 + drivers/clk/mxs/clk-imx28.c | 45 ++++++++++++++++++++++++++------------------- 2 files changed, 27 insertions(+), 19 deletions(-) diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig index f7d13569ea..f4a9d3d422 100644 --- a/arch/arm/mach-mxs/Kconfig +++ b/arch/arm/mach-mxs/Kconfig @@ -11,6 +11,7 @@ config ARCH_TEXT_BASE config ARCH_MXS_OF_SUPPORT bool + select COMMON_CLK_OF_PROVIDER select OFTREE select OFDEVICE diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c index aedd8d4a7c..1dd724c8a6 100644 --- a/drivers/clk/mxs/clk-imx28.c +++ b/drivers/clk/mxs/clk-imx28.c @@ -61,8 +61,9 @@ enum imx28_clk { }; static struct clk *clks[clk_max]; +static struct clk_onecell_data clk_data; -static int __init mx28_clocks_init(void __iomem *regs) +static int __init mx28_clocks_init(struct device_d *dev, void __iomem *regs) { clks[ref_xtal] = clk_fixed("ref_xtal", 24000000); clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000); @@ -132,23 +133,29 @@ static int __init mx28_clocks_init(void __iomem *regs) clk_set_rate(clks[ssp3], 96000000); clk_set_parent(clks[lcdif_sel], clks[ref_pix]); - clkdev_add_physbase(clks[ssp0], IMX_SSP0_BASE, NULL); - clkdev_add_physbase(clks[ssp1], IMX_SSP1_BASE, NULL); - clkdev_add_physbase(clks[ssp2], IMX_SSP2_BASE, NULL); - clkdev_add_physbase(clks[ssp3], IMX_SSP3_BASE, NULL); - clkdev_add_physbase(clks[fec], IMX_FEC0_BASE, NULL); - clkdev_add_physbase(clks[xbus], IMX_DBGUART_BASE, NULL); - clkdev_add_physbase(clks[hbus], IMX_OCOTP_BASE, NULL); - clkdev_add_physbase(clks[hbus], MXS_APBH_BASE, NULL); - clkdev_add_physbase(clks[uart], IMX_UART0_BASE, NULL); - clkdev_add_physbase(clks[uart], IMX_UART1_BASE, NULL); - clkdev_add_physbase(clks[uart], IMX_UART2_BASE, NULL); - clkdev_add_physbase(clks[uart], IMX_UART3_BASE, NULL); - clkdev_add_physbase(clks[uart], IMX_UART4_BASE, NULL); - clkdev_add_physbase(clks[gpmi], MXS_GPMI_BASE, NULL); - clkdev_add_physbase(clks[pwm], IMX_PWM_BASE, NULL); - if (IS_ENABLED(CONFIG_DRIVER_VIDEO_STM)) - clkdev_add_physbase(clks[lcdif_comp], IMX_FB_BASE, NULL); + if (dev->device_node) { + clk_data.clks = clks; + clk_data.clk_num = clk_max; + of_clk_add_provider(dev->device_node, of_clk_src_onecell_get, &clk_data); + } else { + clkdev_add_physbase(clks[ssp0], IMX_SSP0_BASE, NULL); + clkdev_add_physbase(clks[ssp1], IMX_SSP1_BASE, NULL); + clkdev_add_physbase(clks[ssp2], IMX_SSP2_BASE, NULL); + clkdev_add_physbase(clks[ssp3], IMX_SSP3_BASE, NULL); + clkdev_add_physbase(clks[fec], IMX_FEC0_BASE, NULL); + clkdev_add_physbase(clks[xbus], IMX_DBGUART_BASE, NULL); + clkdev_add_physbase(clks[hbus], IMX_OCOTP_BASE, NULL); + clkdev_add_physbase(clks[hbus], MXS_APBH_BASE, NULL); + clkdev_add_physbase(clks[uart], IMX_UART0_BASE, NULL); + clkdev_add_physbase(clks[uart], IMX_UART1_BASE, NULL); + clkdev_add_physbase(clks[uart], IMX_UART2_BASE, NULL); + clkdev_add_physbase(clks[uart], IMX_UART3_BASE, NULL); + clkdev_add_physbase(clks[uart], IMX_UART4_BASE, NULL); + clkdev_add_physbase(clks[gpmi], MXS_GPMI_BASE, NULL); + clkdev_add_physbase(clks[pwm], IMX_PWM_BASE, NULL); + if (IS_ENABLED(CONFIG_DRIVER_VIDEO_STM)) + clkdev_add_physbase(clks[lcdif_comp], IMX_FB_BASE, NULL); + } return 0; } @@ -163,7 +170,7 @@ static int imx28_ccm_probe(struct device_d *dev) return PTR_ERR(iores); regs = IOMEM(iores->start); - mx28_clocks_init(regs); + mx28_clocks_init(dev, regs); return 0; } -- cgit v1.2.3