From c7027459975ac8f573358cf6c5d98bcad01d7791 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 29 Feb 2016 08:10:52 +0100 Subject: dts: update to v4.5-rc5 Signed-off-by: Sascha Hauer --- dts/Bindings/clock/rockchip,rk3036-cru.txt | 2 +- dts/Bindings/interrupt-controller/arm,gic-v3.txt | 5 ++--- dts/Bindings/rtc/s3c-rtc.txt | 6 ++++++ dts/Bindings/serial/fsl-imx-uart.txt | 2 +- dts/include/dt-bindings/clock/tegra210-car.h | 2 +- 5 files changed, 11 insertions(+), 6 deletions(-) diff --git a/dts/Bindings/clock/rockchip,rk3036-cru.txt b/dts/Bindings/clock/rockchip,rk3036-cru.txt index ace05992a2..20df350b9e 100644 --- a/dts/Bindings/clock/rockchip,rk3036-cru.txt +++ b/dts/Bindings/clock/rockchip,rk3036-cru.txt @@ -30,7 +30,7 @@ that they are defined using standard clock bindings with following clock-output-names: - "xin24m" - crystal input - required, - "ext_i2s" - external I2S clock - optional, - - "ext_gmac" - external GMAC clock - optional + - "rmii_clkin" - external EMAC clock - optional Example: Clock controller node: diff --git a/dts/Bindings/interrupt-controller/arm,gic-v3.txt b/dts/Bindings/interrupt-controller/arm,gic-v3.txt index 7803e77d85..007a5b4625 100644 --- a/dts/Bindings/interrupt-controller/arm,gic-v3.txt +++ b/dts/Bindings/interrupt-controller/arm,gic-v3.txt @@ -24,9 +24,8 @@ Main node required properties: 1 = edge triggered 4 = level triggered - Cells 4 and beyond are reserved for future use. When the 1st cell - has a value of 0 or 1, cells 4 and beyond act as padding, and may be - ignored. It is recommended that padding cells have a value of 0. + Cells 4 and beyond are reserved for future use and must have a value + of 0 if present. - reg : Specifies base physical address(s) and size of the GIC registers, in the following order: diff --git a/dts/Bindings/rtc/s3c-rtc.txt b/dts/Bindings/rtc/s3c-rtc.txt index ac2fcd6ff4..1068ffce9f 100644 --- a/dts/Bindings/rtc/s3c-rtc.txt +++ b/dts/Bindings/rtc/s3c-rtc.txt @@ -14,6 +14,10 @@ Required properties: interrupt number is the rtc alarm interrupt and second interrupt number is the rtc tick interrupt. The number of cells representing a interrupt depends on the parent interrupt controller. +- clocks: Must contain a list of phandle and clock specifier for the rtc + and source clocks. +- clock-names: Must contain "rtc" and "rtc_src" entries sorted in the + same order as the clocks property. Example: @@ -21,4 +25,6 @@ Example: compatible = "samsung,s3c6410-rtc"; reg = <0x10070000 0x100>; interrupts = <44 0 45 0>; + clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; }; diff --git a/dts/Bindings/serial/fsl-imx-uart.txt b/dts/Bindings/serial/fsl-imx-uart.txt index 35ae1fb353..ed94c217c9 100644 --- a/dts/Bindings/serial/fsl-imx-uart.txt +++ b/dts/Bindings/serial/fsl-imx-uart.txt @@ -9,7 +9,7 @@ Optional properties: - fsl,uart-has-rtscts : Indicate the uart has rts and cts - fsl,irda-mode : Indicate the uart supports irda mode - fsl,dte-mode : Indicate the uart works in DTE mode. The uart works - is DCE mode by default. + in DCE mode by default. Note: Each uart controller should have an alias correctly numbered in "aliases" node. diff --git a/dts/include/dt-bindings/clock/tegra210-car.h b/dts/include/dt-bindings/clock/tegra210-car.h index 6f45aea49e..0a05b0d36a 100644 --- a/dts/include/dt-bindings/clock/tegra210-car.h +++ b/dts/include/dt-bindings/clock/tegra210-car.h @@ -126,7 +126,7 @@ /* 104 */ /* 105 */ #define TEGRA210_CLK_D_AUDIO 106 -/* 107 ( affects abp -> ape) */ +#define TEGRA210_CLK_APB2APE 107 /* 108 */ /* 109 */ /* 110 */ -- cgit v1.2.3