From d86bbaed71cf8928575b40e4bfa904cded5fa2d2 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Thu, 2 Feb 2023 13:05:24 +0100 Subject: clk: imx8mp: add USB suspend clock Linux added another USB clock to properly describe the controller root and suspend clocks. As new DTs are using this clock to keep the shared gate enabled, access to the USB controller will hang Barebox without support for this clock. Fixes: 0d682a2997a8 ("dts: update to v6.2-rc5") Signed-off-by: Lucas Stach Link: https://lore.barebox.org/20230202120524.469258-1-l.stach@pengutronix.de Signed-off-by: Sascha Hauer --- drivers/clk/imx/clk-imx8mp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index a1611be183..40578c2a4b 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -665,7 +665,8 @@ static int imx8mp_clocks_init(struct device_node *ccm_np) hws[IMX8MP_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk", "uart2", ccm_base + 0x44a0, 0); hws[IMX8MP_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk", "uart3", ccm_base + 0x44b0, 0); hws[IMX8MP_CLK_UART4_ROOT] = imx_clk_hw_gate4("uart4_root_clk", "uart4", ccm_base + 0x44c0, 0); - hws[IMX8MP_CLK_USB_ROOT] = imx_clk_hw_gate4("usb_root_clk", "osc_32k", ccm_base + 0x44d0, 0); + hws[IMX8MP_CLK_USB_ROOT] = imx_clk_hw_gate2_shared2("usb_root_clk", "hsio_axi", ccm_base + 0x44d0, 0); + hws[IMX8MP_CLK_USB_SUSP] = imx_clk_hw_gate2_shared2("usb_suspend_clk", "osc_32k", ccm_base + 0x44d0, 0); hws[IMX8MP_CLK_USB_PHY_ROOT] = imx_clk_hw_gate4("usb_phy_root_clk", "usb_phy_ref", ccm_base + 0x44f0, 0); hws[IMX8MP_CLK_USDHC1_ROOT] = imx_clk_hw_gate4("usdhc1_root_clk", "usdhc1", ccm_base + 0x4510, 0); hws[IMX8MP_CLK_USDHC2_ROOT] = imx_clk_hw_gate4("usdhc2_root_clk", "usdhc2", ccm_base + 0x4520, 0); -- cgit v1.2.3