From e0965c4d5607429141ee4c0d6685878f8526117e Mon Sep 17 00:00:00 2001 From: Juergen Beisert Date: Sat, 12 Mar 2011 20:14:55 +0100 Subject: S3C24xx/NFC: Consider correct NAND page size for boot. When booting from NAND, its important to know the correct page size. When the NAND is used as the boot source, four dedicated pins are used to configure the correct page size and address cycles. These pins can be read back in one of the NFC registers to parametrize the load function. This patch also extends the read routine to support more than four address cycles on demand. BTW: At least some mini2440s are misconfigured to use five address cycles for a NAND device that is known to need only four address cycles. In this case the vendor is at our side: This NAND simply ignores any additional address cycles than required. Signed-off-by: Juergen Beisert Signed-off-by: Sascha Hauer --- arch/arm/boards/a9m2440/a9m2440.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boards/a9m2440') diff --git a/arch/arm/boards/a9m2440/a9m2440.c b/arch/arm/boards/a9m2440/a9m2440.c index 764cd65325..39b52761c5 100644 --- a/arch/arm/boards/a9m2440/a9m2440.c +++ b/arch/arm/boards/a9m2440/a9m2440.c @@ -182,7 +182,7 @@ device_initcall(a9m2440_devices_init); #ifdef CONFIG_S3C24XX_NAND_BOOT void __bare_init nand_boot(void) { - s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0, 512); + s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0); } #endif -- cgit v1.2.3