From 9a56bfa95d3ca167fba04eacc0421c39efbbdd8a Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 7 Aug 2015 14:24:54 +0200 Subject: ARM: MMU: Fix order when flushing inner/outer cache When flushing the cache L1 has to be flushed before L2, not the other way round. Signed-off-by: Sascha Hauer --- arch/arm/cpu/mmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/cpu/mmu.c') diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c index 37bfa058a5..1bd6080f5c 100644 --- a/arch/arm/cpu/mmu.c +++ b/arch/arm/cpu/mmu.c @@ -159,9 +159,9 @@ static u32 *find_pte(unsigned long adr) static void dma_flush_range(unsigned long start, unsigned long end) { + __dma_flush_range(start, end); if (outer_cache.flush_range) outer_cache.flush_range(start, end); - __dma_flush_range(start, end); } static void dma_inv_range(unsigned long start, unsigned long end) -- cgit v1.2.3