From f4d4b659e44e9689685d6e4e07dccbcfee17397e Mon Sep 17 00:00:00 2001 From: Christian Hemp Date: Tue, 13 Dec 2016 15:31:44 +0100 Subject: ARCH: ARM: Add support for phytec-phycore-imx6ul Add support for the phycore i.MX6 UltraLite. - 512MB RAM - 512MB NAND - 10/100 Mbit Ethernet Signed-off-by: Christian Hemp Signed-off-by: Stefan Lengfeld Signed-off-by: Sascha Hauer --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx6ul-phytec-phycore-som.dts | 185 +++++++++++++++++++++++++++++ 2 files changed, 187 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx6ul-phytec-phycore-som.dts (limited to 'arch/arm/dts') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 607c620806..8ba99577e0 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -51,7 +51,8 @@ pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-pbaa03.dtb.o \ imx6q-phytec-phycore-som-nand.dtb.o \ imx6q-phytec-phycore-som-emmc.dtb.o \ imx6dl-phytec-phycore-som-nand.dtb.o \ - imx6dl-phytec-phycore-som-emmc.dtb.o + imx6dl-phytec-phycore-som-emmc.dtb.o \ + imx6ul-phytec-phycore-som.dtb.o pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += kirkwood-openblocks_a6-bb.dtb.o pbl-dtb-$(CONFIG_MACH_RADXA_ROCK) += rk3188-radxarock.dtb.o diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dts b/arch/arm/dts/imx6ul-phytec-phycore-som.dts new file mode 100644 index 0000000000..65a936551e --- /dev/null +++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dts @@ -0,0 +1,185 @@ +/* + * Copyright (C) 2016 PHYTEC Messtechnik GmbH + * Author: Christian Hemp + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include + +/ { + model = "Phytec phyCORE-i.MX6 Ultra Lite SOM"; + compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul"; + + chosen { + linux,stdout-path = &uart1; + + environment-nand { + compatible = "barebox,environment"; + device-path = &gpmi, "partname:barebox-environment"; + status = "disabled"; + }; + + environment-sd1 { + compatible = "barebox,environment"; + device-path = &usdhc1, "partname:barebox-environment"; + status = "disabled"; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + reg = <1>; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + fsl,no-blockmark-swap; + status = "okay"; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x400000>; + }; + + partition@400000 { + label = "barebox-environment"; + reg = <0x400000 0x100000>; + }; + + partition@500000 { + label = "root"; + reg = <0x500000 0x0>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 =<&pinctrl_i2c1>; + clock-frequency = <100000>; + status = "okay"; + + eeprom@52 { + compatible = "cat,24c32"; + reg = <0x52>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx6ul-phytec-phycore-som { + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 + >; + }; + + pinctrl_i2c1: i2cgrp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ + >; + }; + }; +}; -- cgit v1.2.3