From 7e73f9a3b89dcabb5737e2989ede1f7558dff9f1 Mon Sep 17 00:00:00 2001 From: Rouven Czerwinski Date: Tue, 28 Jan 2020 06:38:19 +0100 Subject: ARM: import setjmp implementation from U-Boot Signed-off-by: Rouven Czerwinski Signed-off-by: Sascha Hauer --- arch/arm/lib32/Makefile | 2 ++ arch/arm/lib32/setjmp.S | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+) create mode 100644 arch/arm/lib32/setjmp.S (limited to 'arch/arm/lib32') diff --git a/arch/arm/lib32/Makefile b/arch/arm/lib32/Makefile index cd43147e66..cfcf3bc8f1 100644 --- a/arch/arm/lib32/Makefile +++ b/arch/arm/lib32/Makefile @@ -28,3 +28,5 @@ extra-y += barebox.lds pbl-y += lib1funcs.o pbl-y += ashldi3.o pbl-y += div0.o + +obj-pbl-y += setjmp.o diff --git a/arch/arm/lib32/setjmp.S b/arch/arm/lib32/setjmp.S new file mode 100644 index 0000000000..f0606a7f66 --- /dev/null +++ b/arch/arm/lib32/setjmp.S @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) 2017 Theobroma Systems Design und Consulting GmbH + */ + +#include +#include +#include + +.pushsection .text.setjmp, "ax" +ENTRY(setjmp) + /* + * A subroutine must preserve the contents of the registers + * r4-r8, r10, r11 (v1-v5, v7 and v8) and SP (and r9 in PCS + * variants that designate r9 as v6). + */ + mov ip, sp + stm a1, {v1-v8, ip, lr} + mov a1, #0 + bx lr +ENDPROC(setjmp) +.popsection + +.pushsection .text.longjmp, "ax" +ENTRY(longjmp) + ldm a1, {v1-v8, ip, lr} + mov sp, ip + mov a1, a2 + /* If we were passed a return value of zero, return one instead */ + cmp a1, #0 + bne 1f + mov a1, #1 +1: + bx lr +ENDPROC(longjmp) +.popsection -- cgit v1.2.3