From f6ebdf21946de82b73fb35308e9f9003a14bc100 Mon Sep 17 00:00:00 2001 From: Alexander Kurz Date: Fri, 9 Sep 2016 17:43:43 +0200 Subject: Add i.MX50 support Signed-off-by: Alexander Kurz Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/include/mach/clock-imx51_53.h | 1 + arch/arm/mach-imx/include/mach/debug_ll.h | 11 +++ arch/arm/mach-imx/include/mach/devices-imx50.h | 83 ++++++++++++++++++++++ arch/arm/mach-imx/include/mach/generic.h | 3 + arch/arm/mach-imx/include/mach/imx5.h | 1 + arch/arm/mach-imx/include/mach/imx50-regs.h | 92 +++++++++++++++++++++++++ 6 files changed, 191 insertions(+) create mode 100644 arch/arm/mach-imx/include/mach/devices-imx50.h create mode 100644 arch/arm/mach-imx/include/mach/imx50-regs.h (limited to 'arch/arm/mach-imx/include/mach') diff --git a/arch/arm/mach-imx/include/mach/clock-imx51_53.h b/arch/arm/mach-imx/include/mach/clock-imx51_53.h index 0f25dfbf2f..06ea2e2a3c 100644 --- a/arch/arm/mach-imx/include/mach/clock-imx51_53.h +++ b/arch/arm/mach-imx/include/mach/clock-imx51_53.h @@ -102,6 +102,7 @@ #define MX5_CCM_CCGR4 0x78 #define MX5_CCM_CCGR5 0x7C #define MX5_CCM_CCGR6 0x80 +#define MX50_CCM_CCGR7 0x84 #define MX53_CCM_CCGR7 0x84 #define MX51_CCM_CMEOR 0x84 diff --git a/arch/arm/mach-imx/include/mach/debug_ll.h b/arch/arm/mach-imx/include/mach/debug_ll.h index 4f2d923aa0..5c2db6cd51 100644 --- a/arch/arm/mach-imx/include/mach/debug_ll.h +++ b/arch/arm/mach-imx/include/mach/debug_ll.h @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -33,6 +34,8 @@ #define IMX_DEBUG_SOC MX31 #elif defined CONFIG_DEBUG_IMX35_UART #define IMX_DEBUG_SOC MX35 +#elif defined CONFIG_DEBUG_IMX50_UART +#define IMX_DEBUG_SOC MX50 #elif defined CONFIG_DEBUG_IMX51_UART #define IMX_DEBUG_SOC MX51 #elif defined CONFIG_DEBUG_IMX53_UART @@ -43,6 +46,13 @@ #error "unknown i.MX debug uart soc type" #endif +static inline void imx50_uart_setup_ll(void) +{ + void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC, CONFIG_DEBUG_IMX_UART_PORT)); + + imx50_uart_setup(base); +} + static inline void imx51_uart_setup_ll(void) { void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC, CONFIG_DEBUG_IMX_UART_PORT)); @@ -76,6 +86,7 @@ static inline void PUTC_LL(int c) } #else +static inline void imx50_uart_setup_ll(void) {} static inline void imx51_uart_setup_ll(void) {} static inline void imx53_uart_setup_ll(void) {} static inline void imx6_uart_setup_ll(void) {} diff --git a/arch/arm/mach-imx/include/mach/devices-imx50.h b/arch/arm/mach-imx/include/mach/devices-imx50.h new file mode 100644 index 0000000000..9e0eaa8cbb --- /dev/null +++ b/arch/arm/mach-imx/include/mach/devices-imx50.h @@ -0,0 +1,83 @@ + +#include +#include + +static inline struct device_d *imx50_add_spi0(struct spi_imx_master *pdata) +{ + return imx_add_spi_imx51((void *)MX50_ECSPI1_BASE_ADDR, 0, pdata); +} + +static inline struct device_d *imx50_add_spi1(struct spi_imx_master *pdata) +{ + return imx_add_spi_imx51((void *)MX50_ECSPI2_BASE_ADDR, 1, pdata); +} + +static inline struct device_d *imx50_add_cspi(struct spi_imx_master *pdata) +{ + return imx_add_spi_imx35((void *)MX50_CSPI_BASE_ADDR, 2, pdata); +} + +static inline struct device_d *imx50_add_i2c0(struct i2c_platform_data *pdata) +{ + return imx_add_i2c((void *)MX50_I2C1_BASE_ADDR, 0, pdata); +} + +static inline struct device_d *imx50_add_i2c1(struct i2c_platform_data *pdata) +{ + return imx_add_i2c((void *)MX50_I2C2_BASE_ADDR, 1, pdata); +} + +static inline struct device_d *imx50_add_i2c2(struct i2c_platform_data *pdata) +{ + return imx_add_i2c((void *)MX50_I2C3_BASE_ADDR, 2, pdata); +} + +static inline struct device_d *imx50_add_uart0(void) +{ + return imx_add_uart_imx21((void *)MX50_UART1_BASE_ADDR, 0); +} + +static inline struct device_d *imx50_add_uart1(void) +{ + return imx_add_uart_imx21((void *)MX50_UART2_BASE_ADDR, 1); +} + +static inline struct device_d *imx50_add_uart2(void) +{ + return imx_add_uart_imx21((void *)MX50_UART3_BASE_ADDR, 2); +} + +static inline struct device_d *imx50_add_uart3(void) +{ + return imx_add_uart_imx21((void *)MX50_UART4_BASE_ADDR, 3); +} + +static inline struct device_d *imx50_add_fec(struct fec_platform_data *pdata) +{ + return imx_add_fec_imx27((void *)MX50_FEC_BASE_ADDR, pdata); +} + +static inline struct device_d *imx50_add_mmc0(struct esdhc_platform_data *pdata) +{ + return imx_add_esdhc((void *)MX50_ESDHC1_BASE_ADDR, 0, pdata); +} + +static inline struct device_d *imx50_add_mmc1(struct esdhc_platform_data *pdata) +{ + return imx_add_esdhc((void *)MX50_ESDHC2_BASE_ADDR, 1, pdata); +} + +static inline struct device_d *imx50_add_mmc2(struct esdhc_platform_data *pdata) +{ + return imx_add_esdhc((void *)MX50_ESDHC3_BASE_ADDR, 2, pdata); +} + +static inline struct device_d *imx50_add_mmc3(struct esdhc_platform_data *pdata) +{ + return imx_add_esdhc((void *)MX50_ESDHC4_BASE_ADDR, 3, pdata); +} + +static inline struct device_d *imx50_add_kpp(struct matrix_keymap_data *pdata) +{ + return imx_add_kpp((void *)MX50_KPP_BASE_ADDR, pdata); +} diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h index 243239d0e8..cadc501040 100644 --- a/arch/arm/mach-imx/include/mach/generic.h +++ b/arch/arm/mach-imx/include/mach/generic.h @@ -11,6 +11,7 @@ u64 imx_uid(void); void imx25_boot_save_loc(void __iomem *ccm_base); void imx35_boot_save_loc(void __iomem *ccm_base); void imx27_boot_save_loc(void __iomem *sysctrl_base); +void imx50_boot_save_loc(void __iomem *src_base); void imx51_boot_save_loc(void __iomem *src_base); void imx53_boot_save_loc(void __iomem *src_base); void imx6_boot_save_loc(void __iomem *src_base); @@ -22,6 +23,7 @@ int imx25_init(void); int imx27_init(void); int imx31_init(void); int imx35_init(void); +int imx50_init(void); int imx51_init(void); int imx53_init(void); int imx6_init(void); @@ -32,6 +34,7 @@ int imx25_devices_init(void); int imx27_devices_init(void); int imx31_devices_init(void); int imx35_devices_init(void); +int imx50_devices_init(void); int imx51_devices_init(void); int imx53_devices_init(void); int imx6_devices_init(void); diff --git a/arch/arm/mach-imx/include/mach/imx5.h b/arch/arm/mach-imx/include/mach/imx5.h index 5d1a7d7d40..5957141298 100644 --- a/arch/arm/mach-imx/include/mach/imx5.h +++ b/arch/arm/mach-imx/include/mach/imx5.h @@ -1,6 +1,7 @@ #ifndef __MACH_MX5_H #define __MACH_MX5_H +void imx50_init_lowlevel(unsigned int cpufreq_mhz); void imx51_init_lowlevel(unsigned int cpufreq_mhz); void imx53_init_lowlevel(unsigned int cpufreq_mhz); void imx53_init_lowlevel_early(unsigned int cpufreq_mhz); diff --git a/arch/arm/mach-imx/include/mach/imx50-regs.h b/arch/arm/mach-imx/include/mach/imx50-regs.h new file mode 100644 index 0000000000..97ac8e2dad --- /dev/null +++ b/arch/arm/mach-imx/include/mach/imx50-regs.h @@ -0,0 +1,92 @@ +#ifndef __MACH_IMX50_REGS_H +#define __MACH_IMX50_REGS_H + +#include + +#define MX50_IROM_BASE_ADDR 0x0 + +#define MX50_IRAM_BASE_ADDR 0xF8000000 +#define MX50_IRAM_SIZE SZ_128K + +/* + * SPBA global module enabled #0 + */ +#define MX50_SPBA0_BASE_ADDR 0x50000000 +#define MX50_SPBA0_SIZE SZ_1M + +#define MX50_ESDHC1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00004000) +#define MX50_ESDHC2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00008000) +#define MX50_UART3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x0000C000) +#define MX50_ECSPI1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00010000) +#define MX50_SSI2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00014000) +#define MX50_ESDHC3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00020000) +#define MX50_ESDHC4_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00024000) +#define MX50_SPBA_CTRL_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x0003C000) + +/* + * AIPS 1 + */ +#define MX50_AIPS1_BASE_ADDR 0x53F00000 +#define MX50_AIPS1_SIZE SZ_512K + +#define MX50_OTG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00080000) +#define MX50_GPIO1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00084000) +#define MX50_GPIO2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00088000) +#define MX50_GPIO3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x0008C000) +#define MX50_GPIO4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00090000) +#define MX50_KPP_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00094000) +#define MX50_WDOG1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00098000) +#define MX50_GPT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000A0000) +#define MX50_SRTC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000A4000) +#define MX50_IOMUXC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000A8000) +#define MX50_EPIT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000AC000) +#define MX50_PWM1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000B4000) +#define MX50_PWM2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000B8000) +#define MX50_UART1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000BC000) +#define MX50_UART2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000C0000) + +#define MX50_SRC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000D0000) +#define MX50_CCM_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000D4000) +#define MX50_GPC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000D8000) +#define MX50_GPIO5_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000DC000) +#define MX50_GPIO6_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000E0000) +#define MX50_I2C3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000EC000) +#define MX50_UART4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000F0000) + +/* + * AIPS 2 + */ +#define MX50_AIPS2_BASE_ADDR 0x63F00000 +#define MX50_AIPS2_SIZE SZ_512K + +#define MX50_PLL1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00080000) +#define MX50_PLL2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00084000) +#define MX50_PLL3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00088000) +#define MX50_UART5_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00090000) +#define MX50_AHBMAX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00094000) +#define MX50_ARM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000A0000) +#define MX50_OWIRE_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000A4000) +#define MX50_ECSPI2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000AC000) +#define MX50_SDMA_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000B0000) +#define MX50_ROMCP_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000B8000) +#define MX50_CSPI_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000C0000) +#define MX50_I2C2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000C4000) +#define MX50_I2C1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000C8000) +#define MX50_SSI1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000CC000) +#define MX50_AUDMUX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000D0000) +#define MX50_WEIM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000DA000) +#define MX50_FEC_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000EC000) + +/* + * Memory regions and CS + */ +#define MX50_CSD0_BASE_ADDR 0x70000000 +#define MX50_CSD1_BASE_ADDR 0xB0000000 +#define MX50_CS0_BASE_ADDR 0xF0000000 +#define MX50_CS1_32MB_BASE_ADDR 0xF2000000 +#define MX50_CS1_64MB_BASE_ADDR 0xF4000000 +#define MX50_CS2_64MB_BASE_ADDR 0xF4000000 +#define MX50_CS2_96MB_BASE_ADDR 0xF6000000 +#define MX50_CS3_BASE_ADDR 0xF6000000 + +#endif /* __MACH_IMX50_REGS_H */ -- cgit v1.2.3