From d08d788930ff693e89d3cefb7bdbc9b8e228a1bf Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Wed, 9 Nov 2016 08:13:49 -0800 Subject: i.MX: Add primitive functions for VF610 family Add very basic functions to support VF610 family. Signed-off-by: Andrey Smirnov Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/include/mach/generic.h | 13 +++++++++++++ arch/arm/mach-imx/include/mach/imx_cpu_types.h | 1 + 2 files changed, 14 insertions(+) (limited to 'arch/arm/mach-imx/include') diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h index 7c275dff84..34194509e8 100644 --- a/arch/arm/mach-imx/include/mach/generic.h +++ b/arch/arm/mach-imx/include/mach/generic.h @@ -45,6 +45,7 @@ int imx6_devices_init(void); void imx5_cpu_lowlevel_init(void); void imx6_cpu_lowlevel_init(void); +void vf610_cpu_lowlevel_init(void); /* There's a off-by-one betweem the gpio bank number and the gpiochip */ /* range e.g. GPIO_1_5 is gpio 5 under linux */ @@ -173,6 +174,18 @@ extern unsigned int __imx_cpu_type; # define cpu_is_mx6() (0) #endif +#ifdef CONFIG_ARCH_VF610 +# ifdef imx_cpu_type +# undef imx_cpu_type +# define imx_cpu_type __imx_cpu_type +# else +# define imx_cpu_type IMX_CPU_VF610 +# endif +# define cpu_is_vf610() (imx_cpu_type == IMX_CPU_VF610) +#else +# define cpu_is_vf610() (0) +#endif + #define cpu_is_mx23() (0) #define cpu_is_mx28() (0) diff --git a/arch/arm/mach-imx/include/mach/imx_cpu_types.h b/arch/arm/mach-imx/include/mach/imx_cpu_types.h index 84724883b5..50be0b6b5e 100644 --- a/arch/arm/mach-imx/include/mach/imx_cpu_types.h +++ b/arch/arm/mach-imx/include/mach/imx_cpu_types.h @@ -11,5 +11,6 @@ #define IMX_CPU_IMX51 51 #define IMX_CPU_IMX53 53 #define IMX_CPU_IMX6 6 +#define IMX_CPU_VF610 610 #endif /* __MACH_IMX_CPU_TYPES_H */ -- cgit v1.2.3 From a5ef52e50291541eb6e7d1b1e5c7f25940177527 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Wed, 9 Nov 2016 08:13:50 -0800 Subject: i.MX: Add register definitions for VF610 SoC Signed-off-by: Andrey Smirnov Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/include/mach/clock-vf610.h | 171 ++++++++++++++++++++ arch/arm/mach-imx/include/mach/iomux-vf610.h | 226 +++++++++++++++++++++++++++ arch/arm/mach-imx/include/mach/vf610-regs.h | 110 +++++++++++++ 3 files changed, 507 insertions(+) create mode 100644 arch/arm/mach-imx/include/mach/clock-vf610.h create mode 100644 arch/arm/mach-imx/include/mach/iomux-vf610.h create mode 100644 arch/arm/mach-imx/include/mach/vf610-regs.h (limited to 'arch/arm/mach-imx/include') diff --git a/arch/arm/mach-imx/include/mach/clock-vf610.h b/arch/arm/mach-imx/include/mach/clock-vf610.h new file mode 100644 index 0000000000..0fa70a4385 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/clock-vf610.h @@ -0,0 +1,171 @@ +/* + * Copyright 2013-2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MACH_CLOCK_VF610_H__ +#define __MACH_CLOCK_VF610_H__ + +#define VF610_CCM_CCR (VF610_CCM_BASE_ADDR + 0x00) +#define VF610_CCM_CSR (VF610_CCM_BASE_ADDR + 0x04) +#define VF610_CCM_CCSR (VF610_CCM_BASE_ADDR + 0x08) +#define VF610_CCM_CACRR (VF610_CCM_BASE_ADDR + 0x0c) +#define VF610_CCM_CSCMR1 (VF610_CCM_BASE_ADDR + 0x10) +#define VF610_CCM_CSCDR1 (VF610_CCM_BASE_ADDR + 0x14) +#define VF610_CCM_CSCDR2 (VF610_CCM_BASE_ADDR + 0x18) +#define VF610_CCM_CSCDR3 (VF610_CCM_BASE_ADDR + 0x1c) +#define VF610_CCM_CSCMR2 (VF610_CCM_BASE_ADDR + 0x20) +#define VF610_CCM_CTOR (VF610_CCM_BASE_ADDR + 0x28) +#define VF610_CCM_CLPCR (VF610_CCM_BASE_ADDR + 0x80) +#define VF610_CCM_CMEOR5 (VF610_CCM_BASE_ADDR + 0x84) +#define VF610_CCM_CPPDSR (VF610_CCM_BASE_ADDR + 0x88) +#define VF610_CCM_CCOWR (VF610_CCM_BASE_ADDR + 0x8c) +#define VF610_CCM_CCPGR0 (VF610_CCM_BASE_ADDR + 0x90) +#define VF610_CCM_CCPGR1 (VF610_CCM_BASE_ADDR + 0x94) +#define VF610_CCM_CCPGR2 (VF610_CCM_BASE_ADDR + 0x98) +#define VF610_CCM_CCPGR3 (VF610_CCM_BASE_ADDR + 0x9c) + +#define VF610_CCM_CCGRx_CGn(n) ((n) * 2) + +#define VF610_ANADIG_PLL1_CTRL (VF610_ANADIG_BASE_ADDR + 0x270) +#define VF610_ANADIG_PLL1_NUM (VF610_ANADIG_BASE_ADDR + 0x290) +#define VF610_ANADIG_PLL1_DENOM (VF610_ANADIG_BASE_ADDR + 0x2A0) +#define VF610_ANADIG_PLL2_CTRL (VF610_ANADIG_BASE_ADDR + 0x30) +#define VF610_ANADIG_PLL2_NUM (VF610_ANADIG_BASE_ADDR + 0x50) +#define VF610_ANADIG_PLL3_CTRL (VF610_ANADIG_BASE_ADDR + 0x10) +#define VF610_ANADIG_PLL4_CTRL (VF610_ANADIG_BASE_ADDR + 0x70) +#define VF610_ANADIG_PLL5_CTRL (VF610_ANADIG_BASE_ADDR + 0xe0) +#define VF610_ANADIG_PLL6_CTRL (VF610_ANADIG_BASE_ADDR + 0xa0) +#define VF610_ANADIG_PLL7_CTRL (VF610_ANADIG_BASE_ADDR + 0x20) +#define VF610_ANADIG_ANA_MISC1 (VF610_ANADIG_BASE_ADDR + 0x160) +#define VF610_ANADIG_LOCK (VF610_ANADIG_BASE_ADDR + 0x2C0) + +#define CCM_CCR_FIRC_EN (1 << 16) +#define CCM_CCR_OSCNT_MASK 0xff +#define CCM_CCR_OSCNT(v) ((v) & 0xff) + +#define CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET 19 +#define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK (0x7 << 19) +#define CCM_CCSR_PLL2_PFD_CLK_SEL(v) (((v) & 0x7) << 19) + +#define CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET 16 +#define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 << 16) +#define CCM_CCSR_PLL1_PFD_CLK_SEL(v) (((v) & 0x7) << 16) + +#define CCM_CCSR_PLL2_PFD4_EN (1 << 15) +#define CCM_CCSR_PLL2_PFD3_EN (1 << 14) +#define CCM_CCSR_PLL2_PFD2_EN (1 << 13) +#define CCM_CCSR_PLL2_PFD1_EN (1 << 12) +#define CCM_CCSR_PLL1_PFD4_EN (1 << 11) +#define CCM_CCSR_PLL1_PFD3_EN (1 << 10) +#define CCM_CCSR_PLL1_PFD2_EN (1 << 9) +#define CCM_CCSR_PLL1_PFD1_EN (1 << 8) + +#define CCM_CCSR_DDRC_CLK_SEL(v) ((v) << 6) +#define CCM_CCSR_FAST_CLK_SEL(v) ((v) << 5) + +#define CCM_CCSR_SYS_CLK_SEL_OFFSET 0 +#define CCM_CCSR_SYS_CLK_SEL_MASK 0x7 +#define CCM_CCSR_SYS_CLK_SEL(v) ((v) & 0x7) + +#define CCM_CACRR_IPG_CLK_DIV_OFFSET 11 +#define CCM_CACRR_IPG_CLK_DIV_MASK (0x3 << 11) +#define CCM_CACRR_IPG_CLK_DIV(v) (((v) & 0x3) << 11) +#define CCM_CACRR_BUS_CLK_DIV_OFFSET 3 +#define CCM_CACRR_BUS_CLK_DIV_MASK (0x7 << 3) +#define CCM_CACRR_BUS_CLK_DIV(v) (((v) & 0x7) << 3) +#define CCM_CACRR_ARM_CLK_DIV_OFFSET 0 +#define CCM_CACRR_ARM_CLK_DIV_MASK 0x7 +#define CCM_CACRR_ARM_CLK_DIV(v) ((v) & 0x7) + +#define CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET 22 +#define CCM_CSCMR1_QSPI0_CLK_SEL_MASK (0x3 << 22) +#define CCM_CSCMR1_QSPI0_CLK_SEL(v) (((v) & 0x3) << 22) +#define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET 18 +#define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18) +#define CCM_CSCMR1_ESDHC1_CLK_SEL(v) (((v) & 0x3) << 18) +#define CCM_CSCMR1_NFC_CLK_SEL_OFFSET 12 +#define CCM_CSCMR1_NFC_CLK_SEL_MASK (0x3 << 12) +#define CCM_CSCMR1_NFC_CLK_SEL(v) (((v) & 0x3) << 12) + +#define CCM_CSCDR1_RMII_CLK_EN (1 << 24) + +#define CCM_CSCDR2_NFC_EN (1 << 9) +#define CCM_CSCDR2_NFC_FRAC_DIV_EN (1 << 13) +#define CCM_CSCDR2_NFC_CLK_INV (1 << 14) +#define CCM_CSCDR2_NFC_FRAC_DIV_OFFSET 4 +#define CCM_CSCDR2_NFC_FRAC_DIV_MASK (0xf << 4) +#define CCM_CSCDR2_NFC_FRAC_DIV(v) (((v) & 0xf) << 4) + +#define CCM_CSCDR2_ESDHC1_EN (1 << 29) +#define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET 20 +#define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20) +#define CCM_CSCDR2_ESDHC1_CLK_DIV(v) (((v) & 0xf) << 20) + +#define CCM_CSCDR3_NFC_PRE_DIV_OFFSET 13 +#define CCM_CSCDR3_NFC_PRE_DIV_MASK (0x7 << 13) +#define CCM_CSCDR3_NFC_PRE_DIV(v) (((v) & 0x7) << 13) +#define CCM_CSCDR3_QSPI0_EN (1 << 4) +#define CCM_CSCDR3_QSPI0_DIV(v) ((v) << 3) +#define CCM_CSCDR3_QSPI0_X2_DIV(v) ((v) << 2) +#define CCM_CSCDR3_QSPI0_X4_DIV(v) ((v) & 0x3) + +#define CCM_CSCMR2_RMII_CLK_SEL_OFFSET 4 +#define CCM_CSCMR2_RMII_CLK_SEL_MASK (0x3 << 4) +#define CCM_CSCMR2_RMII_CLK_SEL(v) (((v) & 0x3) << 4) + +#define CCM_REG_CTRL_MASK 0xffffffff +#define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14) +#define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16) +#define CCM_CCGR0_DSPI0_CTRL_MASK (0x3 << 24) +#define CCM_CCGR0_DSPI1_CTRL_MASK (0x3 << 26) +#define CCM_CCGR1_USBC0_CTRL_MASK (0x3 << 8) +#define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14) +#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28) +#define CCM_CCGR2_QSPI0_CTRL_MASK (0x3 << 8) +#define CCM_CCGR2_IOMUXC_CTRL_MASK (0x3 << 16) +#define CCM_CCGR2_PORTA_CTRL_MASK (0x3 << 18) +#define CCM_CCGR2_PORTB_CTRL_MASK (0x3 << 20) +#define CCM_CCGR2_PORTC_CTRL_MASK (0x3 << 22) +#define CCM_CCGR2_PORTD_CTRL_MASK (0x3 << 24) +#define CCM_CCGR2_PORTE_CTRL_MASK (0x3 << 26) +#define CCM_CCGR3_ANADIG_CTRL_MASK 0x3 +#define CCM_CCGR3_SCSC_CTRL_MASK (0x3 << 4) +#define CCM_CCGR4_WKUP_CTRL_MASK (0x3 << 20) +#define CCM_CCGR4_CCM_CTRL_MASK (0x3 << 22) +#define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24) +#define CCM_CCGR4_I2C0_CTRL_MASK (0x3 << 12) +#define CCM_CCGR4_I2C1_CTRL_MASK (0x3 << 14) +#define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10) +#define CCM_CCGR6_DSPI2_CTRL_MASK (0x3 << 24) +#define CCM_CCGR6_DSPI3_CTRL_MASK (0x3 << 26) +#define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28) +#define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4) +#define CCM_CCGR7_USBC1_CTRL_MASK (0x3 << 8) +#define CCM_CCGR9_FEC0_CTRL_MASK 0x3 +#define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2) +#define CCM_CCGR10_NFC_CTRL_MASK 0x3 +#define CCM_CCGR10_I2C2_CTRL_MASK (0x3 << 12) +#define CCM_CCGR10_I2C3_CTRL_MASK (0x3 << 14) + +#define ANADIG_PLL7_CTRL_BYPASS (1 << 16) +#define ANADIG_PLL7_CTRL_ENABLE (1 << 13) +#define ANADIG_PLL7_CTRL_POWERDOWN (1 << 12) +#define ANADIG_PLL7_CTRL_DIV_SELECT (1 << 1) +#define ANADIG_PLL5_CTRL_BYPASS (1 << 16) +#define ANADIG_PLL5_CTRL_ENABLE (1 << 13) +#define ANADIG_PLL5_CTRL_POWERDOWN (1 << 12) +#define ANADIG_PLL5_CTRL_DIV_SELECT 1 +#define ANADIG_PLL3_CTRL_BYPASS (1 << 16) +#define ANADIG_PLL3_CTRL_ENABLE (1 << 13) +#define ANADIG_PLL3_CTRL_POWERDOWN (1 << 12) +#define ANADIG_PLL3_CTRL_DIV_SELECT (1 << 1) +#define ANADIG_PLL2_CTRL_ENABLE (1 << 13) +#define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12) +#define ANADIG_PLL2_CTRL_DIV_SELECT 1 +#define ANADIG_PLL1_CTRL_ENABLE (1 << 13) +#define ANADIG_PLL1_CTRL_POWERDOWN (1 << 12) +#define ANADIG_PLL1_CTRL_DIV_SELECT 1 + +#endif diff --git a/arch/arm/mach-imx/include/mach/iomux-vf610.h b/arch/arm/mach-imx/include/mach/iomux-vf610.h new file mode 100644 index 0000000000..15356282f2 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/iomux-vf610.h @@ -0,0 +1,226 @@ +/* + * Copyright 2013-2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MACH_IOMUX_VF610_H__ +#define __MACH_IOMUX_VF610_H__ + +#include + +#undef PAD_CTL_ODE +#undef PAD_CTL_PKE +#undef PAD_CTL_PUE + +enum { + PAD_MUX_MODE_SHIFT = 20, + PAD_CTL_INPUT_DIFFERENTIAL = 1 << 16, + PAD_CTL_SPEED_MED = 1 << 12, + PAD_CTL_SPEED_HIGH = 3 << 12, + PAD_CTL_SRE = 1 << 11, + PAD_CTL_ODE = 1 << 10, + PAD_CTL_DSE_150ohm = 1 << 6, + PAD_CTL_DSE_50ohm = 3 << 6, + PAD_CTL_DSE_25ohm = 6 << 6, + PAD_CTL_DSE_20ohm = 7 << 6, + PAD_CTL_PKE = 1 << 3, + PAD_CTL_PUE = 1 << 2 | PAD_CTL_PKE, + PAD_CTL_OBE_IBE_ENABLE = 3 << 0, + PAD_CTL_OBE_ENABLE = 1 << 1, + PAD_CTL_IBE_ENABLE = 1 << 0, +}; + +/* These 2 defines are for pins that may not have a mux register, but could + * have a pad setting register, and vice-versa. */ +#define __NA_ 0x00 + +/* Pad control groupings */ +enum { + + VF610_UART_PAD_CTRL = PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE, + VF610_SDHC_PAD_CTRL = PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE, + VF610_ENET_PAD_CTRL = PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE, + VF610_DDR_PAD_CTRL = PAD_CTL_DSE_25ohm, + VF610_DDR_PAD_CTRL_1 = PAD_CTL_DSE_25ohm | PAD_CTL_INPUT_DIFFERENTIAL, + VF610_I2C_PAD_CTRL = PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | PAD_CTL_SPEED_HIGH | PAD_CTL_ODE | PAD_CTL_OBE_IBE_ENABLE, + VF610_NFC_IO_PAD_CTRL = PAD_CTL_SPEED_MED | PAD_CTL_SRE | PAD_CTL_DSE_50ohm | PAD_CTL_PUS_47K_UP | PAD_CTL_OBE_IBE_ENABLE, + VF610_NFC_CN_PAD_CTRL = PAD_CTL_SPEED_MED | PAD_CTL_SRE | PAD_CTL_DSE_25ohm | PAD_CTL_OBE_ENABLE, + VF610_NFC_RB_PAD_CTRL = PAD_CTL_SPEED_MED | PAD_CTL_SRE | PAD_CTL_PUS_22K_UP | PAD_CTL_IBE_ENABLE, + VF610_QSPI_PAD_CTRL = PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_150ohm | PAD_CTL_PUS_22K_UP | PAD_CTL_OBE_IBE_ENABLE, + VF610_GPIO_PAD_CTRL = PAD_CTL_SPEED_MED | PAD_CTL_DSE_50ohm | PAD_CTL_IBE_ENABLE, + VF610_DSPI_PAD_CTRL = PAD_CTL_OBE_ENABLE | PAD_CTL_DSE_20ohm | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH, + VF610_DSPI_SIN_PAD_CTRL = PAD_CTL_IBE_ENABLE | PAD_CTL_DSE_20ohm | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH, +}; + +enum { + VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTA6__RMII0_CLKOUT = IOMUX_PAD(0x0000, 0x0000, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTA7__GPIO_134 = IOMUX_PAD(0x0218, 0x0218, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTA17__GPIO_7 = IOMUX_PAD(0x001c, 0x001c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTA20__GPIO_10 = IOMUX_PAD(0x0028, 0x0028, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTA21__GPIO_11 = IOMUX_PAD(0x002c, 0x002c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTA30__GPIO_20 = IOMUX_PAD(0x0050, 0x0050, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTA31__GPIO_21 = IOMUX_PAD(0x0054, 0x0054, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB0__GPIO_22 = IOMUX_PAD(0x0058, 0x0058, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB1__GPIO_23 = IOMUX_PAD(0x005C, 0x005C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB4__UART1_TX = IOMUX_PAD(0x0068, 0x0068, 2, 0x0380, 0, VF610_UART_PAD_CTRL), + VF610_PAD_PTB5__UART1_RX = IOMUX_PAD(0x006c, 0x006c, 2, 0x037c, 0, VF610_UART_PAD_CTRL), + VF610_PAD_PTB6__GPIO_28 = IOMUX_PAD(0x0070, 0x0070, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB7__GPIO_29 = IOMUX_PAD(0x0074, 0x0074, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB8__GPIO_30 = IOMUX_PAD(0x0078, 0x0078, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB9__GPIO_31 = IOMUX_PAD(0x007C, 0x007C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB10__UART0_TX = IOMUX_PAD(0x0080, 0x0080, 1, __NA_, 0, VF610_UART_PAD_CTRL), + VF610_PAD_PTB11__UART0_RX = IOMUX_PAD(0x0084, 0x0084, 1, __NA_, 0, VF610_UART_PAD_CTRL), + VF610_PAD_PTB12__GPIO_34 = IOMUX_PAD(0x0088, 0x0088, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB13__GPIO_35 = IOMUX_PAD(0x008c, 0x008c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB16__GPIO_38 = IOMUX_PAD(0x0098, 0x0098, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB17__GPIO_39 = IOMUX_PAD(0x009c, 0x009c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB18__GPIO_40 = IOMUX_PAD(0x00a0, 0x00a0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB21__GPIO_43 = IOMUX_PAD(0x00ac, 0x00ac, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB22__GPIO_44 = IOMUX_PAD(0x00b0, 0x00b0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB23__GPIO_93 = IOMUX_PAD(0x0174, 0x0174, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB26__GPIO_96 = IOMUX_PAD(0x0180, 0x0180, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB28__GPIO_98 = IOMUX_PAD(0x0188, 0x0188, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTC1__GPIO_46 = IOMUX_PAD(0x00b8, 0x00b8, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTC1__RMII0_MDIO = IOMUX_PAD(0x00b8, 0x00b8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC0__GPIO_45 = IOMUX_PAD(0x00b4, 0x00b4, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTC0__RMII0_MDC = IOMUX_PAD(0x00b4, 0x00b4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC2__RMII0_CRS_DV = IOMUX_PAD(0x00bc, 0x00bc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC2__GPIO_47 = IOMUX_PAD(0x00bc, 0x00bc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTC3__RMII0_RD1 = IOMUX_PAD(0x00c0, 0x00c0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC3__GPIO_48 = IOMUX_PAD(0x00c0, 0x00c0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTC4__RMII0_RD0 = IOMUX_PAD(0x00c4, 0x00c4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC4__GPIO_49 = IOMUX_PAD(0x00c4, 0x00c4, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTC5__RMII0_RXER = IOMUX_PAD(0x00c8, 0x00c8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC5__GPIO_50 = IOMUX_PAD(0x00c8, 0x00c8, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTC6__RMII0_TD1 = IOMUX_PAD(0x00cc, 0x00cc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC6__GPIO_51 = IOMUX_PAD(0x00cc, 0x00cc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTC7__RMII0_TD0 = IOMUX_PAD(0x00D0, 0x00D0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC7__GPIO_52 = IOMUX_PAD(0x00D0, 0x00D0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTC8__RMII0_TXEN = IOMUX_PAD(0x00D4, 0x00D4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC8__GPIO_53 = IOMUX_PAD(0x00D4, 0x00D4, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTC10__RMII1_MDIO = IOMUX_PAD(0x00dc, 0x00dc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC9__RMII1_MDC = IOMUX_PAD(0x00d8, 0x00d8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC11__RMII1_CRS_DV = IOMUX_PAD(0x00e0, 0x00e0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC12__RMII1_RD1 = IOMUX_PAD(0x00e4, 0x00e4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC13__RMII1_RD0 = IOMUX_PAD(0x00e8, 0x00e8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC14__RMII1_RXER = IOMUX_PAD(0x00ec, 0x00ec, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC15__RMII1_TD1 = IOMUX_PAD(0x00f0, 0x00f0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC16__RMII1_TD0 = IOMUX_PAD(0x00f4, 0x00f4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC17__RMII1_TXEN = IOMUX_PAD(0x00f8, 0x00f8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTD5__DSPI1_CS0 = IOMUX_PAD(0x0150, 0x0150, 3, 0x300, 1, VF610_DSPI_PAD_CTRL), + VF610_PAD_PTD6__DSPI1_SIN = IOMUX_PAD(0x0154, 0x0154, 3, 0x2fc, 1, VF610_DSPI_SIN_PAD_CTRL), + VF610_PAD_PTD7__DSPI1_SOUT = IOMUX_PAD(0x0158, 0x0158, 3, __NA_, 0, VF610_DSPI_PAD_CTRL), + VF610_PAD_PTD8__DSPI1_SCK = IOMUX_PAD(0x015c, 0x015c, 3, 0x2f8, 1, VF610_DSPI_PAD_CTRL), + VF610_PAD_PTC29__GPIO_102 = IOMUX_PAD(0x0198, 0x0198, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTC30__GPIO_103 = IOMUX_PAD(0x019c, 0x019c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTA24__ESDHC1_CLK = IOMUX_PAD(0x0038, 0x0038, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), + VF610_PAD_PTA25__ESDHC1_CMD = IOMUX_PAD(0x003c, 0x003c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), + VF610_PAD_PTA26__ESDHC1_DAT0 = IOMUX_PAD(0x0040, 0x0040, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), + VF610_PAD_PTA27__ESDHC1_DAT1 = IOMUX_PAD(0x0044, 0x0044, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), + VF610_PAD_PTA28__ESDHC1_DAT2 = IOMUX_PAD(0x0048, 0x0048, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), + VF610_PAD_PTA29__ESDHC1_DAT3 = IOMUX_PAD(0x004c, 0x004c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), + VF610_PAD_PTB14__I2C0_SCL = IOMUX_PAD(0x0090, 0x0090, 2, 0x033c, 1, VF610_I2C_PAD_CTRL), + VF610_PAD_PTB15__I2C0_SDA = IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, VF610_I2C_PAD_CTRL), + VF610_PAD_PTA22__I2C2_SCL = IOMUX_PAD(0x0030, 0x0030, 6, 0x034c, 0, VF610_I2C_PAD_CTRL), + VF610_PAD_PTA23__I2C2_SDA = IOMUX_PAD(0x0034, 0x0034, 6, 0x0350, 0, VF610_I2C_PAD_CTRL), + VF610_PAD_PTD31__NF_IO15 = IOMUX_PAD(0x00fc, 0x00fc, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD31__GPIO_63 = IOMUX_PAD(0x00fc, 0x00fc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTD30__NF_IO14 = IOMUX_PAD(0x0100, 0x0100, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD30__GPIO_64 = IOMUX_PAD(0x0100, 0x0100, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTD29__NF_IO13 = IOMUX_PAD(0x0104, 0x0104, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD29__GPIO_65 = IOMUX_PAD(0x0104, 0x0104, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTD28__NF_IO12 = IOMUX_PAD(0x0108, 0x0108, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD28__GPIO_66 = IOMUX_PAD(0x0108, 0x0108, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTD27__NF_IO11 = IOMUX_PAD(0x010c, 0x010c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD27__GPIO_67 = IOMUX_PAD(0x010c, 0x010c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTD26__NF_IO10 = IOMUX_PAD(0x0110, 0x0110, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD26__GPIO_68 = IOMUX_PAD(0x0110, 0x0110, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTD25__NF_IO9 = IOMUX_PAD(0x0114, 0x0114, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD25__GPIO_69 = IOMUX_PAD(0x0114, 0x0114, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTD24__NF_IO8 = IOMUX_PAD(0x0118, 0x0118, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD24__GPIO_70 = IOMUX_PAD(0x0118, 0x0118, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTD23__NF_IO7 = IOMUX_PAD(0x011c, 0x011c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD0__QSPI0_A_QSCK = IOMUX_PAD(0x013c, 0x013c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD1__QSPI0_A_CS0 = IOMUX_PAD(0x0140, 0x0140, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD2__QSPI0_A_DATA3 = IOMUX_PAD(0x0144, 0x0144, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD3__QSPI0_A_DATA2 = IOMUX_PAD(0x0148, 0x0148, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD4__GPIO_83 = IOMUX_PAD(0x014C, 0x014C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTD4__QSPI0_A_DATA1 = IOMUX_PAD(0x014c, 0x014c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD5__QSPI0_A_DATA0 = IOMUX_PAD(0x0150, 0x0150, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD7__QSPI0_B_QSCK = IOMUX_PAD(0x0158, 0x0158, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD8__QSPI0_B_CS0 = IOMUX_PAD(0x015c, 0x015c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD9__QSPI0_B_DATA3 = IOMUX_PAD(0x0160, 0x0160, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD9__GPIO_88 = IOMUX_PAD(0x0160, 0x0160, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTD10__QSPI0_B_DATA2 = IOMUX_PAD(0x0164, 0x0164, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD10__GPIO_89 = IOMUX_PAD(0x0164, 0x0164, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTD11__QSPI0_B_DATA1 = IOMUX_PAD(0x0168, 0x0168, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD11__GPIO_90 = IOMUX_PAD(0x0168, 0x0168, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTD12__QSPI0_B_DATA0 = IOMUX_PAD(0x016c, 0x016c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD12__GPIO_91 = IOMUX_PAD(0x016c, 0x016c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTD13__GPIO_92 = IOMUX_PAD(0x0170, 0x0170, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTD22__NF_IO6 = IOMUX_PAD(0x0120, 0x0120, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD21__NF_IO5 = IOMUX_PAD(0x0124, 0x0124, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD20__NF_IO4 = IOMUX_PAD(0x0128, 0x0128, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD19__NF_IO3 = IOMUX_PAD(0x012c, 0x012c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD18__NF_IO2 = IOMUX_PAD(0x0130, 0x0130, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD17__NF_IO1 = IOMUX_PAD(0x0134, 0x0134, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD16__NF_IO0 = IOMUX_PAD(0x0138, 0x0138, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTB24__NF_WE_B = IOMUX_PAD(0x0178, 0x0178, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL), + VF610_PAD_PTB25__NF_CE0_B = IOMUX_PAD(0x017c, 0x017c, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL), + VF610_PAD_PTB27__NF_RE_B = IOMUX_PAD(0x0184, 0x0184, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), + VF610_PAD_PTC26__NF_RB_B = IOMUX_PAD(0x018C, 0x018C, 5, __NA_, 0, VF610_NFC_RB_PAD_CTRL), + VF610_PAD_PTC27__NF_ALE = IOMUX_PAD(0x0190, 0x0190, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), + VF610_PAD_PTC28__NF_CLE = IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), + VF610_PAD_DDR_RESETB = IOMUX_PAD(0x021c, 0x021c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A12__DDR_A_12 = IOMUX_PAD(0x022c, 0x022c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A11__DDR_A_11 = IOMUX_PAD(0x0230, 0x0230, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A10__DDR_A_10 = IOMUX_PAD(0x0234, 0x0234, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A9__DDR_A_9 = IOMUX_PAD(0x0238, 0x0238, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A8__DDR_A_8 = IOMUX_PAD(0x023c, 0x023c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A7__DDR_A_7 = IOMUX_PAD(0x0240, 0x0240, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A6__DDR_A_6 = IOMUX_PAD(0x0244, 0x0244, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A5__DDR_A_5 = IOMUX_PAD(0x0248, 0x0248, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A4__DDR_A_4 = IOMUX_PAD(0x024c, 0x024c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A3__DDR_A_3 = IOMUX_PAD(0x0250, 0x0250, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A2__DDR_A_2 = IOMUX_PAD(0x0254, 0x0254, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A1__DDR_A_1 = IOMUX_PAD(0x0258, 0x0258, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A0__DDR_A_0 = IOMUX_PAD(0x025c, 0x025c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_BA2__DDR_BA_2 = IOMUX_PAD(0x0260, 0x0260, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_BA1__DDR_BA_1 = IOMUX_PAD(0x0264, 0x0264, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_BA0__DDR_BA_0 = IOMUX_PAD(0x0268, 0x0268, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_CAS__DDR_CAS_B = IOMUX_PAD(0x026c, 0x026c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_CKE__DDR_CKE_0 = IOMUX_PAD(0x0270, 0x0270, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_CLK__DDR_CLK_0 = IOMUX_PAD(0x0274, 0x0274, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_CS__DDR_CS_B_0 = IOMUX_PAD(0x0278, 0x0278, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, 0x027c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, 0x0280, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, 0x0284, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, 0x0288, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, 0x028c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, 0x0290, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, 0x0294, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, 0x0298, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, 0x029c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, 0x02a0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, 0x02a4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, 0x02a8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, 0x02ac, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, 0x02b0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, 0x02b4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, 0x02b8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, 0x02bc, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, 0x02c0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, 0x02c4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, 0x02c8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_RAS__DDR_RAS_B = IOMUX_PAD(0x02cc, 0x02cc, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, 0x02d0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, 0x02d4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_ODT0__DDR_ODT_1 = IOMUX_PAD(0x02d8, 0x02d8, 0, __NA_, 0, VF610_DDR_PAD_CTRL), +}; + +#endif /* __IOMUX_VF610_H__ */ diff --git a/arch/arm/mach-imx/include/mach/vf610-regs.h b/arch/arm/mach-imx/include/mach/vf610-regs.h new file mode 100644 index 0000000000..8be220b68c --- /dev/null +++ b/arch/arm/mach-imx/include/mach/vf610-regs.h @@ -0,0 +1,110 @@ +/* + * Copyright 2013-2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MACH_VF610_REGS_H__ +#define __MACH_VF610_REGS_H__ + +#define VF610_IRAM_BASE_ADDR 0x3F000000 /* internal ram */ +#define VF610_IRAM_SIZE 0x00080000 /* 512 KB */ + +#define VF610_AIPS0_BASE_ADDR 0x40000000 +#define VF610_AIPS1_BASE_ADDR 0x40080000 + +/* AIPS 0 */ +#define VF610_MSCM_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00001000) +#define VF610_MSCM_IR_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00001800) +#define VF610_CA5SCU_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00002000) +#define VF610_CA5_INTD_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00003000) +#define VF610_CA5_L2C_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00006000) +#define VF610_NIC0_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00008000) +#define VF610_NIC1_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00009000) +#define VF610_NIC2_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0000A000) +#define VF610_NIC3_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0000B000) +#define VF610_NIC4_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0000C000) +#define VF610_NIC5_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0000D000) +#define VF610_NIC6_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0000E000) +#define VF610_NIC7_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0000F000) +#define VF610_AHBTZASC_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00010000) +#define VF610_TZASC_SYS0_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00011000) +#define VF610_TZASC_SYS1_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00012000) +#define VF610_TZASC_GFX_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00013000) +#define VF610_TZASC_DDR0_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00014000) +#define VF610_TZASC_DDR1_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00015000) +#define VF610_CSU_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00017000) +#define VF610_DMA0_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00018000) +#define VF610_DMA0_TCD_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00019000) +#define VF610_SEMA4_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0001D000) +#define VF610_FB_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0001E000) +#define VF610_DMA_MUX0_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00024000) +#define VF610_UART1_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00027000) +#define VF610_UART2_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00028000) +#define VF610_UART3_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00029000) +#define VF610_UART4_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0002A000) +#define VF610_SPI0_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0002C000) +#define VF610_SPI1_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0002D000) +#define VF610_SAI0_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0002F000) +#define VF610_SAI1_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00030000) +#define VF610_SAI2_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00031000) +#define VF610_SAI3_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00032000) +#define VF610_CRC_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00033000) +#define VF610_USBC0_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00034000) +#define VF610_PDB_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00036000) +#define VF610_PIT_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00037000) +#define VF610_FTM0_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00038000) +#define VF610_FTM1_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00039000) +#define VF610_ADC_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0003B000) +#define VF610_TCON0_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0003D000) +#define VF610_WDOG1_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0003E000) +#define VF610_LPTMR_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00040000) +#define VF610_RLE_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00042000) +#define VF610_MLB_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00043000) +#define VF610_QSPI0_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00044000) +#define VF610_IOMUXC_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00048000) +#define VF610_ANADIG_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00050000) +#define VF610_USB_PHY0_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00050800) +#define VF610_USB_PHY1_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00050C00) +#define VF610_SCSC_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00052000) +#define VF610_ASRC_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00060000) +#define VF610_SPDIF_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00061000) +#define VF610_ESAI_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00062000) +#define VF610_ESAI_FIFO_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00063000) +#define VF610_WDOG_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00065000) +#define VF610_I2C1_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00066000) +#define VF610_I2C2_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00067000) +#define VF610_I2C3_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x000E6000) +#define VF610_I2C4_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x000E7000) +#define VF610_WKUP_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0006A000) +#define VF610_CCM_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0006B000) +#define VF610_GPC_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0006C000) +#define VF610_VREG_DIG_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0006D000) +#define VF610_SRC_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0006E000) +#define VF610_CMU_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0006F000) +#define VF610_GPIO0_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x000FF000) +#define VF610_GPIO1_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x000FF040) +#define VF610_GPIO2_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x000FF080) +#define VF610_GPIO3_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x000FF0C0) +#define VF610_GPIO4_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x000FF100) + +/* AIPS 1 */ +#define VF610_OCOTP_BASE_ADDR (VF610_AIPS1_BASE_ADDR + 0x00025000) +#define VF610_DDR_BASE_ADDR (VF610_AIPS1_BASE_ADDR + 0x0002E000) +#define VF610_ESDHC0_BASE_ADDR (VF610_AIPS1_BASE_ADDR + 0x00031000) +#define VF610_ESDHC1_BASE_ADDR (VF610_AIPS1_BASE_ADDR + 0x00032000) +#define VF610_USBC1_BASE_ADDR (VF610_AIPS1_BASE_ADDR + 0x00034000) +#define VF610_ENET_BASE_ADDR (VF610_AIPS1_BASE_ADDR + 0x00050000) +#define VF610_ENET1_BASE_ADDR (VF610_AIPS1_BASE_ADDR + 0x00051000) +#define VF610_NFC_BASE_ADDR (VF610_AIPS1_BASE_ADDR + 0x00060000) + +#define VF610_QSPI0_AMBA_BASE 0x20000000 + + +/* MSCM interrupt rounter */ +#define VF610_MSCM_IRSPRC(n) (0x880 + 2 * (n)) +#define VF610_MSCM_CPxTYPE 0 +#define VF610_MSCM_IRSPRC_CP0_EN 1 +#define VF610_MSCM_IRSPRC_NUM 112 + +#endif -- cgit v1.2.3 From 3dc136ef875f7a875c58b2b4684d2404a062326d Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Wed, 9 Nov 2016 08:13:51 -0800 Subject: i.MX: Add DEBUG_LL hooks for VF610 Add code to support DEBUG_LL functionality on VF610/Vybrid platform. Signed-off-by: Andrey Smirnov Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/include/mach/debug_ll.h | 27 ++- common/Kconfig | 10 +- include/serial/lpuart.h | 281 ++++++++++++++++++++++++++++++ 3 files changed, 316 insertions(+), 2 deletions(-) create mode 100644 include/serial/lpuart.h (limited to 'arch/arm/mach-imx/include') diff --git a/arch/arm/mach-imx/include/mach/debug_ll.h b/arch/arm/mach-imx/include/mach/debug_ll.h index 5c2db6cd51..a132f3c163 100644 --- a/arch/arm/mach-imx/include/mach/debug_ll.h +++ b/arch/arm/mach-imx/include/mach/debug_ll.h @@ -14,8 +14,10 @@ #include #include #include +#include #include +#include #ifdef CONFIG_DEBUG_LL @@ -42,6 +44,8 @@ #define IMX_DEBUG_SOC MX53 #elif defined CONFIG_DEBUG_IMX6Q_UART #define IMX_DEBUG_SOC MX6 +#elif defined CONFIG_DEBUG_VF610_UART +#define IMX_DEBUG_SOC VF610 #else #error "unknown i.MX debug uart soc type" #endif @@ -74,6 +78,13 @@ static inline void imx6_uart_setup_ll(void) imx6_uart_setup(base); } +static inline void vf610_uart_setup_ll(void) +{ + void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC, CONFIG_DEBUG_IMX_UART_PORT)); + + lpuart_setup(base, 66000000); +} + static inline void PUTC_LL(int c) { void __iomem *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC, @@ -82,14 +93,19 @@ static inline void PUTC_LL(int c) if (!base) return; - imx_uart_putc(base, c); + if (IS_ENABLED(CONFIG_DEBUG_VF610_UART)) + lpuart_putc(base, c); + else + imx_uart_putc(base, c); } + #else static inline void imx50_uart_setup_ll(void) {} static inline void imx51_uart_setup_ll(void) {} static inline void imx53_uart_setup_ll(void) {} static inline void imx6_uart_setup_ll(void) {} +static inline void vf610_uart_setup_ll(void) {} #endif /* CONFIG_DEBUG_LL */ @@ -115,4 +131,13 @@ static inline void imx53_ungate_all_peripherals(void) imx_ungate_all_peripherals(IOMEM(MX53_CCM_BASE_ADDR)); } +static inline void vf610_ungate_all_peripherals(void) +{ + void __iomem *ccmbase = IOMEM(VF610_CCM_BASE_ADDR); + int i; + + for (i = 0x40; i <= 0x6c; i += 4) + writel(0xffffffff, ccmbase + i); +} + #endif /* __MACH_DEBUG_LL_H__ */ diff --git a/common/Kconfig b/common/Kconfig index efd19494d6..ed472a0b5c 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -1071,6 +1071,13 @@ config DEBUG_IMX6Q_UART Say Y here if you want kernel low-level debugging support on i.MX6Q. +config DEBUG_VF610_UART + bool "VF610 Debug UART" + depends on ARCH_VF610 + help + Say Y here if you want kernel low-level debugging support + on VF610. + config DEBUG_OMAP3_UART bool "OMAP3 Debug UART" depends on ARCH_OMAP3 @@ -1111,7 +1118,8 @@ config DEBUG_IMX_UART_PORT DEBUG_IMX51_UART || \ DEBUG_IMX53_UART || \ DEBUG_IMX6Q_UART || \ - DEBUG_IMX6SL_UART + DEBUG_IMX6SL_UART || \ + DEBUG_VF610_UART default 1 depends on ARCH_IMX help diff --git a/include/serial/lpuart.h b/include/serial/lpuart.h new file mode 100644 index 0000000000..917f644a59 --- /dev/null +++ b/include/serial/lpuart.h @@ -0,0 +1,281 @@ +/* + * Copyright (c) 2016 Zodiac Inflight Innovation + * Author: Andrey Smirnov + * + * Based on code found in Linux kernel and U-Boot. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __LPUART_H__ +#define __LPUART_H__ + + +/* All registers are 8-bit width */ +#define UARTBDH 0x00 +#define UARTBDL 0x01 +#define UARTCR1 0x02 +#define UARTCR2 0x03 +#define UARTSR1 0x04 +#define UARTCR3 0x06 +#define UARTDR 0x07 +#define UARTCR4 0x0a +#define UARTCR5 0x0b +#define UARTMODEM 0x0d +#define UARTPFIFO 0x10 +#define UARTCFIFO 0x11 +#define UARTSFIFO 0x12 +#define UARTTWFIFO 0x13 +#define UARTTCFIFO 0x14 +#define UARTRWFIFO 0x15 +#define UARTRCFIFO 0x16 + +#define UARTBDH_LBKDIE 0x80 +#define UARTBDH_RXEDGIE 0x40 +#define UARTBDH_SBR_MASK 0x1f + +#define UARTCR1_LOOPS 0x80 +#define UARTCR1_RSRC 0x20 +#define UARTCR1_M 0x10 +#define UARTCR1_WAKE 0x08 +#define UARTCR1_ILT 0x04 +#define UARTCR1_PE 0x02 +#define UARTCR1_PT 0x01 + +#define UARTCR2_TIE 0x80 +#define UARTCR2_TCIE 0x40 +#define UARTCR2_RIE 0x20 +#define UARTCR2_ILIE 0x10 +#define UARTCR2_TE 0x08 +#define UARTCR2_RE 0x04 +#define UARTCR2_RWU 0x02 +#define UARTCR2_SBK 0x01 + +#define UARTSR1_TDRE 0x80 +#define UARTSR1_TC 0x40 +#define UARTSR1_RDRF 0x20 +#define UARTSR1_IDLE 0x10 +#define UARTSR1_OR 0x08 +#define UARTSR1_NF 0x04 +#define UARTSR1_FE 0x02 +#define UARTSR1_PE 0x01 + +#define UARTCR3_R8 0x80 +#define UARTCR3_T8 0x40 +#define UARTCR3_TXDIR 0x20 +#define UARTCR3_TXINV 0x10 +#define UARTCR3_ORIE 0x08 +#define UARTCR3_NEIE 0x04 +#define UARTCR3_FEIE 0x02 +#define UARTCR3_PEIE 0x01 + +#define UARTCR4_MAEN1 0x80 +#define UARTCR4_MAEN2 0x40 +#define UARTCR4_M10 0x20 +#define UARTCR4_BRFA_MASK 0x1f +#define UARTCR4_BRFA_OFF 0 + +#define UARTCR5_TDMAS 0x80 +#define UARTCR5_RDMAS 0x20 + +#define UARTMODEM_RXRTSE 0x08 +#define UARTMODEM_TXRTSPOL 0x04 +#define UARTMODEM_TXRTSE 0x02 +#define UARTMODEM_TXCTSE 0x01 + +#define UARTPFIFO_TXFE 0x80 +#define UARTPFIFO_FIFOSIZE_MASK 0x7 +#define UARTPFIFO_TXSIZE_OFF 4 +#define UARTPFIFO_RXFE 0x08 +#define UARTPFIFO_RXSIZE_OFF 0 + +#define UARTCFIFO_TXFLUSH 0x80 +#define UARTCFIFO_RXFLUSH 0x40 +#define UARTCFIFO_RXOFE 0x04 +#define UARTCFIFO_TXOFE 0x02 +#define UARTCFIFO_RXUFE 0x01 + +#define UARTSFIFO_TXEMPT 0x80 +#define UARTSFIFO_RXEMPT 0x40 +#define UARTSFIFO_RXOF 0x04 +#define UARTSFIFO_TXOF 0x02 +#define UARTSFIFO_RXUF 0x01 + +/* 32-bit register defination */ +#define UARTBAUD 0x00 +#define UARTSTAT 0x04 +#define UARTCTRL 0x08 +#define UARTDATA 0x0C +#define UARTMATCH 0x10 +#define UARTMODIR 0x14 +#define UARTFIFO 0x18 +#define UARTWATER 0x1c + +#define UARTBAUD_MAEN1 0x80000000 +#define UARTBAUD_MAEN2 0x40000000 +#define UARTBAUD_M10 0x20000000 +#define UARTBAUD_TDMAE 0x00800000 +#define UARTBAUD_RDMAE 0x00200000 +#define UARTBAUD_MATCFG 0x00400000 +#define UARTBAUD_BOTHEDGE 0x00020000 +#define UARTBAUD_RESYNCDIS 0x00010000 +#define UARTBAUD_LBKDIE 0x00008000 +#define UARTBAUD_RXEDGIE 0x00004000 +#define UARTBAUD_SBNS 0x00002000 +#define UARTBAUD_SBR 0x00000000 +#define UARTBAUD_SBR_MASK 0x1fff + +#define UARTSTAT_LBKDIF 0x80000000 +#define UARTSTAT_RXEDGIF 0x40000000 +#define UARTSTAT_MSBF 0x20000000 +#define UARTSTAT_RXINV 0x10000000 +#define UARTSTAT_RWUID 0x08000000 +#define UARTSTAT_BRK13 0x04000000 +#define UARTSTAT_LBKDE 0x02000000 +#define UARTSTAT_RAF 0x01000000 +#define UARTSTAT_TDRE 0x00800000 +#define UARTSTAT_TC 0x00400000 +#define UARTSTAT_RDRF 0x00200000 +#define UARTSTAT_IDLE 0x00100000 +#define UARTSTAT_OR 0x00080000 +#define UARTSTAT_NF 0x00040000 +#define UARTSTAT_FE 0x00020000 +#define UARTSTAT_PE 0x00010000 +#define UARTSTAT_MA1F 0x00008000 +#define UARTSTAT_M21F 0x00004000 + +#define UARTCTRL_R8T9 0x80000000 +#define UARTCTRL_R9T8 0x40000000 +#define UARTCTRL_TXDIR 0x20000000 +#define UARTCTRL_TXINV 0x10000000 +#define UARTCTRL_ORIE 0x08000000 +#define UARTCTRL_NEIE 0x04000000 +#define UARTCTRL_FEIE 0x02000000 +#define UARTCTRL_PEIE 0x01000000 +#define UARTCTRL_TIE 0x00800000 +#define UARTCTRL_TCIE 0x00400000 +#define UARTCTRL_RIE 0x00200000 +#define UARTCTRL_ILIE 0x00100000 +#define UARTCTRL_TE 0x00080000 +#define UARTCTRL_RE 0x00040000 +#define UARTCTRL_RWU 0x00020000 +#define UARTCTRL_SBK 0x00010000 +#define UARTCTRL_MA1IE 0x00008000 +#define UARTCTRL_MA2IE 0x00004000 +#define UARTCTRL_IDLECFG 0x00000100 +#define UARTCTRL_LOOPS 0x00000080 +#define UARTCTRL_DOZEEN 0x00000040 +#define UARTCTRL_RSRC 0x00000020 +#define UARTCTRL_M 0x00000010 +#define UARTCTRL_WAKE 0x00000008 +#define UARTCTRL_ILT 0x00000004 +#define UARTCTRL_PE 0x00000002 +#define UARTCTRL_PT 0x00000001 + +#define UARTDATA_NOISY 0x00008000 +#define UARTDATA_PARITYE 0x00004000 +#define UARTDATA_FRETSC 0x00002000 +#define UARTDATA_RXEMPT 0x00001000 +#define UARTDATA_IDLINE 0x00000800 +#define UARTDATA_MASK 0x3ff + +#define UARTMODIR_IREN 0x00020000 +#define UARTMODIR_TXCTSSRC 0x00000020 +#define UARTMODIR_TXCTSC 0x00000010 +#define UARTMODIR_RXRTSE 0x00000008 +#define UARTMODIR_TXRTSPOL 0x00000004 +#define UARTMODIR_TXRTSE 0x00000002 +#define UARTMODIR_TXCTSE 0x00000001 + +#define UARTFIFO_TXEMPT 0x00800000 +#define UARTFIFO_RXEMPT 0x00400000 +#define UARTFIFO_TXOF 0x00020000 +#define UARTFIFO_RXUF 0x00010000 +#define UARTFIFO_TXFLUSH 0x00008000 +#define UARTFIFO_RXFLUSH 0x00004000 +#define UARTFIFO_TXOFE 0x00000200 +#define UARTFIFO_RXUFE 0x00000100 +#define UARTFIFO_TXFE 0x00000080 +#define UARTFIFO_FIFOSIZE_MASK 0x7 +#define UARTFIFO_TXSIZE_OFF 4 +#define UARTFIFO_RXFE 0x00000008 +#define UARTFIFO_RXSIZE_OFF 0 + +#define UARTWATER_COUNT_MASK 0xff +#define UARTWATER_TXCNT_OFF 8 +#define UARTWATER_RXCNT_OFF 24 +#define UARTWATER_WATER_MASK 0xff +#define UARTWATER_TXWATER_OFF 0 +#define UARTWATER_RXWATER_OFF 16 + +#define FSL_UART_RX_DMA_BUFFER_SIZE 64 + +static inline void lpuart_setbrg(void __iomem *base, + unsigned int refclock, + unsigned int baudrate) +{ + unsigned int bfra; + u16 sbr; + + sbr = (u16) (refclock / (16 * baudrate)); + + writeb(sbr >> 8, base + UARTBDH); + writeb(sbr & 0xff, base + UARTBDL); + + bfra = DIV_ROUND_UP(2 * refclock, baudrate) - 32 * sbr; + bfra &= UARTCR4_BRFA_MASK; + writeb(bfra, base + UARTCR4); +} + +static inline void lpuart_setup_with_fifo(void __iomem *base, + unsigned int refclock, + unsigned int twfifo) +{ + /* Disable UART */ + writeb(0, base + UARTCR2); + writeb(0, base + UARTMODEM); + writeb(0, base + UARTCR1); + + if (twfifo) { + writeb(UARTPFIFO_TXFE | UARTPFIFO_RXFE, base + UARTPFIFO); + writeb((u8)twfifo, base + UARTTWFIFO); + } else { + writeb(0, base + UARTPFIFO); + writeb(0, base + UARTTWFIFO); + } + writeb(1, base + UARTRWFIFO); + writeb(UARTCFIFO_RXFLUSH | UARTCFIFO_TXFLUSH, base + UARTCFIFO); + + lpuart_setbrg(base, refclock, CONFIG_BAUDRATE); + + writeb(UARTCR2_TE | UARTCR2_RE, base + UARTCR2); +} + +static inline void lpuart_setup(void __iomem *base, + unsigned int refclock) +{ + lpuart_setup_with_fifo(base, refclock, 0x00); +} + +static inline void lpuart_putc(void __iomem *base, int c) +{ + if (!(readb(base + UARTCR2) & UARTCR2_TE)) + return; + + while (!(readb(base + UARTSR1) & UARTSR1_TDRE)); + + writeb(c, base + UARTDR); +} + +#endif -- cgit v1.2.3