From de73734fcc59aa83c84297f1f3719609e6b72aba Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 7 Feb 2020 10:46:56 +0100 Subject: ARM: i.MX8: Move iomux header to make space for i.MX8MM Parts of iomux-mx8.h are for i.MX8M and others for i.MX8MQ only, but never for i.MX8 in general. Split this up into different file and avoid the imx8_ prefix. Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/include/mach/iomux-mx8.h | 645 --------------------------- arch/arm/mach-imx/include/mach/iomux-mx8m.h | 27 ++ arch/arm/mach-imx/include/mach/iomux-mx8mq.h | 625 ++++++++++++++++++++++++++ 3 files changed, 652 insertions(+), 645 deletions(-) delete mode 100644 arch/arm/mach-imx/include/mach/iomux-mx8.h create mode 100644 arch/arm/mach-imx/include/mach/iomux-mx8m.h create mode 100644 arch/arm/mach-imx/include/mach/iomux-mx8mq.h (limited to 'arch/arm/mach-imx/include') diff --git a/arch/arm/mach-imx/include/mach/iomux-mx8.h b/arch/arm/mach-imx/include/mach/iomux-mx8.h deleted file mode 100644 index 9660697d96..0000000000 --- a/arch/arm/mach-imx/include/mach/iomux-mx8.h +++ /dev/null @@ -1,645 +0,0 @@ -/* - * Copyright (C) 2017 NXP - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MACH_IOMUX_IMX8MQ_H__ -#define __MACH_IOMUX_IMX8MQ_H__ - -#include - -#define PAD_CTL_DSE_3P3V_45_OHM 0b110 - -enum { - IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0 = IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT = IOMUX_PAD(0x0290, 0x0028, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO00__XTALOSC_REF_CLK_32K = IOMUX_PAD(0x0290, 0x0028, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO00__CCM_EXT_CLK1 = IOMUX_PAD(0x0290, 0x0028, 6, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO00__JTAG_FAIL = IOMUX_PAD(0x0290, 0x0028, 7, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO01__GPIO1_IO1 = IOMUX_PAD(0x0294, 0x002C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO01__PWM1_OUT = IOMUX_PAD(0x0294, 0x002C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO01__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x0294, 0x002C, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO01__CCM_EXT_CLK2 = IOMUX_PAD(0x0294, 0x002C, 6, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO01__JTAG_ACTIVE = IOMUX_PAD(0x0294, 0x002C, 7, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO02__GPIO1_IO2 = IOMUX_PAD(0x0298, 0x0030, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B = IOMUX_PAD(0x0298, 0x0030, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_ANY = IOMUX_PAD(0x0298, 0x0030, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO02__JTAG_DE_B = IOMUX_PAD(0x0298, 0x0030, 7, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO03__GPIO1_IO3 = IOMUX_PAD(0x029C, 0x0034, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO03__USDHC1_VSELECT = IOMUX_PAD(0x029C, 0x0034, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO03__SDMA1_EXT_EVENT0 = IOMUX_PAD(0x029C, 0x0034, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO03__XTALOSC_XTAL_OK = IOMUX_PAD(0x029C, 0x0034, 6, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO03__JTAG_DONE = IOMUX_PAD(0x029C, 0x0034, 7, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 = IOMUX_PAD(0x02A0, 0x0038, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO04__USDHC2_VSELECT = IOMUX_PAD(0x02A0, 0x0038, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO04__SDMA1_EXT_EVENT1 = IOMUX_PAD(0x02A0, 0x0038, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO04__XTALOSC_XTAL_OK_1V = IOMUX_PAD(0x02A0, 0x0038, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO05__GPIO1_IO5 = IOMUX_PAD(0x02A4, 0x003C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO05__ARM_PLATFORM_CM4_NMI = IOMUX_PAD(0x02A4, 0x003C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO05__CCM_PMIC_READY = IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0), - IMX8MQ_PAD_GPIO1_IO05__SRC_INT_BOOT = IOMUX_PAD(0x02A4, 0x003C, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO06__GPIO1_IO6 = IOMUX_PAD(0x02A8, 0x0040, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO06__ENET_MDC = IOMUX_PAD(0x02A8, 0x0040, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO06__USDHC1_CD_B = IOMUX_PAD(0x02A8, 0x0040, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO06__CCM_EXT_CLK3 = IOMUX_PAD(0x02A8, 0x0040, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO07__GPIO1_IO7 = IOMUX_PAD(0x02AC, 0x0044, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO07__ENET_MDIO = IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0), - IMX8MQ_PAD_GPIO1_IO07__USDHC1_WP = IOMUX_PAD(0x02AC, 0x0044, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO07__CCM_EXT_CLK4 = IOMUX_PAD(0x02AC, 0x0044, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8 = IOMUX_PAD(0x02B0, 0x0048, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO08__ENET_1588_EVENT0_IN = IOMUX_PAD(0x02B0, 0x0048, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO08__USDHC2_RESET_B = IOMUX_PAD(0x02B0, 0x0048, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO08__CCM_WAIT = IOMUX_PAD(0x02B0, 0x0048, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 = IOMUX_PAD(0x02B4, 0x004C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO09__ENET_1588_EVENT0_OUT = IOMUX_PAD(0x02B4, 0x004C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO09__SDMA2_EXT_EVENT0 = IOMUX_PAD(0x02B4, 0x004C, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO09__CCM_STOP = IOMUX_PAD(0x02B4, 0x004C, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO10__GPIO1_IO10 = IOMUX_PAD(0x02B8, 0x0050, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO10__USB1_OTG_ID = IOMUX_PAD(0x02B8, 0x0050, 1, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO11__GPIO1_IO11 = IOMUX_PAD(0x02BC, 0x0054, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO11__USB2_OTG_ID = IOMUX_PAD(0x02BC, 0x0054, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO11__CCM_PMIC_READY = IOMUX_PAD(0x02BC, 0x0054, 5, 0x04BC, 1, 0), - - IMX8MQ_PAD_GPIO1_IO12__GPIO1_IO12 = IOMUX_PAD(0x02C0, 0x0058, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO12__USB1_OTG_PWR = IOMUX_PAD(0x02C0, 0x0058, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO12__SDMA2_EXT_EVENT1 = IOMUX_PAD(0x02C0, 0x0058, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT0 = IOMUX_PAD(0x02C0, 0x0058, 7, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO13__GPIO1_IO13 = IOMUX_PAD(0x02C4, 0x005C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO13__USB1_OTG_OC = IOMUX_PAD(0x02C4, 0x005C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO13__PWM2_OUT = IOMUX_PAD(0x02C4, 0x005C, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT1 = IOMUX_PAD(0x02C4, 0x005C, 7, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14 = IOMUX_PAD(0x02C8, 0x0060, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO14__USB2_OTG_PWR = IOMUX_PAD(0x02C8, 0x0060, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO14__PWM3_OUT = IOMUX_PAD(0x02C8, 0x0060, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO14__CCM_CLKO1 = IOMUX_PAD(0x02C8, 0x0060, 6, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO14__CSU_CSU_ALARM_AUT2 = IOMUX_PAD(0x02C8, 0x0060, 7, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO15__GPIO1_IO15 = IOMUX_PAD(0x02CC, 0x0064, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO15__USB2_OTG_OC = IOMUX_PAD(0x02CC, 0x0064, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO15__PWM4_OUT = IOMUX_PAD(0x02CC, 0x0064, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO15__CCM_CLKO2 = IOMUX_PAD(0x02CC, 0x0064, 6, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO15__CSU_CSU_INT_DEB = IOMUX_PAD(0x02CC, 0x0064, 7, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x02D0, 0x0068, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_MDC__GPIO1_IO16 = IOMUX_PAD(0x02D0, 0x0068, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x02D4, 0x006C, 0, 0x04C0, 1, 0), - IMX8MQ_PAD_ENET_MDIO__GPIO1_IO17 = IOMUX_PAD(0x02D4, 0x006C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x02D8, 0x0070, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_TD3__GPIO1_IO18 = IOMUX_PAD(0x02D8, 0x0070, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x02DC, 0x0074, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_TD2__ENET_TX_CLK = IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_TD2__GPIO1_IO19 = IOMUX_PAD(0x02DC, 0x0074, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x02E0, 0x0078, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_TD1__GPIO1_IO20 = IOMUX_PAD(0x02E0, 0x0078, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x02E4, 0x007C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_TD0__GPIO1_IO21 = IOMUX_PAD(0x02E4, 0x007C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_TX_CTL__ENET_RGMII_TX_CTL = IOMUX_PAD(0x02E8, 0x0080, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_TX_CTL__GPIO1_IO22 = IOMUX_PAD(0x02E8, 0x0080, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x02EC, 0x0084, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_TXC__ENET_TX_ER = IOMUX_PAD(0x02EC, 0x0084, 1, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_TXC__GPIO1_IO23 = IOMUX_PAD(0x02EC, 0x0084, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_RX_CTL__ENET_RGMII_RX_CTL = IOMUX_PAD(0x02F0, 0x0088, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_RX_CTL__GPIO1_IO24 = IOMUX_PAD(0x02F0, 0x0088, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x02F4, 0x008C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_RXC__ENET_RX_ER = IOMUX_PAD(0x02F4, 0x008C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_RXC__GPIO1_IO25 = IOMUX_PAD(0x02F4, 0x008C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x02F8, 0x0090, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_RD0__GPIO1_IO26 = IOMUX_PAD(0x02F8, 0x0090, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x02FC, 0x0094, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_RD1__GPIO1_IO27 = IOMUX_PAD(0x02FC, 0x0094, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x0300, 0x0098, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_RD2__GPIO1_IO28 = IOMUX_PAD(0x0300, 0x0098, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x0304, 0x009C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_RD3__GPIO1_IO29 = IOMUX_PAD(0x0304, 0x009C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0308, 0x00A0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_CLK__GPIO2_IO0 = IOMUX_PAD(0x0308, 0x00A0, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x030C, 0x00A4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_CMD__GPIO2_IO1 = IOMUX_PAD(0x030C, 0x00A4, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x0310, 0x00A8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_DATA0__GPIO2_IO2 = IOMUX_PAD(0x0310, 0x00A8, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x0314, 0x00AC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_DATA1__GPIO2_IO3 = IOMUX_PAD(0x0314, 0x00AC, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x0318, 0x00B0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_DATA2__GPIO2_IO4 = IOMUX_PAD(0x0318, 0x00B0, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x031C, 0x00B4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_DATA3__GPIO2_IO5 = IOMUX_PAD(0x031C, 0x00B4, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 = IOMUX_PAD(0x0320, 0x00B8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_DATA4__GPIO2_IO6 = IOMUX_PAD(0x0320, 0x00B8, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 = IOMUX_PAD(0x0324, 0x00BC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_DATA5__GPIO2_IO7 = IOMUX_PAD(0x0324, 0x00BC, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 = IOMUX_PAD(0x0328, 0x00C0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_DATA6__GPIO2_IO8 = IOMUX_PAD(0x0328, 0x00C0, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 = IOMUX_PAD(0x032C, 0x00C4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_DATA7__GPIO2_IO9 = IOMUX_PAD(0x032C, 0x00C4, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_RESET_B__USDHC1_RESET_B = IOMUX_PAD(0x0330, 0x00C8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 = IOMUX_PAD(0x0330, 0x00C8, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_STROBE__USDHC1_STROBE = IOMUX_PAD(0x0334, 0x00CC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_STROBE__GPIO2_IO11 = IOMUX_PAD(0x0334, 0x00CC, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD2_CD_B__USDHC2_CD_B = IOMUX_PAD(0x0338, 0x00D0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 = IOMUX_PAD(0x0338, 0x00D0, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x033C, 0x00D4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_CLK__GPIO2_IO13 = IOMUX_PAD(0x033C, 0x00D4, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0340, 0x00D8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_CMD__GPIO2_IO14 = IOMUX_PAD(0x0340, 0x00D8, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 = IOMUX_PAD(0x0344, 0x00DC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_DATA0__GPIO2_IO15 = IOMUX_PAD(0x0344, 0x00DC, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 = IOMUX_PAD(0x0348, 0x00E0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_DATA1__GPIO2_IO16 = IOMUX_PAD(0x0348, 0x00E0, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_DATA1__CCM_WAIT = IOMUX_PAD(0x0348, 0x00E0, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 = IOMUX_PAD(0x034C, 0x00E4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_DATA2__GPIO2_IO17 = IOMUX_PAD(0x034C, 0x00E4, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_DATA2__CCM_STOP = IOMUX_PAD(0x034C, 0x00E4, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 = IOMUX_PAD(0x0350, 0x00E8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_DATA3__GPIO2_IO18 = IOMUX_PAD(0x0350, 0x00E8, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_DATA3__SRC_EARLY_RESET = IOMUX_PAD(0x0350, 0x00E8, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SD2_RESET_B__USDHC2_RESET_B = IOMUX_PAD(0x0354, 0x00EC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 = IOMUX_PAD(0x0354, 0x00EC, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_RESET_B__SRC_SYSTEM_RESET = IOMUX_PAD(0x0354, 0x00EC, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SD2_WP__USDHC2_WP = IOMUX_PAD(0x0358, 0x00F0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_WP__GPIO2_IO20 = IOMUX_PAD(0x0358, 0x00F0, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_ALE__RAWNAND_ALE = IOMUX_PAD(0x035C, 0x00F4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK = IOMUX_PAD(0x035C, 0x00F4, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_ALE__GPIO3_IO0 = IOMUX_PAD(0x035C, 0x00F4, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_CE0_B__RAWNAND_CE0_B = IOMUX_PAD(0x0360, 0x00F8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B = IOMUX_PAD(0x0360, 0x00F8, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_CE0_B__GPIO3_IO1 = IOMUX_PAD(0x0360, 0x00F8, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_CE1_B__RAWNAND_CE1_B = IOMUX_PAD(0x0364, 0x00FC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_CE1_B__QSPI_A_SS1_B = IOMUX_PAD(0x0364, 0x00FC, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_CE1_B__GPIO3_IO2 = IOMUX_PAD(0x0364, 0x00FC, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_CE2_B__RAWNAND_CE2_B = IOMUX_PAD(0x0368, 0x0100, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_CE2_B__QSPI_B_SS0_B = IOMUX_PAD(0x0368, 0x0100, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_CE2_B__GPIO3_IO3 = IOMUX_PAD(0x0368, 0x0100, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_CE3_B__RAWNAND_CE3_B = IOMUX_PAD(0x036C, 0x0104, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_CE3_B__QSPI_B_SS1_B = IOMUX_PAD(0x036C, 0x0104, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_CE3_B__GPIO3_IO4 = IOMUX_PAD(0x036C, 0x0104, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_CLE__RAWNAND_CLE = IOMUX_PAD(0x0370, 0x0108, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_CLE__QSPI_B_SCLK = IOMUX_PAD(0x0370, 0x0108, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_CLE__GPIO3_IO5 = IOMUX_PAD(0x0370, 0x0108, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_DATA00__RAWNAND_DATA00 = IOMUX_PAD(0x0374, 0x010C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0 = IOMUX_PAD(0x0374, 0x010C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA00__GPIO3_IO6 = IOMUX_PAD(0x0374, 0x010C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_DATA01__RAWNAND_DATA01 = IOMUX_PAD(0x0378, 0x0110, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1 = IOMUX_PAD(0x0378, 0x0110, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA01__GPIO3_IO7 = IOMUX_PAD(0x0378, 0x0110, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_DATA02__RAWNAND_DATA02 = IOMUX_PAD(0x037C, 0x0114, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2 = IOMUX_PAD(0x037C, 0x0114, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA02__GPIO3_IO8 = IOMUX_PAD(0x037C, 0x0114, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_DATA03__RAWNAND_DATA03 = IOMUX_PAD(0x0380, 0x0118, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3 = IOMUX_PAD(0x0380, 0x0118, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA03__GPIO3_IO9 = IOMUX_PAD(0x0380, 0x0118, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_DATA04__RAWNAND_DATA04 = IOMUX_PAD(0x0384, 0x011C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA04__QSPI_B_DATA0 = IOMUX_PAD(0x0384, 0x011C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA04__GPIO3_IO10 = IOMUX_PAD(0x0384, 0x011C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_DATA05__RAWNAND_DATA05 = IOMUX_PAD(0x0388, 0x0120, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA05__QSPI_B_DATA1 = IOMUX_PAD(0x0388, 0x0120, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA05__GPIO3_IO11 = IOMUX_PAD(0x0388, 0x0120, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_DATA06__RAWNAND_DATA06 = IOMUX_PAD(0x038C, 0x0124, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA06__QSPI_B_DATA2 = IOMUX_PAD(0x038C, 0x0124, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12 = IOMUX_PAD(0x038C, 0x0124, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_DATA07__RAWNAND_DATA07 = IOMUX_PAD(0x0390, 0x0128, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA07__QSPI_B_DATA3 = IOMUX_PAD(0x0390, 0x0128, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA07__GPIO3_IO13 = IOMUX_PAD(0x0390, 0x0128, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_DQS__RAWNAND_DQS = IOMUX_PAD(0x0394, 0x012C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DQS__QSPI_A_DQS = IOMUX_PAD(0x0394, 0x012C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DQS__GPIO3_IO14 = IOMUX_PAD(0x0394, 0x012C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_RE_B__RAWNAND_RE_B = IOMUX_PAD(0x0398, 0x0130, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_RE_B__QSPI_B_DQS = IOMUX_PAD(0x0398, 0x0130, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 = IOMUX_PAD(0x0398, 0x0130, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_READY_B__RAWNAND_READY_B = IOMUX_PAD(0x039C, 0x0134, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_READY_B__GPIO3_IO16 = IOMUX_PAD(0x039C, 0x0134, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_WE_B__RAWNAND_WE_B = IOMUX_PAD(0x03A0, 0x0138, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_WE_B__GPIO3_IO17 = IOMUX_PAD(0x03A0, 0x0138, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_WP_B__RAWNAND_WP_B = IOMUX_PAD(0x03A4, 0x013C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_WP_B__GPIO3_IO18 = IOMUX_PAD(0x03A4, 0x013C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI5_RXFS__SAI5_RX_SYNC = IOMUX_PAD(0x03A8, 0x0140, 0, 0x04E4, 0, 0), - IMX8MQ_PAD_SAI5_RXFS__SAI1_TX_DATA0 = IOMUX_PAD(0x03A8, 0x0140, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI5_RXFS__GPIO3_IO19 = IOMUX_PAD(0x03A8, 0x0140, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI5_RXC__SAI5_RX_BCLK = IOMUX_PAD(0x03AC, 0x0144, 0, 0x04D0, 0, 0), - IMX8MQ_PAD_SAI5_RXC__SAI1_TX_DATA1 = IOMUX_PAD(0x03AC, 0x0144, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI5_RXC__GPIO3_IO20 = IOMUX_PAD(0x03AC, 0x0144, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI5_RXD0__SAI5_RX_DATA0 = IOMUX_PAD(0x03B0, 0x0148, 0, 0x04D4, 0, 0), - IMX8MQ_PAD_SAI5_RXD0__SAI1_TX_DATA2 = IOMUX_PAD(0x03B0, 0x0148, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI5_RXD0__GPIO3_IO21 = IOMUX_PAD(0x03B0, 0x0148, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI5_RXD1__SAI5_RX_DATA1 = IOMUX_PAD(0x03B4, 0x014C, 0, 0x04D8, 0, 0), - IMX8MQ_PAD_SAI5_RXD1__SAI1_TX_DATA3 = IOMUX_PAD(0x03B4, 0x014C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI5_RXD1__SAI1_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 2, 0x04CC, 0, 0), - IMX8MQ_PAD_SAI5_RXD1__SAI5_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 3, 0x04EC, 0, 0), - IMX8MQ_PAD_SAI5_RXD1__GPIO3_IO22 = IOMUX_PAD(0x03B4, 0x014C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI5_RXD2__SAI5_RX_DATA2 = IOMUX_PAD(0x03B8, 0x0150, 0, 0x04DC, 0, 0), - IMX8MQ_PAD_SAI5_RXD2__SAI1_TX_DATA4 = IOMUX_PAD(0x03B8, 0x0150, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI5_RXD2__SAI1_TX_SYNC = IOMUX_PAD(0x03B8, 0x0150, 2, 0x04CC, 1, 0), - IMX8MQ_PAD_SAI5_RXD2__SAI5_TX_BCLK = IOMUX_PAD(0x03B8, 0x0150, 3, 0x04E8, 0, 0), - IMX8MQ_PAD_SAI5_RXD2__GPIO3_IO23 = IOMUX_PAD(0x03B8, 0x0150, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI5_RXD3__SAI5_RX_DATA3 = IOMUX_PAD(0x03BC, 0x0154, 0, 0x04E0, 0, 0), - IMX8MQ_PAD_SAI5_RXD3__SAI1_TX_DATA5 = IOMUX_PAD(0x03BC, 0x0154, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI5_RXD3__SAI1_TX_SYNC = IOMUX_PAD(0x03BC, 0x0154, 2, 0x04CC, 2, 0), - IMX8MQ_PAD_SAI5_RXD3__SAI5_TX_DATA0 = IOMUX_PAD(0x03BC, 0x0154, 3, 0x0000, 0, 0), - IMX8MQ_PAD_SAI5_RXD3__GPIO3_IO24 = IOMUX_PAD(0x03BC, 0x0154, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI5_MCLK__SAI5_MCLK = IOMUX_PAD(0x03C0, 0x0158, 0, 0x052C, 0, 0), - IMX8MQ_PAD_SAI5_MCLK__SAI1_TX_BCLK = IOMUX_PAD(0x03C0, 0x0158, 1, 0x04C8, 0, 0), - IMX8MQ_PAD_SAI5_MCLK__SAI4_MCLK = IOMUX_PAD(0x03C0, 0x0158, 2, 0x0000, 0, 0), - IMX8MQ_PAD_SAI5_MCLK__GPIO3_IO25 = IOMUX_PAD(0x03C0, 0x0158, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI5_MCLK__SRC_TESTER_ACK = IOMUX_PAD(0x03C0, 0x0158, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_RXFS__SAI1_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 0, 0x04C4, 0, 0), - IMX8MQ_PAD_SAI1_RXFS__SAI5_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 1, 0x04E4, 1, 0), - IMX8MQ_PAD_SAI1_RXFS__ARM_PLATFORM_TRACE_CLK = IOMUX_PAD(0x03C4, 0x015C, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXFS__GPIO4_IO0 = IOMUX_PAD(0x03C4, 0x015C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_RXC__SAI1_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXC__SAI5_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 1, 0x04D0, 1, 0), - IMX8MQ_PAD_SAI1_RXC__ARM_PLATFORM_TRACE_CTL = IOMUX_PAD(0x03C8, 0x0160, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXC__GPIO4_IO1 = IOMUX_PAD(0x03C8, 0x0160, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_RXD0__SAI1_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD0__SAI5_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 1, 0x04D4, 1, 0), - IMX8MQ_PAD_SAI1_RXD0__ARM_PLATFORM_TRACE0 = IOMUX_PAD(0x03CC, 0x0164, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD0__GPIO4_IO2 = IOMUX_PAD(0x03CC, 0x0164, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD0__SRC_BOOT_CFG0 = IOMUX_PAD(0x03CC, 0x0164, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_RXD1__SAI1_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD1__SAI5_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 1, 0x04D8, 1, 0), - IMX8MQ_PAD_SAI1_RXD1__ARM_PLATFORM_TRACE1 = IOMUX_PAD(0x03D0, 0x0168, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD1__GPIO4_IO3 = IOMUX_PAD(0x03D0, 0x0168, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD1__SRC_BOOT_CFG1 = IOMUX_PAD(0x03D0, 0x0168, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_RXD2__SAI1_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD2__SAI5_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 1, 0x04DC, 1, 0), - IMX8MQ_PAD_SAI1_RXD2__ARM_PLATFORM_TRACE2 = IOMUX_PAD(0x03D4, 0x016C, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD2__GPIO4_IO4 = IOMUX_PAD(0x03D4, 0x016C, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD2__SRC_BOOT_CFG2 = IOMUX_PAD(0x03D4, 0x016C, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_RXD3__SAI1_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 0, 0x04E0, 1, 0), - IMX8MQ_PAD_SAI1_RXD3__SAI5_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD3__ARM_PLATFORM_TRACE3 = IOMUX_PAD(0x03D8, 0x0170, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD3__GPIO4_IO5 = IOMUX_PAD(0x03D8, 0x0170, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD3__SRC_BOOT_CFG3 = IOMUX_PAD(0x03D8, 0x0170, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_RXD4__SAI1_RX_DATA4 = IOMUX_PAD(0x03DC, 0x0174, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD4__SAI6_TX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 1, 0x051C, 0, 0), - IMX8MQ_PAD_SAI1_RXD4__SAI6_RX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 2, 0x0510, 0, 0), - IMX8MQ_PAD_SAI1_RXD4__ARM_PLATFORM_TRACE4 = IOMUX_PAD(0x03DC, 0x0174, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD4__GPIO4_IO6 = IOMUX_PAD(0x03DC, 0x0174, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD4__SRC_BOOT_CFG4 = IOMUX_PAD(0x03DC, 0x0174, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_RXD5__SAI1_RX_DATA5 = IOMUX_PAD(0x03E0, 0x0178, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD5__SAI6_TX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD5__SAI6_RX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 2, 0x0514, 0, 0), - IMX8MQ_PAD_SAI1_RXD5__SAI1_RX_SYNC = IOMUX_PAD(0x03E0, 0x0178, 3, 0x04C4, 1, 0), - IMX8MQ_PAD_SAI1_RXD5__ARM_PLATFORM_TRACE5 = IOMUX_PAD(0x03E0, 0x0178, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD5__GPIO4_IO7 = IOMUX_PAD(0x03E0, 0x0178, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD5__SRC_BOOT_CFG5 = IOMUX_PAD(0x03E0, 0x0178, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_RXD6__SAI1_RX_DATA6 = IOMUX_PAD(0x03E4, 0x017C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD6__SAI6_TX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 1, 0x0520, 0, 0), - IMX8MQ_PAD_SAI1_RXD6__SAI6_RX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 2, 0x0518, 0, 0), - IMX8MQ_PAD_SAI1_RXD6__ARM_PLATFORM_TRACE6 = IOMUX_PAD(0x03E4, 0x017C, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD6__GPIO4_IO8 = IOMUX_PAD(0x03E4, 0x017C, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD6__SRC_BOOT_CFG6 = IOMUX_PAD(0x03E4, 0x017C, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_RXD7__SAI1_RX_DATA7 = IOMUX_PAD(0x03E8, 0x0180, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD7__SAI6_MCLK = IOMUX_PAD(0x03E8, 0x0180, 1, 0x0530, 0, 0), - IMX8MQ_PAD_SAI1_RXD7__SAI1_TX_SYNC = IOMUX_PAD(0x03E8, 0x0180, 2, 0x04CC, 4, 0), - IMX8MQ_PAD_SAI1_RXD7__SAI1_TX_DATA4 = IOMUX_PAD(0x03E8, 0x0180, 3, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD7__ARM_PLATFORM_TRACE7 = IOMUX_PAD(0x03E8, 0x0180, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD7__GPIO4_IO9 = IOMUX_PAD(0x03E8, 0x0180, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD7__SRC_BOOT_CFG7 = IOMUX_PAD(0x03E8, 0x0180, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_TXFS__SAI1_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 0, 0x04CC, 3, 0), - IMX8MQ_PAD_SAI1_TXFS__SAI5_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 1, 0x04EC, 1, 0), - IMX8MQ_PAD_SAI1_TXFS__ARM_PLATFORM_EVENTO = IOMUX_PAD(0x03EC, 0x0184, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXFS__GPIO4_IO10 = IOMUX_PAD(0x03EC, 0x0184, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_TXC__SAI1_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 0, 0x04C8, 1, 0), - IMX8MQ_PAD_SAI1_TXC__SAI5_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 1, 0x04E8, 1, 0), - IMX8MQ_PAD_SAI1_TXC__ARM_PLATFORM_EVENTI = IOMUX_PAD(0x03F0, 0x0188, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXC__GPIO4_IO11 = IOMUX_PAD(0x03F0, 0x0188, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_TXD0__SAI1_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD0__SAI5_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD0__ARM_PLATFORM_TRACE8 = IOMUX_PAD(0x03F4, 0x018C, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD0__GPIO4_IO12 = IOMUX_PAD(0x03F4, 0x018C, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD0__SRC_BOOT_CFG8 = IOMUX_PAD(0x03F4, 0x018C, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_TXD1__SAI1_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD1__SAI5_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD1__ARM_PLATFORM_TRACE9 = IOMUX_PAD(0x03F8, 0x0190, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD1__GPIO4_IO13 = IOMUX_PAD(0x03F8, 0x0190, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD1__SRC_BOOT_CFG9 = IOMUX_PAD(0x03F8, 0x0190, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_TXD2__SAI1_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD2__SAI5_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD2__ARM_PLATFORM_TRACE10 = IOMUX_PAD(0x03FC, 0x0194, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD2__GPIO4_IO14 = IOMUX_PAD(0x03FC, 0x0194, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD2__SRC_BOOT_CFG10 = IOMUX_PAD(0x03FC, 0x0194, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_TXD3__SAI1_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD3__SAI5_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD3__ARM_PLATFORM_TRACE11 = IOMUX_PAD(0x0400, 0x0198, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD3__GPIO4_IO15 = IOMUX_PAD(0x0400, 0x0198, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD3__SRC_BOOT_CFG11 = IOMUX_PAD(0x0400, 0x0198, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_TXD4__SAI1_TX_DATA4 = IOMUX_PAD(0x0404, 0x019C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD4__SAI6_RX_BCLK = IOMUX_PAD(0x0404, 0x019C, 1, 0x0510, 1, 0), - IMX8MQ_PAD_SAI1_TXD4__SAI6_TX_BCLK = IOMUX_PAD(0x0404, 0x019C, 2, 0x051C, 1, 0), - IMX8MQ_PAD_SAI1_TXD4__ARM_PLATFORM_TRACE12 = IOMUX_PAD(0x0404, 0x019C, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD4__GPIO4_IO16 = IOMUX_PAD(0x0404, 0x019C, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD4__SRC_BOOT_CFG12 = IOMUX_PAD(0x0404, 0x019C, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_TXD5__SAI1_TX_DATA5 = IOMUX_PAD(0x0408, 0x01A0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD5__SAI6_RX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 1, 0x0514, 1, 0), - IMX8MQ_PAD_SAI1_TXD5__SAI6_TX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 2, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD5__ARM_PLATFORM_TRACE13 = IOMUX_PAD(0x0408, 0x01A0, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD5__GPIO4_IO17 = IOMUX_PAD(0x0408, 0x01A0, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD5__SRC_BOOT_CFG13 = IOMUX_PAD(0x0408, 0x01A0, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_TXD6__SAI1_TX_DATA6 = IOMUX_PAD(0x040C, 0x01A4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD6__SAI6_RX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 1, 0x0518, 1, 0), - IMX8MQ_PAD_SAI1_TXD6__SAI6_TX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 2, 0x0520, 1, 0), - IMX8MQ_PAD_SAI1_TXD6__ARM_PLATFORM_TRACE14 = IOMUX_PAD(0x040C, 0x01A4, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD6__GPIO4_IO18 = IOMUX_PAD(0x040C, 0x01A4, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD6__SRC_BOOT_CFG14 = IOMUX_PAD(0x040C, 0x01A4, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_TXD7__SAI1_TX_DATA7 = IOMUX_PAD(0x0410, 0x01A8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD7__SAI6_MCLK = IOMUX_PAD(0x0410, 0x01A8, 1, 0x0530, 1, 0), - IMX8MQ_PAD_SAI1_TXD7__ARM_PLATFORM_TRACE15 = IOMUX_PAD(0x0410, 0x01A8, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD7__GPIO4_IO19 = IOMUX_PAD(0x0410, 0x01A8, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD7__SRC_BOOT_CFG15 = IOMUX_PAD(0x0410, 0x01A8, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_MCLK__SAI1_MCLK = IOMUX_PAD(0x0414, 0x01AC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_MCLK__SAI5_MCLK = IOMUX_PAD(0x0414, 0x01AC, 1, 0x052C, 1, 0), - IMX8MQ_PAD_SAI1_MCLK__SAI1_TX_BCLK = IOMUX_PAD(0x0414, 0x01AC, 2, 0x04C8, 2, 0), - IMX8MQ_PAD_SAI1_MCLK__GPIO4_IO20 = IOMUX_PAD(0x0414, 0x01AC, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI2_RXFS__SAI2_RX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI2_RXFS__SAI5_TX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 1, 0x04EC, 2, 0), - IMX8MQ_PAD_SAI2_RXFS__GPIO4_IO21 = IOMUX_PAD(0x0418, 0x01B0, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI2_RXC__SAI2_RX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI2_RXC__SAI5_TX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 1, 0x04E8, 2, 0), - IMX8MQ_PAD_SAI2_RXC__GPIO4_IO22 = IOMUX_PAD(0x041C, 0x01B4, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI2_RXD0__SAI2_RX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI2_RXD0__SAI5_TX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI2_RXD0__GPIO4_IO23 = IOMUX_PAD(0x0420, 0x01B8, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI2_TXFS__SAI2_TX_SYNC = IOMUX_PAD(0x0424, 0x01BC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI2_TXFS__SAI5_TX_DATA1 = IOMUX_PAD(0x0424, 0x01BC, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI2_TXFS__GPIO4_IO24 = IOMUX_PAD(0x0424, 0x01BC, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI2_TXC__SAI2_TX_BCLK = IOMUX_PAD(0x0428, 0x01C0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI2_TXC__SAI5_TX_DATA2 = IOMUX_PAD(0x0428, 0x01C0, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI2_TXC__GPIO4_IO25 = IOMUX_PAD(0x0428, 0x01C0, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI2_TXD0__SAI2_TX_DATA0 = IOMUX_PAD(0x042C, 0x01C4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI2_TXD0__SAI5_TX_DATA3 = IOMUX_PAD(0x042C, 0x01C4, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI2_TXD0__GPIO4_IO26 = IOMUX_PAD(0x042C, 0x01C4, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI2_MCLK__SAI2_MCLK = IOMUX_PAD(0x0430, 0x01C8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI2_MCLK__SAI5_MCLK = IOMUX_PAD(0x0430, 0x01C8, 1, 0x052C, 2, 0), - IMX8MQ_PAD_SAI2_MCLK__GPIO4_IO27 = IOMUX_PAD(0x0430, 0x01C8, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI3_RXFS__SAI3_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_RXFS__GPT1_CAPTURE1 = IOMUX_PAD(0x0434, 0x01CC, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_RXFS__SAI5_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 2, 0x04E4, 2, 0), - IMX8MQ_PAD_SAI3_RXFS__GPIO4_IO28 = IOMUX_PAD(0x0434, 0x01CC, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI3_RXC__SAI3_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_RXC__GPT1_CAPTURE2 = IOMUX_PAD(0x0438, 0x01D0, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_RXC__SAI5_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 2, 0x04D0, 2, 0), - IMX8MQ_PAD_SAI3_RXC__GPIO4_IO29 = IOMUX_PAD(0x0438, 0x01D0, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI3_RXD__SAI3_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_RXD__GPT1_COMPARE1 = IOMUX_PAD(0x043C, 0x01D4, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_RXD__SAI5_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 2, 0x04D4, 2, 0), - IMX8MQ_PAD_SAI3_RXD__GPIO4_IO30 = IOMUX_PAD(0x043C, 0x01D4, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI3_TXFS__SAI3_TX_SYNC = IOMUX_PAD(0x0440, 0x01D8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_TXFS__GPT1_CLK = IOMUX_PAD(0x0440, 0x01D8, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_TXFS__SAI5_RX_DATA1 = IOMUX_PAD(0x0440, 0x01D8, 2, 0x04D8, 2, 0), - IMX8MQ_PAD_SAI3_TXFS__GPIO4_IO31 = IOMUX_PAD(0x0440, 0x01D8, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI3_TXC__SAI3_TX_BCLK = IOMUX_PAD(0x0444, 0x01DC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_TXC__GPT1_COMPARE2 = IOMUX_PAD(0x0444, 0x01DC, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_TXC__SAI5_RX_DATA2 = IOMUX_PAD(0x0444, 0x01DC, 2, 0x04DC, 2, 0), - IMX8MQ_PAD_SAI3_TXC__GPIO5_IO0 = IOMUX_PAD(0x0444, 0x01DC, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI3_TXD__SAI3_TX_DATA0 = IOMUX_PAD(0x0448, 0x01E0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_TXD__GPT1_COMPARE3 = IOMUX_PAD(0x0448, 0x01E0, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_TXD__SAI5_RX_DATA3 = IOMUX_PAD(0x0448, 0x01E0, 2, 0x04E0, 2, 0), - IMX8MQ_PAD_SAI3_TXD__GPIO5_IO1 = IOMUX_PAD(0x0448, 0x01E0, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI3_MCLK__SAI3_MCLK = IOMUX_PAD(0x044C, 0x01E4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_MCLK__PWM4_OUT = IOMUX_PAD(0x044C, 0x01E4, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_MCLK__SAI5_MCLK = IOMUX_PAD(0x044C, 0x01E4, 2, 0x052C, 3, 0), - IMX8MQ_PAD_SAI3_MCLK__GPIO5_IO2 = IOMUX_PAD(0x044C, 0x01E4, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SPDIF_TX__SPDIF1_OUT = IOMUX_PAD(0x0450, 0x01E8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SPDIF_TX__PWM3_OUT = IOMUX_PAD(0x0450, 0x01E8, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SPDIF_TX__GPIO5_IO3 = IOMUX_PAD(0x0450, 0x01E8, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SPDIF_RX__SPDIF1_IN = IOMUX_PAD(0x0454, 0x01EC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SPDIF_RX__PWM2_OUT = IOMUX_PAD(0x0454, 0x01EC, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SPDIF_RX__GPIO5_IO4 = IOMUX_PAD(0x0454, 0x01EC, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SPDIF_EXT_CLK__SPDIF1_EXT_CLK = IOMUX_PAD(0x0458, 0x01F0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SPDIF_EXT_CLK__PWM1_OUT = IOMUX_PAD(0x0458, 0x01F0, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SPDIF_EXT_CLK__GPIO5_IO5 = IOMUX_PAD(0x0458, 0x01F0, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ECSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x045C, 0x01F4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ECSPI1_SCLK__UART3_RX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0504, 0, 0), - IMX8MQ_PAD_ECSPI1_SCLK__GPIO5_IO6 = IOMUX_PAD(0x045C, 0x01F4, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ECSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x0460, 0x01F8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ECSPI1_MOSI__UART3_TX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0504, 1, 0), - IMX8MQ_PAD_ECSPI1_MOSI__GPIO5_IO7 = IOMUX_PAD(0x0460, 0x01F8, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ECSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x0464, 0x01FC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ECSPI1_MISO__UART3_CTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0500, 0, 0), - IMX8MQ_PAD_ECSPI1_MISO__GPIO5_IO8 = IOMUX_PAD(0x0464, 0x01FC, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ECSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x0468, 0x0200, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ECSPI1_SS0__UART3_RTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0500, 1, 0), - IMX8MQ_PAD_ECSPI1_SS0__GPIO5_IO9 = IOMUX_PAD(0x0468, 0x0200, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ECSPI2_SCLK__ECSPI2_SCLK = IOMUX_PAD(0x046C, 0x0204, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ECSPI2_SCLK__UART4_RX = IOMUX_PAD(0x046C, 0x0204, 1, 0x050C, 0, 0), - IMX8MQ_PAD_ECSPI2_SCLK__GPIO5_IO10 = IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ECSPI2_MOSI__ECSPI2_MOSI = IOMUX_PAD(0x0470, 0x0208, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ECSPI2_MOSI__UART4_TX = IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0), - IMX8MQ_PAD_ECSPI2_MOSI__GPIO5_IO11 = IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ECSPI2_MISO__ECSPI2_MISO = IOMUX_PAD(0x0474, 0x020C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ECSPI2_MISO__UART4_CTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0508, 0, 0), - IMX8MQ_PAD_ECSPI2_MISO__GPIO5_IO12 = IOMUX_PAD(0x0474, 0x020C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ECSPI2_SS0__ECSPI2_SS0 = IOMUX_PAD(0x0478, 0x0210, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ECSPI2_SS0__UART4_RTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0508, 1, 0), - IMX8MQ_PAD_ECSPI2_SS0__GPIO5_IO13 = IOMUX_PAD(0x0478, 0x0210, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x047C, 0x0214, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), - IMX8MQ_PAD_I2C1_SCL__ENET_MDC = IOMUX_PAD(0x047C, 0x0214, 1, 0x0000, 0, 0), - IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 = IOMUX_PAD(0x047C, 0x0214, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0480, 0x0218, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), - IMX8MQ_PAD_I2C1_SDA__ENET_MDIO = IOMUX_PAD(0x0480, 0x0218, 1, 0x04C0, 2, 0), - IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 = IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_I2C2_SCL__I2C2_SCL = IOMUX_PAD(0x0484, 0x021C, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), - IMX8MQ_PAD_I2C2_SCL__ENET_1588_EVENT1_IN = IOMUX_PAD(0x0484, 0x021C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_I2C2_SCL__GPIO5_IO16 = IOMUX_PAD(0x0484, 0x021C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_I2C2_SDA__I2C2_SDA = IOMUX_PAD(0x0488, 0x0220, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), - IMX8MQ_PAD_I2C2_SDA__ENET_1588_EVENT1_OUT = IOMUX_PAD(0x0488, 0x0220, 1, 0x0000, 0, 0), - IMX8MQ_PAD_I2C2_SDA__GPIO5_IO17 = IOMUX_PAD(0x0488, 0x0220, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_I2C3_SCL__I2C3_SCL = IOMUX_PAD(0x048C, 0x0224, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), - IMX8MQ_PAD_I2C3_SCL__PWM4_OUT = IOMUX_PAD(0x048C, 0x0224, 1, 0x0000, 0, 0), - IMX8MQ_PAD_I2C3_SCL__GPT2_CLK = IOMUX_PAD(0x048C, 0x0224, 2, 0x0000, 0, 0), - IMX8MQ_PAD_I2C3_SCL__GPIO5_IO18 = IOMUX_PAD(0x048C, 0x0224, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_I2C3_SDA__I2C3_SDA = IOMUX_PAD(0x0490, 0x0228, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), - IMX8MQ_PAD_I2C3_SDA__PWM3_OUT = IOMUX_PAD(0x0490, 0x0228, 1, 0x0000, 0, 0), - IMX8MQ_PAD_I2C3_SDA__GPT3_CLK = IOMUX_PAD(0x0490, 0x0228, 2, 0x0000, 0, 0), - IMX8MQ_PAD_I2C3_SDA__GPIO5_IO19 = IOMUX_PAD(0x0490, 0x0228, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_I2C4_SCL__I2C4_SCL = IOMUX_PAD(0x0494, 0x022C, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), - IMX8MQ_PAD_I2C4_SCL__PWM2_OUT = IOMUX_PAD(0x0494, 0x022C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_I2C4_SCL__PCIE1_CLKREQ_B = IOMUX_PAD(0x0494, 0x022C, 2, 0x0524, 0, 0), - IMX8MQ_PAD_I2C4_SCL__GPIO5_IO20 = IOMUX_PAD(0x0494, 0x022C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_I2C4_SDA__I2C4_SDA = IOMUX_PAD(0x0498, 0x0230, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), - IMX8MQ_PAD_I2C4_SDA__PWM1_OUT = IOMUX_PAD(0x0498, 0x0230, 1, 0x0000, 0, 0), - IMX8MQ_PAD_I2C4_SDA__PCIE2_CLKREQ_B = IOMUX_PAD(0x0498, 0x0230, 2, 0x0528, 0, 0), - IMX8MQ_PAD_I2C4_SDA__GPIO5_IO21 = IOMUX_PAD(0x0498, 0x0230, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_UART1_RXD__UART1_RX = IOMUX_PAD(0x049C, 0x0234, 0, 0x04F4, 0, 0), - IMX8MQ_PAD_UART1_RXD__ECSPI3_SCLK = IOMUX_PAD(0x049C, 0x0234, 1, 0x0000, 0, 0), - IMX8MQ_PAD_UART1_RXD__GPIO5_IO22 = IOMUX_PAD(0x049C, 0x0234, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_UART1_TXD__UART1_TX = IOMUX_PAD(0x04A0, 0x0238, 0, 0x0000, 0, 0), - IMX8MQ_PAD_UART1_TXD__ECSPI3_MOSI = IOMUX_PAD(0x04A0, 0x0238, 1, 0x0000, 0, 0), - IMX8MQ_PAD_UART1_TXD__GPIO5_IO23 = IOMUX_PAD(0x04A0, 0x0238, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_UART2_RXD__UART2_RX = IOMUX_PAD(0x04A4, 0x023C, 0, 0x04FC, 0, 0), - IMX8MQ_PAD_UART2_RXD__ECSPI3_MISO = IOMUX_PAD(0x04A4, 0x023C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_UART2_RXD__GPIO5_IO24 = IOMUX_PAD(0x04A4, 0x023C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_UART2_TXD__UART2_TX = IOMUX_PAD(0x04A8, 0x0240, 0, 0x0000, 0, 0), - IMX8MQ_PAD_UART2_TXD__ECSPI3_SS0 = IOMUX_PAD(0x04A8, 0x0240, 1, 0x0000, 0, 0), - IMX8MQ_PAD_UART2_TXD__GPIO5_IO25 = IOMUX_PAD(0x04A8, 0x0240, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_UART3_RXD__UART3_RX = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0504, 2, 0), - IMX8MQ_PAD_UART3_RXD__UART1_CTS_B = IOMUX_PAD(0x04AC, 0x0244, 1, 0x04F0, 0, 0), - IMX8MQ_PAD_UART3_RXD__GPIO5_IO26 = IOMUX_PAD(0x04AC, 0x0244, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_UART3_TXD__UART3_TX = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0000, 0, 0), - IMX8MQ_PAD_UART3_TXD__UART1_RTS_B = IOMUX_PAD(0x04B0, 0x0248, 1, 0x04F0, 1, 0), - IMX8MQ_PAD_UART3_TXD__GPIO5_IO27 = IOMUX_PAD(0x04B0, 0x0248, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_UART4_RXD__UART4_RX = IOMUX_PAD(0x04B4, 0x024C, 0, 0x050C, 2, 0), - IMX8MQ_PAD_UART4_RXD__UART2_CTS_B = IOMUX_PAD(0x04B4, 0x024C, 1, 0x04F8, 0, 0), - IMX8MQ_PAD_UART4_RXD__PCIE1_CLKREQ_B = IOMUX_PAD(0x04B4, 0x024C, 2, 0x0524, 1, 0), - IMX8MQ_PAD_UART4_RXD__GPIO5_IO28 = IOMUX_PAD(0x04B4, 0x024C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_UART4_TXD__UART4_TX = IOMUX_PAD(0x04B8, 0x0250, 0, 0x0000, 0, 0), - IMX8MQ_PAD_UART4_TXD__UART2_RTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x04F8, 1, 0), - IMX8MQ_PAD_UART4_TXD__PCIE2_CLKREQ_B = IOMUX_PAD(0x04B8, 0x0250, 2, 0x0528, 1, 0), - IMX8MQ_PAD_UART4_TXD__GPIO5_IO29 = IOMUX_PAD(0x04B8, 0x0250, 5, 0x0000, 0, 0), -}; - -static inline void mx8_setup_pad(void __iomem *iomux, iomux_v3_cfg_t pad) -{ - unsigned int flags = 0; - uint32_t mode = IOMUX_MODE(pad); - - if (mode & IOMUX_CONFIG_LPSR) { - mode &= ~IOMUX_CONFIG_LPSR; - flags = ZERO_OFFSET_VALID | IMX7_PINMUX_LPSR; - } - - iomux_v3_setup_pad(iomux, flags, - IOMUX_CTRL_OFS(pad), - IOMUX_PAD_CTRL_OFS(pad), - IOMUX_SEL_INPUT_OFS(pad), - mode, - IOMUX_PAD_CTRL(pad), - IOMUX_SEL_INPUT(pad)); -} - -#endif diff --git a/arch/arm/mach-imx/include/mach/iomux-mx8m.h b/arch/arm/mach-imx/include/mach/iomux-mx8m.h new file mode 100644 index 0000000000..de6675064a --- /dev/null +++ b/arch/arm/mach-imx/include/mach/iomux-mx8m.h @@ -0,0 +1,27 @@ +#ifndef __MACH_IOMUX_IMX8M_H__ +#define __MACH_IOMUX_IMX8M_H__ + +#include + +#define PAD_CTL_DSE_3P3V_45_OHM 0b110 + +static inline void imx8m_setup_pad(void __iomem *iomux, iomux_v3_cfg_t pad) +{ + unsigned int flags = 0; + uint32_t mode = IOMUX_MODE(pad); + + if (mode & IOMUX_CONFIG_LPSR) { + mode &= ~IOMUX_CONFIG_LPSR; + flags = ZERO_OFFSET_VALID | IMX7_PINMUX_LPSR; + } + + iomux_v3_setup_pad(iomux, flags, + IOMUX_CTRL_OFS(pad), + IOMUX_PAD_CTRL_OFS(pad), + IOMUX_SEL_INPUT_OFS(pad), + mode, + IOMUX_PAD_CTRL(pad), + IOMUX_SEL_INPUT(pad)); +} + +#endif /* __MACH_IOMUX_IMX8MQ_H__ */ diff --git a/arch/arm/mach-imx/include/mach/iomux-mx8mq.h b/arch/arm/mach-imx/include/mach/iomux-mx8mq.h new file mode 100644 index 0000000000..5c94731ea7 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/iomux-mx8mq.h @@ -0,0 +1,625 @@ +/* + * Copyright (C) 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MACH_IOMUX_IMX8MQ_H__ +#define __MACH_IOMUX_IMX8MQ_H__ + +#include +#include + +enum { + IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0 = IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT = IOMUX_PAD(0x0290, 0x0028, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO00__XTALOSC_REF_CLK_32K = IOMUX_PAD(0x0290, 0x0028, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO00__CCM_EXT_CLK1 = IOMUX_PAD(0x0290, 0x0028, 6, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO00__JTAG_FAIL = IOMUX_PAD(0x0290, 0x0028, 7, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO01__GPIO1_IO1 = IOMUX_PAD(0x0294, 0x002C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO01__PWM1_OUT = IOMUX_PAD(0x0294, 0x002C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO01__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x0294, 0x002C, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO01__CCM_EXT_CLK2 = IOMUX_PAD(0x0294, 0x002C, 6, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO01__JTAG_ACTIVE = IOMUX_PAD(0x0294, 0x002C, 7, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO02__GPIO1_IO2 = IOMUX_PAD(0x0298, 0x0030, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B = IOMUX_PAD(0x0298, 0x0030, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_ANY = IOMUX_PAD(0x0298, 0x0030, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO02__JTAG_DE_B = IOMUX_PAD(0x0298, 0x0030, 7, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO03__GPIO1_IO3 = IOMUX_PAD(0x029C, 0x0034, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO03__USDHC1_VSELECT = IOMUX_PAD(0x029C, 0x0034, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO03__SDMA1_EXT_EVENT0 = IOMUX_PAD(0x029C, 0x0034, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO03__XTALOSC_XTAL_OK = IOMUX_PAD(0x029C, 0x0034, 6, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO03__JTAG_DONE = IOMUX_PAD(0x029C, 0x0034, 7, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 = IOMUX_PAD(0x02A0, 0x0038, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO04__USDHC2_VSELECT = IOMUX_PAD(0x02A0, 0x0038, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO04__SDMA1_EXT_EVENT1 = IOMUX_PAD(0x02A0, 0x0038, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO04__XTALOSC_XTAL_OK_1V = IOMUX_PAD(0x02A0, 0x0038, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO05__GPIO1_IO5 = IOMUX_PAD(0x02A4, 0x003C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO05__ARM_PLATFORM_CM4_NMI = IOMUX_PAD(0x02A4, 0x003C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO05__CCM_PMIC_READY = IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0), + IMX8MQ_PAD_GPIO1_IO05__SRC_INT_BOOT = IOMUX_PAD(0x02A4, 0x003C, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO06__GPIO1_IO6 = IOMUX_PAD(0x02A8, 0x0040, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO06__ENET_MDC = IOMUX_PAD(0x02A8, 0x0040, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO06__USDHC1_CD_B = IOMUX_PAD(0x02A8, 0x0040, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO06__CCM_EXT_CLK3 = IOMUX_PAD(0x02A8, 0x0040, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO07__GPIO1_IO7 = IOMUX_PAD(0x02AC, 0x0044, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO07__ENET_MDIO = IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0), + IMX8MQ_PAD_GPIO1_IO07__USDHC1_WP = IOMUX_PAD(0x02AC, 0x0044, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO07__CCM_EXT_CLK4 = IOMUX_PAD(0x02AC, 0x0044, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8 = IOMUX_PAD(0x02B0, 0x0048, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO08__ENET_1588_EVENT0_IN = IOMUX_PAD(0x02B0, 0x0048, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO08__USDHC2_RESET_B = IOMUX_PAD(0x02B0, 0x0048, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO08__CCM_WAIT = IOMUX_PAD(0x02B0, 0x0048, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 = IOMUX_PAD(0x02B4, 0x004C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO09__ENET_1588_EVENT0_OUT = IOMUX_PAD(0x02B4, 0x004C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO09__SDMA2_EXT_EVENT0 = IOMUX_PAD(0x02B4, 0x004C, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO09__CCM_STOP = IOMUX_PAD(0x02B4, 0x004C, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO10__GPIO1_IO10 = IOMUX_PAD(0x02B8, 0x0050, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO10__USB1_OTG_ID = IOMUX_PAD(0x02B8, 0x0050, 1, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO11__GPIO1_IO11 = IOMUX_PAD(0x02BC, 0x0054, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO11__USB2_OTG_ID = IOMUX_PAD(0x02BC, 0x0054, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO11__CCM_PMIC_READY = IOMUX_PAD(0x02BC, 0x0054, 5, 0x04BC, 1, 0), + + IMX8MQ_PAD_GPIO1_IO12__GPIO1_IO12 = IOMUX_PAD(0x02C0, 0x0058, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO12__USB1_OTG_PWR = IOMUX_PAD(0x02C0, 0x0058, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO12__SDMA2_EXT_EVENT1 = IOMUX_PAD(0x02C0, 0x0058, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT0 = IOMUX_PAD(0x02C0, 0x0058, 7, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO13__GPIO1_IO13 = IOMUX_PAD(0x02C4, 0x005C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO13__USB1_OTG_OC = IOMUX_PAD(0x02C4, 0x005C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO13__PWM2_OUT = IOMUX_PAD(0x02C4, 0x005C, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT1 = IOMUX_PAD(0x02C4, 0x005C, 7, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14 = IOMUX_PAD(0x02C8, 0x0060, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO14__USB2_OTG_PWR = IOMUX_PAD(0x02C8, 0x0060, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO14__PWM3_OUT = IOMUX_PAD(0x02C8, 0x0060, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO14__CCM_CLKO1 = IOMUX_PAD(0x02C8, 0x0060, 6, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO14__CSU_CSU_ALARM_AUT2 = IOMUX_PAD(0x02C8, 0x0060, 7, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO15__GPIO1_IO15 = IOMUX_PAD(0x02CC, 0x0064, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO15__USB2_OTG_OC = IOMUX_PAD(0x02CC, 0x0064, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO15__PWM4_OUT = IOMUX_PAD(0x02CC, 0x0064, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO15__CCM_CLKO2 = IOMUX_PAD(0x02CC, 0x0064, 6, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO15__CSU_CSU_INT_DEB = IOMUX_PAD(0x02CC, 0x0064, 7, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x02D0, 0x0068, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_MDC__GPIO1_IO16 = IOMUX_PAD(0x02D0, 0x0068, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x02D4, 0x006C, 0, 0x04C0, 1, 0), + IMX8MQ_PAD_ENET_MDIO__GPIO1_IO17 = IOMUX_PAD(0x02D4, 0x006C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x02D8, 0x0070, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_TD3__GPIO1_IO18 = IOMUX_PAD(0x02D8, 0x0070, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x02DC, 0x0074, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_TD2__ENET_TX_CLK = IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_TD2__GPIO1_IO19 = IOMUX_PAD(0x02DC, 0x0074, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x02E0, 0x0078, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_TD1__GPIO1_IO20 = IOMUX_PAD(0x02E0, 0x0078, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x02E4, 0x007C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_TD0__GPIO1_IO21 = IOMUX_PAD(0x02E4, 0x007C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_TX_CTL__ENET_RGMII_TX_CTL = IOMUX_PAD(0x02E8, 0x0080, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_TX_CTL__GPIO1_IO22 = IOMUX_PAD(0x02E8, 0x0080, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x02EC, 0x0084, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_TXC__ENET_TX_ER = IOMUX_PAD(0x02EC, 0x0084, 1, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_TXC__GPIO1_IO23 = IOMUX_PAD(0x02EC, 0x0084, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_RX_CTL__ENET_RGMII_RX_CTL = IOMUX_PAD(0x02F0, 0x0088, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_RX_CTL__GPIO1_IO24 = IOMUX_PAD(0x02F0, 0x0088, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x02F4, 0x008C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_RXC__ENET_RX_ER = IOMUX_PAD(0x02F4, 0x008C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_RXC__GPIO1_IO25 = IOMUX_PAD(0x02F4, 0x008C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x02F8, 0x0090, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_RD0__GPIO1_IO26 = IOMUX_PAD(0x02F8, 0x0090, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x02FC, 0x0094, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_RD1__GPIO1_IO27 = IOMUX_PAD(0x02FC, 0x0094, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x0300, 0x0098, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_RD2__GPIO1_IO28 = IOMUX_PAD(0x0300, 0x0098, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x0304, 0x009C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_RD3__GPIO1_IO29 = IOMUX_PAD(0x0304, 0x009C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0308, 0x00A0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_CLK__GPIO2_IO0 = IOMUX_PAD(0x0308, 0x00A0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x030C, 0x00A4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_CMD__GPIO2_IO1 = IOMUX_PAD(0x030C, 0x00A4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x0310, 0x00A8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_DATA0__GPIO2_IO2 = IOMUX_PAD(0x0310, 0x00A8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x0314, 0x00AC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_DATA1__GPIO2_IO3 = IOMUX_PAD(0x0314, 0x00AC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x0318, 0x00B0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_DATA2__GPIO2_IO4 = IOMUX_PAD(0x0318, 0x00B0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x031C, 0x00B4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_DATA3__GPIO2_IO5 = IOMUX_PAD(0x031C, 0x00B4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 = IOMUX_PAD(0x0320, 0x00B8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_DATA4__GPIO2_IO6 = IOMUX_PAD(0x0320, 0x00B8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 = IOMUX_PAD(0x0324, 0x00BC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_DATA5__GPIO2_IO7 = IOMUX_PAD(0x0324, 0x00BC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 = IOMUX_PAD(0x0328, 0x00C0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_DATA6__GPIO2_IO8 = IOMUX_PAD(0x0328, 0x00C0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 = IOMUX_PAD(0x032C, 0x00C4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_DATA7__GPIO2_IO9 = IOMUX_PAD(0x032C, 0x00C4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_RESET_B__USDHC1_RESET_B = IOMUX_PAD(0x0330, 0x00C8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 = IOMUX_PAD(0x0330, 0x00C8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_STROBE__USDHC1_STROBE = IOMUX_PAD(0x0334, 0x00CC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_STROBE__GPIO2_IO11 = IOMUX_PAD(0x0334, 0x00CC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_CD_B__USDHC2_CD_B = IOMUX_PAD(0x0338, 0x00D0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 = IOMUX_PAD(0x0338, 0x00D0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x033C, 0x00D4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_CLK__GPIO2_IO13 = IOMUX_PAD(0x033C, 0x00D4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0340, 0x00D8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_CMD__GPIO2_IO14 = IOMUX_PAD(0x0340, 0x00D8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 = IOMUX_PAD(0x0344, 0x00DC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_DATA0__GPIO2_IO15 = IOMUX_PAD(0x0344, 0x00DC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 = IOMUX_PAD(0x0348, 0x00E0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_DATA1__GPIO2_IO16 = IOMUX_PAD(0x0348, 0x00E0, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_DATA1__CCM_WAIT = IOMUX_PAD(0x0348, 0x00E0, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 = IOMUX_PAD(0x034C, 0x00E4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_DATA2__GPIO2_IO17 = IOMUX_PAD(0x034C, 0x00E4, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_DATA2__CCM_STOP = IOMUX_PAD(0x034C, 0x00E4, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 = IOMUX_PAD(0x0350, 0x00E8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_DATA3__GPIO2_IO18 = IOMUX_PAD(0x0350, 0x00E8, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_DATA3__SRC_EARLY_RESET = IOMUX_PAD(0x0350, 0x00E8, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_RESET_B__USDHC2_RESET_B = IOMUX_PAD(0x0354, 0x00EC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 = IOMUX_PAD(0x0354, 0x00EC, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_RESET_B__SRC_SYSTEM_RESET = IOMUX_PAD(0x0354, 0x00EC, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_WP__USDHC2_WP = IOMUX_PAD(0x0358, 0x00F0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_WP__GPIO2_IO20 = IOMUX_PAD(0x0358, 0x00F0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_ALE__RAWNAND_ALE = IOMUX_PAD(0x035C, 0x00F4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK = IOMUX_PAD(0x035C, 0x00F4, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_ALE__GPIO3_IO0 = IOMUX_PAD(0x035C, 0x00F4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_CE0_B__RAWNAND_CE0_B = IOMUX_PAD(0x0360, 0x00F8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B = IOMUX_PAD(0x0360, 0x00F8, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CE0_B__GPIO3_IO1 = IOMUX_PAD(0x0360, 0x00F8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_CE1_B__RAWNAND_CE1_B = IOMUX_PAD(0x0364, 0x00FC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CE1_B__QSPI_A_SS1_B = IOMUX_PAD(0x0364, 0x00FC, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CE1_B__GPIO3_IO2 = IOMUX_PAD(0x0364, 0x00FC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_CE2_B__RAWNAND_CE2_B = IOMUX_PAD(0x0368, 0x0100, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CE2_B__QSPI_B_SS0_B = IOMUX_PAD(0x0368, 0x0100, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CE2_B__GPIO3_IO3 = IOMUX_PAD(0x0368, 0x0100, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_CE3_B__RAWNAND_CE3_B = IOMUX_PAD(0x036C, 0x0104, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CE3_B__QSPI_B_SS1_B = IOMUX_PAD(0x036C, 0x0104, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CE3_B__GPIO3_IO4 = IOMUX_PAD(0x036C, 0x0104, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_CLE__RAWNAND_CLE = IOMUX_PAD(0x0370, 0x0108, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CLE__QSPI_B_SCLK = IOMUX_PAD(0x0370, 0x0108, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CLE__GPIO3_IO5 = IOMUX_PAD(0x0370, 0x0108, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DATA00__RAWNAND_DATA00 = IOMUX_PAD(0x0374, 0x010C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0 = IOMUX_PAD(0x0374, 0x010C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA00__GPIO3_IO6 = IOMUX_PAD(0x0374, 0x010C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DATA01__RAWNAND_DATA01 = IOMUX_PAD(0x0378, 0x0110, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1 = IOMUX_PAD(0x0378, 0x0110, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA01__GPIO3_IO7 = IOMUX_PAD(0x0378, 0x0110, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DATA02__RAWNAND_DATA02 = IOMUX_PAD(0x037C, 0x0114, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2 = IOMUX_PAD(0x037C, 0x0114, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA02__GPIO3_IO8 = IOMUX_PAD(0x037C, 0x0114, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DATA03__RAWNAND_DATA03 = IOMUX_PAD(0x0380, 0x0118, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3 = IOMUX_PAD(0x0380, 0x0118, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA03__GPIO3_IO9 = IOMUX_PAD(0x0380, 0x0118, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DATA04__RAWNAND_DATA04 = IOMUX_PAD(0x0384, 0x011C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA04__QSPI_B_DATA0 = IOMUX_PAD(0x0384, 0x011C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA04__GPIO3_IO10 = IOMUX_PAD(0x0384, 0x011C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DATA05__RAWNAND_DATA05 = IOMUX_PAD(0x0388, 0x0120, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA05__QSPI_B_DATA1 = IOMUX_PAD(0x0388, 0x0120, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA05__GPIO3_IO11 = IOMUX_PAD(0x0388, 0x0120, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DATA06__RAWNAND_DATA06 = IOMUX_PAD(0x038C, 0x0124, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA06__QSPI_B_DATA2 = IOMUX_PAD(0x038C, 0x0124, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12 = IOMUX_PAD(0x038C, 0x0124, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DATA07__RAWNAND_DATA07 = IOMUX_PAD(0x0390, 0x0128, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA07__QSPI_B_DATA3 = IOMUX_PAD(0x0390, 0x0128, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA07__GPIO3_IO13 = IOMUX_PAD(0x0390, 0x0128, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DQS__RAWNAND_DQS = IOMUX_PAD(0x0394, 0x012C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DQS__QSPI_A_DQS = IOMUX_PAD(0x0394, 0x012C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DQS__GPIO3_IO14 = IOMUX_PAD(0x0394, 0x012C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_RE_B__RAWNAND_RE_B = IOMUX_PAD(0x0398, 0x0130, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_RE_B__QSPI_B_DQS = IOMUX_PAD(0x0398, 0x0130, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 = IOMUX_PAD(0x0398, 0x0130, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_READY_B__RAWNAND_READY_B = IOMUX_PAD(0x039C, 0x0134, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_READY_B__GPIO3_IO16 = IOMUX_PAD(0x039C, 0x0134, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_WE_B__RAWNAND_WE_B = IOMUX_PAD(0x03A0, 0x0138, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_WE_B__GPIO3_IO17 = IOMUX_PAD(0x03A0, 0x0138, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_WP_B__RAWNAND_WP_B = IOMUX_PAD(0x03A4, 0x013C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_WP_B__GPIO3_IO18 = IOMUX_PAD(0x03A4, 0x013C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI5_RXFS__SAI5_RX_SYNC = IOMUX_PAD(0x03A8, 0x0140, 0, 0x04E4, 0, 0), + IMX8MQ_PAD_SAI5_RXFS__SAI1_TX_DATA0 = IOMUX_PAD(0x03A8, 0x0140, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_RXFS__GPIO3_IO19 = IOMUX_PAD(0x03A8, 0x0140, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI5_RXC__SAI5_RX_BCLK = IOMUX_PAD(0x03AC, 0x0144, 0, 0x04D0, 0, 0), + IMX8MQ_PAD_SAI5_RXC__SAI1_TX_DATA1 = IOMUX_PAD(0x03AC, 0x0144, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_RXC__GPIO3_IO20 = IOMUX_PAD(0x03AC, 0x0144, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI5_RXD0__SAI5_RX_DATA0 = IOMUX_PAD(0x03B0, 0x0148, 0, 0x04D4, 0, 0), + IMX8MQ_PAD_SAI5_RXD0__SAI1_TX_DATA2 = IOMUX_PAD(0x03B0, 0x0148, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_RXD0__GPIO3_IO21 = IOMUX_PAD(0x03B0, 0x0148, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI5_RXD1__SAI5_RX_DATA1 = IOMUX_PAD(0x03B4, 0x014C, 0, 0x04D8, 0, 0), + IMX8MQ_PAD_SAI5_RXD1__SAI1_TX_DATA3 = IOMUX_PAD(0x03B4, 0x014C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_RXD1__SAI1_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 2, 0x04CC, 0, 0), + IMX8MQ_PAD_SAI5_RXD1__SAI5_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 3, 0x04EC, 0, 0), + IMX8MQ_PAD_SAI5_RXD1__GPIO3_IO22 = IOMUX_PAD(0x03B4, 0x014C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI5_RXD2__SAI5_RX_DATA2 = IOMUX_PAD(0x03B8, 0x0150, 0, 0x04DC, 0, 0), + IMX8MQ_PAD_SAI5_RXD2__SAI1_TX_DATA4 = IOMUX_PAD(0x03B8, 0x0150, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_RXD2__SAI1_TX_SYNC = IOMUX_PAD(0x03B8, 0x0150, 2, 0x04CC, 1, 0), + IMX8MQ_PAD_SAI5_RXD2__SAI5_TX_BCLK = IOMUX_PAD(0x03B8, 0x0150, 3, 0x04E8, 0, 0), + IMX8MQ_PAD_SAI5_RXD2__GPIO3_IO23 = IOMUX_PAD(0x03B8, 0x0150, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI5_RXD3__SAI5_RX_DATA3 = IOMUX_PAD(0x03BC, 0x0154, 0, 0x04E0, 0, 0), + IMX8MQ_PAD_SAI5_RXD3__SAI1_TX_DATA5 = IOMUX_PAD(0x03BC, 0x0154, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_RXD3__SAI1_TX_SYNC = IOMUX_PAD(0x03BC, 0x0154, 2, 0x04CC, 2, 0), + IMX8MQ_PAD_SAI5_RXD3__SAI5_TX_DATA0 = IOMUX_PAD(0x03BC, 0x0154, 3, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_RXD3__GPIO3_IO24 = IOMUX_PAD(0x03BC, 0x0154, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI5_MCLK__SAI5_MCLK = IOMUX_PAD(0x03C0, 0x0158, 0, 0x052C, 0, 0), + IMX8MQ_PAD_SAI5_MCLK__SAI1_TX_BCLK = IOMUX_PAD(0x03C0, 0x0158, 1, 0x04C8, 0, 0), + IMX8MQ_PAD_SAI5_MCLK__SAI4_MCLK = IOMUX_PAD(0x03C0, 0x0158, 2, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_MCLK__GPIO3_IO25 = IOMUX_PAD(0x03C0, 0x0158, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_MCLK__SRC_TESTER_ACK = IOMUX_PAD(0x03C0, 0x0158, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXFS__SAI1_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 0, 0x04C4, 0, 0), + IMX8MQ_PAD_SAI1_RXFS__SAI5_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 1, 0x04E4, 1, 0), + IMX8MQ_PAD_SAI1_RXFS__ARM_PLATFORM_TRACE_CLK = IOMUX_PAD(0x03C4, 0x015C, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXFS__GPIO4_IO0 = IOMUX_PAD(0x03C4, 0x015C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXC__SAI1_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXC__SAI5_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 1, 0x04D0, 1, 0), + IMX8MQ_PAD_SAI1_RXC__ARM_PLATFORM_TRACE_CTL = IOMUX_PAD(0x03C8, 0x0160, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXC__GPIO4_IO1 = IOMUX_PAD(0x03C8, 0x0160, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXD0__SAI1_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD0__SAI5_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 1, 0x04D4, 1, 0), + IMX8MQ_PAD_SAI1_RXD0__ARM_PLATFORM_TRACE0 = IOMUX_PAD(0x03CC, 0x0164, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD0__GPIO4_IO2 = IOMUX_PAD(0x03CC, 0x0164, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD0__SRC_BOOT_CFG0 = IOMUX_PAD(0x03CC, 0x0164, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXD1__SAI1_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD1__SAI5_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 1, 0x04D8, 1, 0), + IMX8MQ_PAD_SAI1_RXD1__ARM_PLATFORM_TRACE1 = IOMUX_PAD(0x03D0, 0x0168, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD1__GPIO4_IO3 = IOMUX_PAD(0x03D0, 0x0168, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD1__SRC_BOOT_CFG1 = IOMUX_PAD(0x03D0, 0x0168, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXD2__SAI1_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD2__SAI5_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 1, 0x04DC, 1, 0), + IMX8MQ_PAD_SAI1_RXD2__ARM_PLATFORM_TRACE2 = IOMUX_PAD(0x03D4, 0x016C, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD2__GPIO4_IO4 = IOMUX_PAD(0x03D4, 0x016C, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD2__SRC_BOOT_CFG2 = IOMUX_PAD(0x03D4, 0x016C, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXD3__SAI1_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 0, 0x04E0, 1, 0), + IMX8MQ_PAD_SAI1_RXD3__SAI5_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD3__ARM_PLATFORM_TRACE3 = IOMUX_PAD(0x03D8, 0x0170, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD3__GPIO4_IO5 = IOMUX_PAD(0x03D8, 0x0170, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD3__SRC_BOOT_CFG3 = IOMUX_PAD(0x03D8, 0x0170, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXD4__SAI1_RX_DATA4 = IOMUX_PAD(0x03DC, 0x0174, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD4__SAI6_TX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 1, 0x051C, 0, 0), + IMX8MQ_PAD_SAI1_RXD4__SAI6_RX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 2, 0x0510, 0, 0), + IMX8MQ_PAD_SAI1_RXD4__ARM_PLATFORM_TRACE4 = IOMUX_PAD(0x03DC, 0x0174, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD4__GPIO4_IO6 = IOMUX_PAD(0x03DC, 0x0174, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD4__SRC_BOOT_CFG4 = IOMUX_PAD(0x03DC, 0x0174, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXD5__SAI1_RX_DATA5 = IOMUX_PAD(0x03E0, 0x0178, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD5__SAI6_TX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD5__SAI6_RX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 2, 0x0514, 0, 0), + IMX8MQ_PAD_SAI1_RXD5__SAI1_RX_SYNC = IOMUX_PAD(0x03E0, 0x0178, 3, 0x04C4, 1, 0), + IMX8MQ_PAD_SAI1_RXD5__ARM_PLATFORM_TRACE5 = IOMUX_PAD(0x03E0, 0x0178, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD5__GPIO4_IO7 = IOMUX_PAD(0x03E0, 0x0178, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD5__SRC_BOOT_CFG5 = IOMUX_PAD(0x03E0, 0x0178, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXD6__SAI1_RX_DATA6 = IOMUX_PAD(0x03E4, 0x017C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD6__SAI6_TX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 1, 0x0520, 0, 0), + IMX8MQ_PAD_SAI1_RXD6__SAI6_RX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 2, 0x0518, 0, 0), + IMX8MQ_PAD_SAI1_RXD6__ARM_PLATFORM_TRACE6 = IOMUX_PAD(0x03E4, 0x017C, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD6__GPIO4_IO8 = IOMUX_PAD(0x03E4, 0x017C, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD6__SRC_BOOT_CFG6 = IOMUX_PAD(0x03E4, 0x017C, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXD7__SAI1_RX_DATA7 = IOMUX_PAD(0x03E8, 0x0180, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD7__SAI6_MCLK = IOMUX_PAD(0x03E8, 0x0180, 1, 0x0530, 0, 0), + IMX8MQ_PAD_SAI1_RXD7__SAI1_TX_SYNC = IOMUX_PAD(0x03E8, 0x0180, 2, 0x04CC, 4, 0), + IMX8MQ_PAD_SAI1_RXD7__SAI1_TX_DATA4 = IOMUX_PAD(0x03E8, 0x0180, 3, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD7__ARM_PLATFORM_TRACE7 = IOMUX_PAD(0x03E8, 0x0180, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD7__GPIO4_IO9 = IOMUX_PAD(0x03E8, 0x0180, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD7__SRC_BOOT_CFG7 = IOMUX_PAD(0x03E8, 0x0180, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXFS__SAI1_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 0, 0x04CC, 3, 0), + IMX8MQ_PAD_SAI1_TXFS__SAI5_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 1, 0x04EC, 1, 0), + IMX8MQ_PAD_SAI1_TXFS__ARM_PLATFORM_EVENTO = IOMUX_PAD(0x03EC, 0x0184, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXFS__GPIO4_IO10 = IOMUX_PAD(0x03EC, 0x0184, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXC__SAI1_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 0, 0x04C8, 1, 0), + IMX8MQ_PAD_SAI1_TXC__SAI5_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 1, 0x04E8, 1, 0), + IMX8MQ_PAD_SAI1_TXC__ARM_PLATFORM_EVENTI = IOMUX_PAD(0x03F0, 0x0188, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXC__GPIO4_IO11 = IOMUX_PAD(0x03F0, 0x0188, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXD0__SAI1_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD0__SAI5_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD0__ARM_PLATFORM_TRACE8 = IOMUX_PAD(0x03F4, 0x018C, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD0__GPIO4_IO12 = IOMUX_PAD(0x03F4, 0x018C, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD0__SRC_BOOT_CFG8 = IOMUX_PAD(0x03F4, 0x018C, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXD1__SAI1_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD1__SAI5_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD1__ARM_PLATFORM_TRACE9 = IOMUX_PAD(0x03F8, 0x0190, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD1__GPIO4_IO13 = IOMUX_PAD(0x03F8, 0x0190, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD1__SRC_BOOT_CFG9 = IOMUX_PAD(0x03F8, 0x0190, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXD2__SAI1_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD2__SAI5_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD2__ARM_PLATFORM_TRACE10 = IOMUX_PAD(0x03FC, 0x0194, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD2__GPIO4_IO14 = IOMUX_PAD(0x03FC, 0x0194, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD2__SRC_BOOT_CFG10 = IOMUX_PAD(0x03FC, 0x0194, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXD3__SAI1_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD3__SAI5_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD3__ARM_PLATFORM_TRACE11 = IOMUX_PAD(0x0400, 0x0198, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD3__GPIO4_IO15 = IOMUX_PAD(0x0400, 0x0198, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD3__SRC_BOOT_CFG11 = IOMUX_PAD(0x0400, 0x0198, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXD4__SAI1_TX_DATA4 = IOMUX_PAD(0x0404, 0x019C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD4__SAI6_RX_BCLK = IOMUX_PAD(0x0404, 0x019C, 1, 0x0510, 1, 0), + IMX8MQ_PAD_SAI1_TXD4__SAI6_TX_BCLK = IOMUX_PAD(0x0404, 0x019C, 2, 0x051C, 1, 0), + IMX8MQ_PAD_SAI1_TXD4__ARM_PLATFORM_TRACE12 = IOMUX_PAD(0x0404, 0x019C, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD4__GPIO4_IO16 = IOMUX_PAD(0x0404, 0x019C, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD4__SRC_BOOT_CFG12 = IOMUX_PAD(0x0404, 0x019C, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXD5__SAI1_TX_DATA5 = IOMUX_PAD(0x0408, 0x01A0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD5__SAI6_RX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 1, 0x0514, 1, 0), + IMX8MQ_PAD_SAI1_TXD5__SAI6_TX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 2, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD5__ARM_PLATFORM_TRACE13 = IOMUX_PAD(0x0408, 0x01A0, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD5__GPIO4_IO17 = IOMUX_PAD(0x0408, 0x01A0, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD5__SRC_BOOT_CFG13 = IOMUX_PAD(0x0408, 0x01A0, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXD6__SAI1_TX_DATA6 = IOMUX_PAD(0x040C, 0x01A4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD6__SAI6_RX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 1, 0x0518, 1, 0), + IMX8MQ_PAD_SAI1_TXD6__SAI6_TX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 2, 0x0520, 1, 0), + IMX8MQ_PAD_SAI1_TXD6__ARM_PLATFORM_TRACE14 = IOMUX_PAD(0x040C, 0x01A4, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD6__GPIO4_IO18 = IOMUX_PAD(0x040C, 0x01A4, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD6__SRC_BOOT_CFG14 = IOMUX_PAD(0x040C, 0x01A4, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXD7__SAI1_TX_DATA7 = IOMUX_PAD(0x0410, 0x01A8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD7__SAI6_MCLK = IOMUX_PAD(0x0410, 0x01A8, 1, 0x0530, 1, 0), + IMX8MQ_PAD_SAI1_TXD7__ARM_PLATFORM_TRACE15 = IOMUX_PAD(0x0410, 0x01A8, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD7__GPIO4_IO19 = IOMUX_PAD(0x0410, 0x01A8, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD7__SRC_BOOT_CFG15 = IOMUX_PAD(0x0410, 0x01A8, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_MCLK__SAI1_MCLK = IOMUX_PAD(0x0414, 0x01AC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_MCLK__SAI5_MCLK = IOMUX_PAD(0x0414, 0x01AC, 1, 0x052C, 1, 0), + IMX8MQ_PAD_SAI1_MCLK__SAI1_TX_BCLK = IOMUX_PAD(0x0414, 0x01AC, 2, 0x04C8, 2, 0), + IMX8MQ_PAD_SAI1_MCLK__GPIO4_IO20 = IOMUX_PAD(0x0414, 0x01AC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI2_RXFS__SAI2_RX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_RXFS__SAI5_TX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 1, 0x04EC, 2, 0), + IMX8MQ_PAD_SAI2_RXFS__GPIO4_IO21 = IOMUX_PAD(0x0418, 0x01B0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI2_RXC__SAI2_RX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_RXC__SAI5_TX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 1, 0x04E8, 2, 0), + IMX8MQ_PAD_SAI2_RXC__GPIO4_IO22 = IOMUX_PAD(0x041C, 0x01B4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI2_RXD0__SAI2_RX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_RXD0__SAI5_TX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_RXD0__GPIO4_IO23 = IOMUX_PAD(0x0420, 0x01B8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI2_TXFS__SAI2_TX_SYNC = IOMUX_PAD(0x0424, 0x01BC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_TXFS__SAI5_TX_DATA1 = IOMUX_PAD(0x0424, 0x01BC, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_TXFS__GPIO4_IO24 = IOMUX_PAD(0x0424, 0x01BC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI2_TXC__SAI2_TX_BCLK = IOMUX_PAD(0x0428, 0x01C0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_TXC__SAI5_TX_DATA2 = IOMUX_PAD(0x0428, 0x01C0, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_TXC__GPIO4_IO25 = IOMUX_PAD(0x0428, 0x01C0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI2_TXD0__SAI2_TX_DATA0 = IOMUX_PAD(0x042C, 0x01C4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_TXD0__SAI5_TX_DATA3 = IOMUX_PAD(0x042C, 0x01C4, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_TXD0__GPIO4_IO26 = IOMUX_PAD(0x042C, 0x01C4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI2_MCLK__SAI2_MCLK = IOMUX_PAD(0x0430, 0x01C8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_MCLK__SAI5_MCLK = IOMUX_PAD(0x0430, 0x01C8, 1, 0x052C, 2, 0), + IMX8MQ_PAD_SAI2_MCLK__GPIO4_IO27 = IOMUX_PAD(0x0430, 0x01C8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI3_RXFS__SAI3_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_RXFS__GPT1_CAPTURE1 = IOMUX_PAD(0x0434, 0x01CC, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_RXFS__SAI5_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 2, 0x04E4, 2, 0), + IMX8MQ_PAD_SAI3_RXFS__GPIO4_IO28 = IOMUX_PAD(0x0434, 0x01CC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI3_RXC__SAI3_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_RXC__GPT1_CAPTURE2 = IOMUX_PAD(0x0438, 0x01D0, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_RXC__SAI5_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 2, 0x04D0, 2, 0), + IMX8MQ_PAD_SAI3_RXC__GPIO4_IO29 = IOMUX_PAD(0x0438, 0x01D0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI3_RXD__SAI3_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_RXD__GPT1_COMPARE1 = IOMUX_PAD(0x043C, 0x01D4, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_RXD__SAI5_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 2, 0x04D4, 2, 0), + IMX8MQ_PAD_SAI3_RXD__GPIO4_IO30 = IOMUX_PAD(0x043C, 0x01D4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI3_TXFS__SAI3_TX_SYNC = IOMUX_PAD(0x0440, 0x01D8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_TXFS__GPT1_CLK = IOMUX_PAD(0x0440, 0x01D8, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_TXFS__SAI5_RX_DATA1 = IOMUX_PAD(0x0440, 0x01D8, 2, 0x04D8, 2, 0), + IMX8MQ_PAD_SAI3_TXFS__GPIO4_IO31 = IOMUX_PAD(0x0440, 0x01D8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI3_TXC__SAI3_TX_BCLK = IOMUX_PAD(0x0444, 0x01DC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_TXC__GPT1_COMPARE2 = IOMUX_PAD(0x0444, 0x01DC, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_TXC__SAI5_RX_DATA2 = IOMUX_PAD(0x0444, 0x01DC, 2, 0x04DC, 2, 0), + IMX8MQ_PAD_SAI3_TXC__GPIO5_IO0 = IOMUX_PAD(0x0444, 0x01DC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI3_TXD__SAI3_TX_DATA0 = IOMUX_PAD(0x0448, 0x01E0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_TXD__GPT1_COMPARE3 = IOMUX_PAD(0x0448, 0x01E0, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_TXD__SAI5_RX_DATA3 = IOMUX_PAD(0x0448, 0x01E0, 2, 0x04E0, 2, 0), + IMX8MQ_PAD_SAI3_TXD__GPIO5_IO1 = IOMUX_PAD(0x0448, 0x01E0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI3_MCLK__SAI3_MCLK = IOMUX_PAD(0x044C, 0x01E4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_MCLK__PWM4_OUT = IOMUX_PAD(0x044C, 0x01E4, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_MCLK__SAI5_MCLK = IOMUX_PAD(0x044C, 0x01E4, 2, 0x052C, 3, 0), + IMX8MQ_PAD_SAI3_MCLK__GPIO5_IO2 = IOMUX_PAD(0x044C, 0x01E4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SPDIF_TX__SPDIF1_OUT = IOMUX_PAD(0x0450, 0x01E8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SPDIF_TX__PWM3_OUT = IOMUX_PAD(0x0450, 0x01E8, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SPDIF_TX__GPIO5_IO3 = IOMUX_PAD(0x0450, 0x01E8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SPDIF_RX__SPDIF1_IN = IOMUX_PAD(0x0454, 0x01EC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SPDIF_RX__PWM2_OUT = IOMUX_PAD(0x0454, 0x01EC, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SPDIF_RX__GPIO5_IO4 = IOMUX_PAD(0x0454, 0x01EC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SPDIF_EXT_CLK__SPDIF1_EXT_CLK = IOMUX_PAD(0x0458, 0x01F0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SPDIF_EXT_CLK__PWM1_OUT = IOMUX_PAD(0x0458, 0x01F0, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SPDIF_EXT_CLK__GPIO5_IO5 = IOMUX_PAD(0x0458, 0x01F0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ECSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x045C, 0x01F4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ECSPI1_SCLK__UART3_RX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0504, 0, 0), + IMX8MQ_PAD_ECSPI1_SCLK__GPIO5_IO6 = IOMUX_PAD(0x045C, 0x01F4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ECSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x0460, 0x01F8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ECSPI1_MOSI__UART3_TX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0504, 1, 0), + IMX8MQ_PAD_ECSPI1_MOSI__GPIO5_IO7 = IOMUX_PAD(0x0460, 0x01F8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ECSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x0464, 0x01FC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ECSPI1_MISO__UART3_CTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0500, 0, 0), + IMX8MQ_PAD_ECSPI1_MISO__GPIO5_IO8 = IOMUX_PAD(0x0464, 0x01FC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ECSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x0468, 0x0200, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ECSPI1_SS0__UART3_RTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0500, 1, 0), + IMX8MQ_PAD_ECSPI1_SS0__GPIO5_IO9 = IOMUX_PAD(0x0468, 0x0200, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ECSPI2_SCLK__ECSPI2_SCLK = IOMUX_PAD(0x046C, 0x0204, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ECSPI2_SCLK__UART4_RX = IOMUX_PAD(0x046C, 0x0204, 1, 0x050C, 0, 0), + IMX8MQ_PAD_ECSPI2_SCLK__GPIO5_IO10 = IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ECSPI2_MOSI__ECSPI2_MOSI = IOMUX_PAD(0x0470, 0x0208, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ECSPI2_MOSI__UART4_TX = IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0), + IMX8MQ_PAD_ECSPI2_MOSI__GPIO5_IO11 = IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ECSPI2_MISO__ECSPI2_MISO = IOMUX_PAD(0x0474, 0x020C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ECSPI2_MISO__UART4_CTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0508, 0, 0), + IMX8MQ_PAD_ECSPI2_MISO__GPIO5_IO12 = IOMUX_PAD(0x0474, 0x020C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ECSPI2_SS0__ECSPI2_SS0 = IOMUX_PAD(0x0478, 0x0210, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ECSPI2_SS0__UART4_RTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0508, 1, 0), + IMX8MQ_PAD_ECSPI2_SS0__GPIO5_IO13 = IOMUX_PAD(0x0478, 0x0210, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x047C, 0x0214, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), + IMX8MQ_PAD_I2C1_SCL__ENET_MDC = IOMUX_PAD(0x047C, 0x0214, 1, 0x0000, 0, 0), + IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 = IOMUX_PAD(0x047C, 0x0214, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0480, 0x0218, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), + IMX8MQ_PAD_I2C1_SDA__ENET_MDIO = IOMUX_PAD(0x0480, 0x0218, 1, 0x04C0, 2, 0), + IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 = IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_I2C2_SCL__I2C2_SCL = IOMUX_PAD(0x0484, 0x021C, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), + IMX8MQ_PAD_I2C2_SCL__ENET_1588_EVENT1_IN = IOMUX_PAD(0x0484, 0x021C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_I2C2_SCL__GPIO5_IO16 = IOMUX_PAD(0x0484, 0x021C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_I2C2_SDA__I2C2_SDA = IOMUX_PAD(0x0488, 0x0220, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), + IMX8MQ_PAD_I2C2_SDA__ENET_1588_EVENT1_OUT = IOMUX_PAD(0x0488, 0x0220, 1, 0x0000, 0, 0), + IMX8MQ_PAD_I2C2_SDA__GPIO5_IO17 = IOMUX_PAD(0x0488, 0x0220, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_I2C3_SCL__I2C3_SCL = IOMUX_PAD(0x048C, 0x0224, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), + IMX8MQ_PAD_I2C3_SCL__PWM4_OUT = IOMUX_PAD(0x048C, 0x0224, 1, 0x0000, 0, 0), + IMX8MQ_PAD_I2C3_SCL__GPT2_CLK = IOMUX_PAD(0x048C, 0x0224, 2, 0x0000, 0, 0), + IMX8MQ_PAD_I2C3_SCL__GPIO5_IO18 = IOMUX_PAD(0x048C, 0x0224, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_I2C3_SDA__I2C3_SDA = IOMUX_PAD(0x0490, 0x0228, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), + IMX8MQ_PAD_I2C3_SDA__PWM3_OUT = IOMUX_PAD(0x0490, 0x0228, 1, 0x0000, 0, 0), + IMX8MQ_PAD_I2C3_SDA__GPT3_CLK = IOMUX_PAD(0x0490, 0x0228, 2, 0x0000, 0, 0), + IMX8MQ_PAD_I2C3_SDA__GPIO5_IO19 = IOMUX_PAD(0x0490, 0x0228, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_I2C4_SCL__I2C4_SCL = IOMUX_PAD(0x0494, 0x022C, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), + IMX8MQ_PAD_I2C4_SCL__PWM2_OUT = IOMUX_PAD(0x0494, 0x022C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_I2C4_SCL__PCIE1_CLKREQ_B = IOMUX_PAD(0x0494, 0x022C, 2, 0x0524, 0, 0), + IMX8MQ_PAD_I2C4_SCL__GPIO5_IO20 = IOMUX_PAD(0x0494, 0x022C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_I2C4_SDA__I2C4_SDA = IOMUX_PAD(0x0498, 0x0230, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), + IMX8MQ_PAD_I2C4_SDA__PWM1_OUT = IOMUX_PAD(0x0498, 0x0230, 1, 0x0000, 0, 0), + IMX8MQ_PAD_I2C4_SDA__PCIE2_CLKREQ_B = IOMUX_PAD(0x0498, 0x0230, 2, 0x0528, 0, 0), + IMX8MQ_PAD_I2C4_SDA__GPIO5_IO21 = IOMUX_PAD(0x0498, 0x0230, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_UART1_RXD__UART1_RX = IOMUX_PAD(0x049C, 0x0234, 0, 0x04F4, 0, 0), + IMX8MQ_PAD_UART1_RXD__ECSPI3_SCLK = IOMUX_PAD(0x049C, 0x0234, 1, 0x0000, 0, 0), + IMX8MQ_PAD_UART1_RXD__GPIO5_IO22 = IOMUX_PAD(0x049C, 0x0234, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_UART1_TXD__UART1_TX = IOMUX_PAD(0x04A0, 0x0238, 0, 0x0000, 0, 0), + IMX8MQ_PAD_UART1_TXD__ECSPI3_MOSI = IOMUX_PAD(0x04A0, 0x0238, 1, 0x0000, 0, 0), + IMX8MQ_PAD_UART1_TXD__GPIO5_IO23 = IOMUX_PAD(0x04A0, 0x0238, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_UART2_RXD__UART2_RX = IOMUX_PAD(0x04A4, 0x023C, 0, 0x04FC, 0, 0), + IMX8MQ_PAD_UART2_RXD__ECSPI3_MISO = IOMUX_PAD(0x04A4, 0x023C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_UART2_RXD__GPIO5_IO24 = IOMUX_PAD(0x04A4, 0x023C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_UART2_TXD__UART2_TX = IOMUX_PAD(0x04A8, 0x0240, 0, 0x0000, 0, 0), + IMX8MQ_PAD_UART2_TXD__ECSPI3_SS0 = IOMUX_PAD(0x04A8, 0x0240, 1, 0x0000, 0, 0), + IMX8MQ_PAD_UART2_TXD__GPIO5_IO25 = IOMUX_PAD(0x04A8, 0x0240, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_UART3_RXD__UART3_RX = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0504, 2, 0), + IMX8MQ_PAD_UART3_RXD__UART1_CTS_B = IOMUX_PAD(0x04AC, 0x0244, 1, 0x04F0, 0, 0), + IMX8MQ_PAD_UART3_RXD__GPIO5_IO26 = IOMUX_PAD(0x04AC, 0x0244, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_UART3_TXD__UART3_TX = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0000, 0, 0), + IMX8MQ_PAD_UART3_TXD__UART1_RTS_B = IOMUX_PAD(0x04B0, 0x0248, 1, 0x04F0, 1, 0), + IMX8MQ_PAD_UART3_TXD__GPIO5_IO27 = IOMUX_PAD(0x04B0, 0x0248, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_UART4_RXD__UART4_RX = IOMUX_PAD(0x04B4, 0x024C, 0, 0x050C, 2, 0), + IMX8MQ_PAD_UART4_RXD__UART2_CTS_B = IOMUX_PAD(0x04B4, 0x024C, 1, 0x04F8, 0, 0), + IMX8MQ_PAD_UART4_RXD__PCIE1_CLKREQ_B = IOMUX_PAD(0x04B4, 0x024C, 2, 0x0524, 1, 0), + IMX8MQ_PAD_UART4_RXD__GPIO5_IO28 = IOMUX_PAD(0x04B4, 0x024C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_UART4_TXD__UART4_TX = IOMUX_PAD(0x04B8, 0x0250, 0, 0x0000, 0, 0), + IMX8MQ_PAD_UART4_TXD__UART2_RTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x04F8, 1, 0), + IMX8MQ_PAD_UART4_TXD__PCIE2_CLKREQ_B = IOMUX_PAD(0x04B8, 0x0250, 2, 0x0528, 1, 0), + IMX8MQ_PAD_UART4_TXD__GPIO5_IO29 = IOMUX_PAD(0x04B8, 0x0250, 5, 0x0000, 0, 0), +}; + +#endif -- cgit v1.2.3 From e2ec86ff52b1f7f7a9084b3412196ca4f06b9d5f Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 17 Feb 2020 08:34:11 +0100 Subject: ARM: i.MX8M: Add base addresses common to i.MX8M This adds defines for the base addresses common to all currently existing i.MX8M SoCs. Only the base addresses that are known to be needed for the early SoC code are added. With this we can reuse the early code for all variants without guessing that the base addresses are the same for the other variants. Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/include/mach/imx8m-regs.h | 37 ++++++++++++++++++++++++++++ arch/arm/mach-imx/include/mach/imx8mq-regs.h | 2 ++ 2 files changed, 39 insertions(+) create mode 100644 arch/arm/mach-imx/include/mach/imx8m-regs.h (limited to 'arch/arm/mach-imx/include') diff --git a/arch/arm/mach-imx/include/mach/imx8m-regs.h b/arch/arm/mach-imx/include/mach/imx8m-regs.h new file mode 100644 index 0000000000..e5f466c291 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/imx8m-regs.h @@ -0,0 +1,37 @@ +#ifndef __MACH_IMX8M_REGS_H +#define __MACH_IMX8M_REGS_H + +#define MX8M_GPIO1_BASE_ADDR 0X30200000 +#define MX8M_GPIO2_BASE_ADDR 0x30210000 +#define MX8M_GPIO3_BASE_ADDR 0x30220000 +#define MX8M_GPIO4_BASE_ADDR 0x30230000 +#define MX8M_GPIO5_BASE_ADDR 0x30240000 +#define MX8M_WDOG1_BASE_ADDR 0x30280000 +#define MX8M_WDOG2_BASE_ADDR 0x30290000 +#define MX8M_WDOG3_BASE_ADDR 0x302A0000 +#define MX8M_IOMUXC_BASE_ADDR 0x30330000 +#define MX8M_IOMUXC_GPR_BASE_ADDR 0x30340000 +#define MX8M_OCOTP_BASE_ADDR 0x30350000 +#define MX8M_ANATOP_BASE_ADDR 0x30360000 +#define MX8M_CCM_BASE_ADDR 0x30380000 +#define MX8M_SRC_BASE_ADDR 0x30390000 +#define MX8M_SRC_DDRC_RCR_ADDR 0x30391000 +#define MX8M_GPC_BASE_ADDR 0x303A0000 +#define MX8M_SYSCNT_CTRL_BASE_ADDR 0x306C0000 +#define MX8M_UART1_BASE_ADDR 0x30860000 +#define MX8M_UART3_BASE_ADDR 0x30880000 +#define MX8M_UART2_BASE_ADDR 0x30890000 +#define MX8M_I2C1_BASE_ADDR 0x30A20000 +#define MX8M_I2C2_BASE_ADDR 0x30A30000 +#define MX8M_I2C3_BASE_ADDR 0x30A40000 +#define MX8M_I2C4_BASE_ADDR 0x30A50000 +#define MX8M_UART4_BASE_ADDR 0x30A60000 +#define MX8M_USDHC1_BASE_ADDR 0x30B40000 +#define MX8M_USDHC2_BASE_ADDR 0x30B50000 +#define MX8M_DDRC_PHY_BASE_ADDR 0x3c000000 +#define MX8M_DDRC_DDR_SS_GPR0 (MX8M_DDRC_PHY_BASE_ADDR + 0x01000000) +#define MX8M_DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000)) +#define MX8M_DDRC_CTL_BASE_ADDR MX8M_DDRC_IPS_BASE_ADDR(0) +#define MX8M_DDR_CSD1_BASE_ADDR 0x40000000 + +#endif /* __MACH_IMX8M_REGS_H */ diff --git a/arch/arm/mach-imx/include/mach/imx8mq-regs.h b/arch/arm/mach-imx/include/mach/imx8mq-regs.h index 51936f526e..2f6488af33 100644 --- a/arch/arm/mach-imx/include/mach/imx8mq-regs.h +++ b/arch/arm/mach-imx/include/mach/imx8mq-regs.h @@ -1,6 +1,8 @@ #ifndef __MACH_IMX8MQ_REGS_H #define __MACH_IMX8MQ_REGS_H +#include + #define MX8MQ_M4_BOOTROM_BASE_ADDR 0x007E0000 #define MX8MQ_SAI1_BASE_ADDR 0x30010000 -- cgit v1.2.3 From d86ac7209083aa390c02b635aba11aaffcfeff9a Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 13 Feb 2020 12:23:21 +0100 Subject: ARM: i.MX8M: add and use imx8mq_setup_pad() We already have a mx8_setup_pad() function for early iomux setup, but it is unused. Add a i.MX8MQ specific wrapper for the function which passes the correct base address to mx8_setup_pad(). Let the boards use this function. While at it rename mx8_setup_pad() to imx8_setup_pad() which is more consistent to other i.MX specific functions. Signed-off-by: Sascha Hauer --- arch/arm/boards/nxp-imx8mq-evk/lowlevel.c | 3 +-- arch/arm/boards/phytec-som-imx8mq/lowlevel.c | 3 +-- arch/arm/boards/zii-imx8mq-dev/lowlevel.c | 3 +-- arch/arm/mach-imx/include/mach/iomux-mx8mq.h | 8 ++++++++ 4 files changed, 11 insertions(+), 6 deletions(-) (limited to 'arch/arm/mach-imx/include') diff --git a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c index 4443c7d3b8..68464e330d 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c +++ b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c @@ -25,7 +25,6 @@ extern char __dtb_imx8mq_evk_start[]; static void setup_uart(void) { - void __iomem *iomux = IOMEM(MX8MQ_IOMUXC_BASE_ADDR); void __iomem *ccm = IOMEM(MX8MQ_CCM_BASE_ADDR); writel(CCM_CCGR_SETTINGn_NEEDED(0), @@ -35,7 +34,7 @@ static void setup_uart(void) writel(CCM_CCGR_SETTINGn_NEEDED(0), ccm + CCM_CCGRn_SET(CCM_CCGR_UART1)); - imx_setup_pad(iomux, IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL); + imx8mq_setup_pad(IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL); imx8_uart_setup_ll(); diff --git a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c index e327b8cdfb..4ce5c4ecde 100644 --- a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c +++ b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c @@ -28,7 +28,6 @@ extern char __dtb_imx8mq_phytec_phycore_som_start[]; static void setup_uart(void) { - void __iomem *iomux = IOMEM(MX8MQ_IOMUXC_BASE_ADDR); void __iomem *ccm = IOMEM(MX8MQ_CCM_BASE_ADDR); writel(CCM_CCGR_SETTINGn_NEEDED(0), @@ -38,7 +37,7 @@ static void setup_uart(void) writel(CCM_CCGR_SETTINGn_NEEDED(0), ccm + CCM_CCGRn_SET(CCM_CCGR_UART1)); - imx_setup_pad(iomux, IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL); + imx8mq_setup_pad(IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL); imx8_uart_setup_ll(); diff --git a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c index a328699142..63f87eede0 100644 --- a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c +++ b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c @@ -27,7 +27,6 @@ static void setup_uart(void) { - void __iomem *iomux = IOMEM(MX8MQ_IOMUXC_BASE_ADDR); void __iomem *ccm = IOMEM(MX8MQ_CCM_BASE_ADDR); writel(CCM_CCGR_SETTINGn_NEEDED(0), @@ -37,7 +36,7 @@ static void setup_uart(void) writel(CCM_CCGR_SETTINGn_NEEDED(0), ccm + CCM_CCGRn_SET(CCM_CCGR_UART1)); - imx_setup_pad(iomux, IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL); + imx8mq_setup_pad(IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL); imx8_uart_setup_ll(); diff --git a/arch/arm/mach-imx/include/mach/iomux-mx8mq.h b/arch/arm/mach-imx/include/mach/iomux-mx8mq.h index 5c94731ea7..d397e975c0 100644 --- a/arch/arm/mach-imx/include/mach/iomux-mx8mq.h +++ b/arch/arm/mach-imx/include/mach/iomux-mx8mq.h @@ -9,6 +9,7 @@ #include #include +#include enum { IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0 = IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0), @@ -622,4 +623,11 @@ enum { IMX8MQ_PAD_UART4_TXD__GPIO5_IO29 = IOMUX_PAD(0x04B8, 0x0250, 5, 0x0000, 0, 0), }; +static inline void imx8mq_setup_pad(iomux_v3_cfg_t pad) +{ + void __iomem *iomux = IOMEM(MX8MQ_IOMUXC_BASE_ADDR); + + imx8m_setup_pad(iomux, pad); +} + #endif -- cgit v1.2.3 From 666d8b6c74f4ef641bd8fc8c24d184ccb69840df Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 13 Feb 2020 12:28:46 +0100 Subject: ARM: i.MX: Drop iomux argument from mx7_setup_pad() The name mx7_setup_pad already implies the SoC where it runs on, so we do not have to pass the iomux base address but can hardcode it in the function. While at it rename it to imx7_setup_pad() which is more consistent to other i.MX specific functions. Signed-off-by: Sascha Hauer --- arch/arm/boards/freescale-mx7-sabresd/lowlevel.c | 3 +-- arch/arm/boards/zii-imx7d-dev/lowlevel.c | 3 +-- arch/arm/mach-imx/include/mach/iomux-mx7.h | 4 +++- 3 files changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm/mach-imx/include') diff --git a/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c b/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c index f718ea73b3..edd965e4ec 100644 --- a/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c +++ b/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c @@ -15,7 +15,6 @@ extern char __dtb_imx7d_sdb_start[]; static inline void setup_uart(void) { - void __iomem *iomux = IOMEM(MX7_IOMUXC_BASE_ADDR); void __iomem *ccm = IOMEM(MX7_CCM_BASE_ADDR); writel(CCM_CCGR_SETTINGn_NEEDED(0), @@ -25,7 +24,7 @@ static inline void setup_uart(void) writel(CCM_CCGR_SETTINGn_NEEDED(0), ccm + CCM_CCGRn_SET(CCM_CCGR_UART1)); - mx7_setup_pad(iomux, MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX); + imx7_setup_pad(MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX); imx7_uart_setup_ll(); diff --git a/arch/arm/boards/zii-imx7d-dev/lowlevel.c b/arch/arm/boards/zii-imx7d-dev/lowlevel.c index 3bacfd0c7d..83d01446b9 100644 --- a/arch/arm/boards/zii-imx7d-dev/lowlevel.c +++ b/arch/arm/boards/zii-imx7d-dev/lowlevel.c @@ -23,7 +23,6 @@ extern char __dtb_z_imx7d_zii_rmu2_start[]; static inline void setup_uart(void) { - void __iomem *iomux = IOMEM(MX7_IOMUXC_BASE_ADDR); void __iomem *ccm = IOMEM(MX7_CCM_BASE_ADDR); writel(CCM_CCGR_SETTINGn_NEEDED(0), @@ -33,7 +32,7 @@ static inline void setup_uart(void) writel(CCM_CCGR_SETTINGn_NEEDED(0), ccm + CCM_CCGRn_SET(CCM_CCGR_UART2)); - mx7_setup_pad(iomux, MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX); + imx7_setup_pad(MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX); imx7_uart_setup_ll(); diff --git a/arch/arm/mach-imx/include/mach/iomux-mx7.h b/arch/arm/mach-imx/include/mach/iomux-mx7.h index 2667dc3eb3..def9cf4d44 100644 --- a/arch/arm/mach-imx/include/mach/iomux-mx7.h +++ b/arch/arm/mach-imx/include/mach/iomux-mx7.h @@ -8,6 +8,7 @@ #define __MACH_IOMUX_IMX7D_H__ #include +#include enum { MX7D_PAD_GPIO1_IO00__GPIO1_IO0 = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), @@ -1306,8 +1307,9 @@ enum { MX7D_PAD_ENET1_COL__CSU_INT_DEB = IOMUX_PAD(0x04D8, 0x0268, 7, 0x0000, 0, 0), }; -static inline void mx7_setup_pad(void __iomem *iomux, iomux_v3_cfg_t pad) +static inline void imx7_setup_pad(iomux_v3_cfg_t pad) { + void __iomem *iomux = IOMEM(MX7_IOMUXC_BASE_ADDR); unsigned int flags = 0; uint32_t mode = IOMUX_MODE(pad); -- cgit v1.2.3 From 40f6bd8cdd1914fd77de3b35933a2195b92c8d7f Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 7 Feb 2020 10:47:16 +0100 Subject: ARM: i.MX8M: Add iomux header for i.MX8MM This adds the iomux definitions for the i.MX8MM, taken from U-Boot 2020-rc1. Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/include/mach/iomux-mx8mm.h | 701 +++++++++++++++++++++++++++ 1 file changed, 701 insertions(+) create mode 100644 arch/arm/mach-imx/include/mach/iomux-mx8mm.h (limited to 'arch/arm/mach-imx/include') diff --git a/arch/arm/mach-imx/include/mach/iomux-mx8mm.h b/arch/arm/mach-imx/include/mach/iomux-mx8mm.h new file mode 100644 index 0000000000..f91671865d --- /dev/null +++ b/arch/arm/mach-imx/include/mach/iomux-mx8mm.h @@ -0,0 +1,701 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018-2019 NXP + */ + +#ifndef __ASM_ARCH_IMX8MM_PINS_H__ +#define __ASM_ARCH_IMX8MM_PINS_H__ + +#include +#include +#include + +enum { + IMX8MM_PAD_GPIO1_IO00_GPIO1_IO0 = IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT = IOMUX_PAD(0x0290, 0x0028, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO00_XTALOSC_REF_CLK_32K = IOMUX_PAD(0x0290, 0x0028, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO00_CCM_EXT_CLK1 = IOMUX_PAD(0x0290, 0x0028, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO01_GPIO1_IO1 = IOMUX_PAD(0x0294, 0x002C, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO01_PWM1_OUT = IOMUX_PAD(0x0294, 0x002C, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO01_XTALOSC_REF_CLK_24M = IOMUX_PAD(0x0294, 0x002C, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO01_CCM_EXT_CLK2 = IOMUX_PAD(0x0294, 0x002C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO02_GPIO1_IO2 = IOMUX_PAD(0x0298, 0x0030, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B = IOMUX_PAD(0x0298, 0x0030, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_ANY = IOMUX_PAD(0x0298, 0x0030, 5, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO03_GPIO1_IO3 = IOMUX_PAD(0x029C, 0x0034, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO03_USDHC1_VSELECT = IOMUX_PAD(0x029C, 0x0034, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO03_SDMA1_EXT_EVENT0 = IOMUX_PAD(0x029C, 0x0034, 5, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO04_GPIO1_IO4 = IOMUX_PAD(0x02A0, 0x0038, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO04_USDHC2_VSELECT = IOMUX_PAD(0x02A0, 0x0038, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO04_SDMA1_EXT_EVENT1 = IOMUX_PAD(0x02A0, 0x0038, 5, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO05_GPIO1_IO5 = IOMUX_PAD(0x02A4, 0x003C, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO05_ARM_PLATFORM_M4_NMI = IOMUX_PAD(0x02A4, 0x003C, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO05_CCM_PMIC_READY = IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0), + IMX8MM_PAD_GPIO1_IO05_SRC_INT_BOOT = IOMUX_PAD(0x02A4, 0x003C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO06_GPIO1_IO6 = IOMUX_PAD(0x02A8, 0x0040, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO06_ENET1_MDC = IOMUX_PAD(0x02A8, 0x0040, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO06_USDHC1_CD_B = IOMUX_PAD(0x02A8, 0x0040, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO06_CCM_EXT_CLK3 = IOMUX_PAD(0x02A8, 0x0040, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO07_GPIO1_IO7 = IOMUX_PAD(0x02AC, 0x0044, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO07_ENET1_MDIO = IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0), + IMX8MM_PAD_GPIO1_IO07_USDHC1_WP = IOMUX_PAD(0x02AC, 0x0044, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO07_CCM_EXT_CLK4 = IOMUX_PAD(0x02AC, 0x0044, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO08_GPIO1_IO8 = IOMUX_PAD(0x02B0, 0x0048, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO08_ENET1_1588_EVENT0_IN = IOMUX_PAD(0x02B0, 0x0048, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO08_USDHC2_RESET_B = IOMUX_PAD(0x02B0, 0x0048, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO08_CCM_WAIT = IOMUX_PAD(0x02B0, 0x0048, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO09_GPIO1_IO9 = IOMUX_PAD(0x02B4, 0x004C, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO09_ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x02B4, 0x004C, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO09_USDHC3_RESET_B = IOMUX_PAD(0x02B4, 0x004C, 4, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO09_SDMA2_EXT_EVENT0 = IOMUX_PAD(0x02B4, 0x004C, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO09_CCM_STOP = IOMUX_PAD(0x02B4, 0x004C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO10_GPIO1_IO10 = IOMUX_PAD(0x02B8, 0x0050, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO10_USB1_OTG_ID = IOMUX_PAD(0x02B8, 0x0050, 1, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO11_GPIO1_IO11 = IOMUX_PAD(0x02BC, 0x0054, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO11_USB2_OTG_ID = IOMUX_PAD(0x02BC, 0x0054, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO11_USDHC3_VSELECT = IOMUX_PAD(0x02BC, 0x0054, 4, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO11_CCM_PMIC_READY = IOMUX_PAD(0x02BC, 0x0054, 5, 0x04BC, 1, 0), + IMX8MM_PAD_GPIO1_IO11_CCM_OUT0 = IOMUX_PAD(0x02BC, 0x0054, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO12_GPIO1_IO12 = IOMUX_PAD(0x02C0, 0x0058, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO12_USB1_OTG_PWR = IOMUX_PAD(0x02C0, 0x0058, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO12_SDMA2_EXT_EVENT1 = IOMUX_PAD(0x02C0, 0x0058, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO12_CCM_OUT1 = IOMUX_PAD(0x02C0, 0x0058, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO13_GPIO1_IO13 = IOMUX_PAD(0x02C4, 0x005C, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO13_USB1_OTG_OC = IOMUX_PAD(0x02C4, 0x005C, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO13_PWM2_OUT = IOMUX_PAD(0x02C4, 0x005C, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO13_CCM_OUT2 = IOMUX_PAD(0x02C4, 0x005C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO14_GPIO1_IO14 = IOMUX_PAD(0x02C8, 0x0060, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO14_USB2_OTG_PWR = IOMUX_PAD(0x02C8, 0x0060, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO14_USDHC3_CD_B = IOMUX_PAD(0x02C8, 0x0060, 4, 0x0544, 2, 0), + IMX8MM_PAD_GPIO1_IO14_PWM3_OUT = IOMUX_PAD(0x02C8, 0x0060, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO14_CCM_CLKO1 = IOMUX_PAD(0x02C8, 0x0060, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO15_GPIO1_IO15 = IOMUX_PAD(0x02CC, 0x0064, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO15_USB2_OTG_OC = IOMUX_PAD(0x02CC, 0x0064, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO15_USDHC3_WP = IOMUX_PAD(0x02CC, 0x0064, 4, 0x0548, 2, 0), + IMX8MM_PAD_GPIO1_IO15_PWM4_OUT = IOMUX_PAD(0x02CC, 0x0064, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO15_CCM_CLKO2 = IOMUX_PAD(0x02CC, 0x0064, 6, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_MDC_ENET1_MDC = IOMUX_PAD(0x02D0, 0x0068, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_MDC_GPIO1_IO16 = IOMUX_PAD(0x02D0, 0x0068, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_MDIO_ENET1_MDIO = IOMUX_PAD(0x02D4, 0x006C, 0, 0x04C0, 1, 0), + IMX8MM_PAD_ENET_MDIO_GPIO1_IO17 = IOMUX_PAD(0x02D4, 0x006C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_TD3_ENET1_RGMII_TD3 = IOMUX_PAD(0x02D8, 0x0070, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TD3_GPIO1_IO18 = IOMUX_PAD(0x02D8, 0x0070, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_TD2_ENET1_RGMII_TD2 = IOMUX_PAD(0x02DC, 0x0074, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TD2_ENET1_TX_CLK = IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TD2_CCM_ENET_REF_CLK_ROOT = IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TD2_GPIO1_IO19 = IOMUX_PAD(0x02DC, 0x0074, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_TD1_ENET1_RGMII_TD1 = IOMUX_PAD(0x02E0, 0x0078, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TD1_GPIO1_IO20 = IOMUX_PAD(0x02E0, 0x0078, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_TD0_ENET1_RGMII_TD0 = IOMUX_PAD(0x02E4, 0x007C, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TD0_GPIO1_IO21 = IOMUX_PAD(0x02E4, 0x007C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_TX_CTL_ENET1_RGMII_TX_CTL = IOMUX_PAD(0x02E8, 0x0080, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TX_CTL_GPIO1_IO22 = IOMUX_PAD(0x02E8, 0x0080, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_TXC_ENET1_RGMII_TXC = IOMUX_PAD(0x02EC, 0x0084, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TXC_ENET1_TX_ER = IOMUX_PAD(0x02EC, 0x0084, 1, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TXC_GPIO1_IO23 = IOMUX_PAD(0x02EC, 0x0084, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_RX_CTL_ENET1_RGMII_RX_CTL = IOMUX_PAD(0x02F0, 0x0088, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RX_CTL_GPIO1_IO24 = IOMUX_PAD(0x02F0, 0x0088, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_RXC_ENET1_RGMII_RXC = IOMUX_PAD(0x02F4, 0x008C, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RXC_ENET1_RX_ER = IOMUX_PAD(0x02F4, 0x008C, 1, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RXC_GPIO1_IO25 = IOMUX_PAD(0x02F4, 0x008C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_RD0_ENET1_RGMII_RD0 = IOMUX_PAD(0x02F8, 0x0090, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RD0_GPIO1_IO26 = IOMUX_PAD(0x02F8, 0x0090, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_RD1_ENET1_RGMII_RD1 = IOMUX_PAD(0x02FC, 0x0094, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RD1_GPIO1_IO27 = IOMUX_PAD(0x02FC, 0x0094, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_RD2_ENET1_RGMII_RD2 = IOMUX_PAD(0x0300, 0x0098, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RD2_GPIO1_IO28 = IOMUX_PAD(0x0300, 0x0098, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_RD3_ENET1_RGMII_RD3 = IOMUX_PAD(0x0304, 0x009C, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RD3_GPIO1_IO29 = IOMUX_PAD(0x0304, 0x009C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_CLK_USDHC1_CLK = IOMUX_PAD(0x0308, 0x00A0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_CLK_GPIO2_IO0 = IOMUX_PAD(0x0308, 0x00A0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_CMD_USDHC1_CMD = IOMUX_PAD(0x030C, 0x00A4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_CMD_GPIO2_IO1 = IOMUX_PAD(0x030C, 0x00A4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA0_USDHC1_DATA0 = IOMUX_PAD(0x0310, 0x00A8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA0_GPIO2_IO2 = IOMUX_PAD(0x0310, 0x00A8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA1_USDHC1_DATA1 = IOMUX_PAD(0x0314, 0x00AC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA1_GPIO2_IO3 = IOMUX_PAD(0x0314, 0x00AC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA2_USDHC1_DATA2 = IOMUX_PAD(0x0318, 0x00B0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA2_GPIO2_IO4 = IOMUX_PAD(0x0318, 0x00B0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA3_USDHC1_DATA3 = IOMUX_PAD(0x031C, 0x00B4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA3_GPIO2_IO5 = IOMUX_PAD(0x031C, 0x00B4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA4_USDHC1_DATA4 = IOMUX_PAD(0x0320, 0x00B8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA4_GPIO2_IO6 = IOMUX_PAD(0x0320, 0x00B8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA5_USDHC1_DATA5 = IOMUX_PAD(0x0324, 0x00BC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA5_GPIO2_IO7 = IOMUX_PAD(0x0324, 0x00BC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA6_USDHC1_DATA6 = IOMUX_PAD(0x0328, 0x00C0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA6_GPIO2_IO8 = IOMUX_PAD(0x0328, 0x00C0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA7_USDHC1_DATA7 = IOMUX_PAD(0x032C, 0x00C4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA7_GPIO2_IO9 = IOMUX_PAD(0x032C, 0x00C4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_RESET_B_USDHC1_RESET_B = IOMUX_PAD(0x0330, 0x00C8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_RESET_B_GPIO2_IO10 = IOMUX_PAD(0x0330, 0x00C8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_STROBE_USDHC1_STROBE = IOMUX_PAD(0x0334, 0x00CC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_STROBE_GPIO2_IO11 = IOMUX_PAD(0x0334, 0x00CC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_CD_B_USDHC2_CD_B = IOMUX_PAD(0x0338, 0x00D0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_CD_B_GPIO2_IO12 = IOMUX_PAD(0x0338, 0x00D0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_CLK_USDHC2_CLK = IOMUX_PAD(0x033C, 0x00D4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_CLK_GPIO2_IO13 = IOMUX_PAD(0x033C, 0x00D4, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_CLK_CCM_OBSERVE0 = IOMUX_PAD(0x033C, 0x00D4, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_CMD_USDHC2_CMD = IOMUX_PAD(0x0340, 0x00D8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_CMD_GPIO2_IO14 = IOMUX_PAD(0x0340, 0x00D8, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_CMD_CCM_OBSERVE1 = IOMUX_PAD(0x0340, 0x00D8, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 = IOMUX_PAD(0x0344, 0x00DC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA0_GPIO2_IO15 = IOMUX_PAD(0x0344, 0x00DC, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA0_CCM_OBSERVE2 = IOMUX_PAD(0x0344, 0x00DC, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 = IOMUX_PAD(0x0348, 0x00E0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA1_GPIO2_IO16 = IOMUX_PAD(0x0348, 0x00E0, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA1_CCM_WAIT = IOMUX_PAD(0x0348, 0x00E0, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 = IOMUX_PAD(0x034C, 0x00E4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA2_GPIO2_IO17 = IOMUX_PAD(0x034C, 0x00E4, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA2_CCM_STOP = IOMUX_PAD(0x034C, 0x00E4, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 = IOMUX_PAD(0x0350, 0x00E8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA3_GPIO2_IO18 = IOMUX_PAD(0x0350, 0x00E8, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA3_SRC_EARLY_RESET = IOMUX_PAD(0x0350, 0x00E8, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_RESET_B_USDHC2_RESET_B = IOMUX_PAD(0x0354, 0x00EC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 = IOMUX_PAD(0x0354, 0x00EC, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_RESET_B_SRC_SYSTEM_RESET = IOMUX_PAD(0x0354, 0x00EC, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_WP_USDHC2_WP = IOMUX_PAD(0x0358, 0x00F0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_WP_GPIO2_IO20 = IOMUX_PAD(0x0358, 0x00F0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_ALE_RAWNAND_ALE = IOMUX_PAD(0x035C, 0x00F4, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_ALE_QSPI_A_SCLK = IOMUX_PAD(0x035C, 0x00F4, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_ALE_GPIO3_IO0 = IOMUX_PAD(0x035C, 0x00F4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_CE0_B_RAWNAND_CE0_B = IOMUX_PAD(0x0360, 0x00F8, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE0_B_QSPI_A_SS0_B = IOMUX_PAD(0x0360, 0x00F8, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE0_B_GPIO3_IO1 = IOMUX_PAD(0x0360, 0x00F8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_CE1_B_RAWNAND_CE1_B = IOMUX_PAD(0x0364, 0x00FC, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE1_B_QSPI_A_SS1_B = IOMUX_PAD(0x0364, 0x00FC, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE1_B_USDHC3_STROBE = IOMUX_PAD(0x0364, 0x00FC, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE1_B_GPIO3_IO2 = IOMUX_PAD(0x0364, 0x00FC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_CE2_B_RAWNAND_CE2_B = IOMUX_PAD(0x0368, 0x0100, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE2_B_QSPI_B_SS0_B = IOMUX_PAD(0x0368, 0x0100, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 = IOMUX_PAD(0x0368, 0x0100, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE2_B_GPIO3_IO3 = IOMUX_PAD(0x0368, 0x0100, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_CE3_B_RAWNAND_CE3_B = IOMUX_PAD(0x036C, 0x0104, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE3_B_QSPI_B_SS1_B = IOMUX_PAD(0x036C, 0x0104, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 = IOMUX_PAD(0x036C, 0x0104, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE3_B_GPIO3_IO4 = IOMUX_PAD(0x036C, 0x0104, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_CLE_RAWNAND_CLE = IOMUX_PAD(0x0370, 0x0108, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CLE_QSPI_B_SCLK = IOMUX_PAD(0x0370, 0x0108, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 = IOMUX_PAD(0x0370, 0x0108, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CLE_GPIO3_IO5 = IOMUX_PAD(0x0370, 0x0108, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA00_RAWNAND_DATA00 = IOMUX_PAD(0x0374, 0x010C, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA00_QSPI_A_DATA0 = IOMUX_PAD(0x0374, 0x010C, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA00_GPIO3_IO6 = IOMUX_PAD(0x0374, 0x010C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA01_RAWNAND_DATA01 = IOMUX_PAD(0x0378, 0x0110, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA01_QSPI_A_DATA1 = IOMUX_PAD(0x0378, 0x0110, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA01_GPIO3_IO7 = IOMUX_PAD(0x0378, 0x0110, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA02_RAWNAND_DATA02 = IOMUX_PAD(0x037C, 0x0114, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA02_QSPI_A_DATA2 = IOMUX_PAD(0x037C, 0x0114, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA02_USDHC3_CD_B = IOMUX_PAD(0x037C, 0x0114, 2, 0x0544, 0, 0), + IMX8MM_PAD_NAND_DATA02_GPIO3_IO8 = IOMUX_PAD(0x037C, 0x0114, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA03_RAWNAND_DATA03 = IOMUX_PAD(0x0380, 0x0118, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA03_QSPI_A_DATA3 = IOMUX_PAD(0x0380, 0x0118, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA03_USDHC3_WP = IOMUX_PAD(0x0380, 0x0118, 2, 0x0548, 0, 0), + IMX8MM_PAD_NAND_DATA03_GPIO3_IO9 = IOMUX_PAD(0x0380, 0x0118, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA04_RAWNAND_DATA04 = IOMUX_PAD(0x0384, 0x011C, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA04_QSPI_B_DATA0 = IOMUX_PAD(0x0384, 0x011C, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 = IOMUX_PAD(0x0384, 0x011C, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA04_GPIO3_IO10 = IOMUX_PAD(0x0384, 0x011C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA05_RAWNAND_DATA05 = IOMUX_PAD(0x0388, 0x0120, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA05_QSPI_B_DATA1 = IOMUX_PAD(0x0388, 0x0120, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 = IOMUX_PAD(0x0388, 0x0120, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA05_GPIO3_IO11 = IOMUX_PAD(0x0388, 0x0120, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA06_RAWNAND_DATA06 = IOMUX_PAD(0x038C, 0x0124, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA06_QSPI_B_DATA2 = IOMUX_PAD(0x038C, 0x0124, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 = IOMUX_PAD(0x038C, 0x0124, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA06_GPIO3_IO12 = IOMUX_PAD(0x038C, 0x0124, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA07_RAWNAND_DATA07 = IOMUX_PAD(0x0390, 0x0128, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA07_QSPI_B_DATA3 = IOMUX_PAD(0x0390, 0x0128, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 = IOMUX_PAD(0x0390, 0x0128, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA07_GPIO3_IO13 = IOMUX_PAD(0x0390, 0x0128, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DQS_RAWNAND_DQS = IOMUX_PAD(0x0394, 0x012C, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DQS_QSPI_A_DQS = IOMUX_PAD(0x0394, 0x012C, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DQS_GPIO3_IO14 = IOMUX_PAD(0x0394, 0x012C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_RE_B_RAWNAND_RE_B = IOMUX_PAD(0x0398, 0x0130, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_RE_B_QSPI_B_DQS = IOMUX_PAD(0x0398, 0x0130, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 = IOMUX_PAD(0x0398, 0x0130, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_RE_B_GPIO3_IO15 = IOMUX_PAD(0x0398, 0x0130, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_READY_B_RAWNAND_READY_B = IOMUX_PAD(0x039C, 0x0134, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_READY_B_USDHC3_RESET_B = IOMUX_PAD(0x039C, 0x0134, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_READY_B_GPIO3_IO16 = IOMUX_PAD(0x039C, 0x0134, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_WE_B_RAWNAND_WE_B = IOMUX_PAD(0x03A0, 0x0138, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_WE_B_USDHC3_CLK = IOMUX_PAD(0x03A0, 0x0138, 2 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + IMX8MM_PAD_NAND_WE_B_GPIO3_IO17 = IOMUX_PAD(0x03A0, 0x0138, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_WP_B_RAWNAND_WP_B = IOMUX_PAD(0x03A4, 0x013C, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_WP_B_USDHC3_CMD = IOMUX_PAD(0x03A4, 0x013C, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_WP_B_GPIO3_IO18 = IOMUX_PAD(0x03A4, 0x013C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_RXFS_SAI5_RX_SYNC = IOMUX_PAD(0x03A8, 0x0140, 0, 0x04E4, 0, 0), + IMX8MM_PAD_SAI5_RXFS_SAI1_TX_DATA0 = IOMUX_PAD(0x03A8, 0x0140, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXFS_GPIO3_IO19 = IOMUX_PAD(0x03A8, 0x0140, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_RXC_SAI5_RX_BCLK = IOMUX_PAD(0x03AC, 0x0144, 0, 0x04D0, 0, 0), + IMX8MM_PAD_SAI5_RXC_SAI1_TX_DATA1 = IOMUX_PAD(0x03AC, 0x0144, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXC_PDM_CLK = IOMUX_PAD(0x03AC, 0x0144, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXC_GPIO3_IO20 = IOMUX_PAD(0x03AC, 0x0144, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_RXD0_SAI5_RX_DATA0 = IOMUX_PAD(0x03B0, 0x0148, 0, 0x04D4, 0, 0), + IMX8MM_PAD_SAI5_RXD0_SAI1_TX_DATA2 = IOMUX_PAD(0x03B0, 0x0148, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXD0_PDM_BIT_STREAM0 = IOMUX_PAD(0x03B0, 0x0148, 4, 0x0534, 0, 0), + IMX8MM_PAD_SAI5_RXD0_GPIO3_IO21 = IOMUX_PAD(0x03B0, 0x0148, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_RXD1_SAI5_RX_DATA1 = IOMUX_PAD(0x03B4, 0x014C, 0, 0x04D8, 0, 0), + IMX8MM_PAD_SAI5_RXD1_SAI1_TX_DATA3 = IOMUX_PAD(0x03B4, 0x014C, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXD1_SAI1_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 2, 0x04CC, 0, 0), + IMX8MM_PAD_SAI5_RXD1_SAI5_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 3, 0x04EC, 0, 0), + IMX8MM_PAD_SAI5_RXD1_PDM_BIT_STREAM1 = IOMUX_PAD(0x03B4, 0x014C, 4, 0x0538, 0, 0), + IMX8MM_PAD_SAI5_RXD1_GPIO3_IO22 = IOMUX_PAD(0x03B4, 0x014C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_RXD2_SAI5_RX_DATA2 = IOMUX_PAD(0x03B8, 0x0150, 0, 0x04DC, 0, 0), + IMX8MM_PAD_SAI5_RXD2_SAI1_TX_DATA4 = IOMUX_PAD(0x03B8, 0x0150, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXD2_SAI1_TX_SYNC = IOMUX_PAD(0x03B8, 0x0150, 2, 0x04CC, 1, 0), + IMX8MM_PAD_SAI5_RXD2_SAI5_TX_BCLK = IOMUX_PAD(0x03B8, 0x0150, 3, 0x04E8, 0, 0), + IMX8MM_PAD_SAI5_RXD2_PDM_BIT_STREAM2 = IOMUX_PAD(0x03B8, 0x0150, 4, 0x053C, 0, 0), + IMX8MM_PAD_SAI5_RXD2_GPIO3_IO23 = IOMUX_PAD(0x03B8, 0x0150, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_RXD3_SAI5_RX_DATA3 = IOMUX_PAD(0x03BC, 0x0154, 0, 0x04E0, 0, 0), + IMX8MM_PAD_SAI5_RXD3_SAI1_TX_DATA5 = IOMUX_PAD(0x03BC, 0x0154, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXD3_SAI1_TX_SYNC = IOMUX_PAD(0x03BC, 0x0154, 2, 0x04CC, 2, 0), + IMX8MM_PAD_SAI5_RXD3_SAI5_TX_DATA0 = IOMUX_PAD(0x03BC, 0x0154, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXD3_PDM_BIT_STREAM3 = IOMUX_PAD(0x03BC, 0x0154, 4, 0x0540, 0, 0), + IMX8MM_PAD_SAI5_RXD3_GPIO3_IO24 = IOMUX_PAD(0x03BC, 0x0154, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_MCLK_SAI5_MCLK = IOMUX_PAD(0x03C0, 0x0158, 0, 0x052C, 0, 0), + IMX8MM_PAD_SAI5_MCLK_SAI1_TX_BCLK = IOMUX_PAD(0x03C0, 0x0158, 1, 0x04C8, 0, 0), + IMX8MM_PAD_SAI5_MCLK_GPIO3_IO25 = IOMUX_PAD(0x03C0, 0x0158, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_MCLK_SRC_TESTER_ACK = IOMUX_PAD(0x03C0, 0x0158, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXFS_SAI1_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 0, 0x04C4, 0, 0), + IMX8MM_PAD_SAI1_RXFS_SAI5_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 1, 0x04E4, 1, 0), + IMX8MM_PAD_SAI1_RXFS_ARM_PLATFORM_TRACE_CLK = IOMUX_PAD(0x03C4, 0x015C, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXFS_GPIO4_IO0 = IOMUX_PAD(0x03C4, 0x015C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXC_SAI1_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXC_SAI5_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 1, 0x04D0, 1, 0), + IMX8MM_PAD_SAI1_RXC_ARM_PLATFORM_TRACE_CTL = IOMUX_PAD(0x03C8, 0x0160, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXC_GPIO4_IO1 = IOMUX_PAD(0x03C8, 0x0160, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD0_SAI1_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD0_SAI5_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 1, 0x04D4, 1, 0), + IMX8MM_PAD_SAI1_RXD0_SAI1_TX_DATA1 = IOMUX_PAD(0x03CC, 0x0164, 2, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD0_PDM_BIT_STREAM0 = IOMUX_PAD(0x03CC, 0x0164, 3, 0x0534, 1, 0), + IMX8MM_PAD_SAI1_RXD0_ARM_PLATFORM_TRACE0 = IOMUX_PAD(0x03CC, 0x0164, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD0_GPIO4_IO2 = IOMUX_PAD(0x03CC, 0x0164, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD0_SRC_BOOT_CFG0 = IOMUX_PAD(0x03CC, 0x0164, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD1_SAI1_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD1_SAI5_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 1, 0x04D8, 1, 0), + IMX8MM_PAD_SAI1_RXD1_PDM_BIT_STREAM1 = IOMUX_PAD(0x03D0, 0x0168, 3, 0x0538, 1, 0), + IMX8MM_PAD_SAI1_RXD1_ARM_PLATFORM_TRACE1 = IOMUX_PAD(0x03D0, 0x0168, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD1_GPIO4_IO3 = IOMUX_PAD(0x03D0, 0x0168, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD1_SRC_BOOT_CFG1 = IOMUX_PAD(0x03D0, 0x0168, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD2_SAI1_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD2_SAI5_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 1, 0x04DC, 1, 0), + IMX8MM_PAD_SAI1_RXD2_PDM_BIT_STREAM2 = IOMUX_PAD(0x03D4, 0x016C, 3, 0x053C, 1, 0), + IMX8MM_PAD_SAI1_RXD2_ARM_PLATFORM_TRACE2 = IOMUX_PAD(0x03D4, 0x016C, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD2_GPIO4_IO4 = IOMUX_PAD(0x03D4, 0x016C, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD2_SRC_BOOT_CFG2 = IOMUX_PAD(0x03D4, 0x016C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD3_SAI1_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD3_SAI5_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 1, 0x04E0, 1, 0), + IMX8MM_PAD_SAI1_RXD3_PDM_BIT_STREAM3 = IOMUX_PAD(0x03D8, 0x0170, 3, 0x0540, 1, 0), + IMX8MM_PAD_SAI1_RXD3_ARM_PLATFORM_TRACE3 = IOMUX_PAD(0x03D8, 0x0170, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD3_GPIO4_IO5 = IOMUX_PAD(0x03D8, 0x0170, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD3_SRC_BOOT_CFG3 = IOMUX_PAD(0x03D8, 0x0170, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD4_SAI1_RX_DATA4 = IOMUX_PAD(0x03DC, 0x0174, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD4_SAI6_TX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 1, 0x051C, 0, 0), + IMX8MM_PAD_SAI1_RXD4_SAI6_RX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 2, 0x0510, 0, 0), + IMX8MM_PAD_SAI1_RXD4_ARM_PLATFORM_TRACE4 = IOMUX_PAD(0x03DC, 0x0174, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD4_GPIO4_IO6 = IOMUX_PAD(0x03DC, 0x0174, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD4_SRC_BOOT_CFG4 = IOMUX_PAD(0x03DC, 0x0174, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD5_SAI1_RX_DATA5 = IOMUX_PAD(0x03E0, 0x0178, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD5_SAI6_TX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD5_SAI6_RX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 2, 0x0514, 0, 0), + IMX8MM_PAD_SAI1_RXD5_SAI1_RX_SYNC = IOMUX_PAD(0x03E0, 0x0178, 3, 0x04C4, 1, 0), + IMX8MM_PAD_SAI1_RXD5_ARM_PLATFORM_TRACE5 = IOMUX_PAD(0x03E0, 0x0178, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD5_GPIO4_IO7 = IOMUX_PAD(0x03E0, 0x0178, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD5_SRC_BOOT_CFG5 = IOMUX_PAD(0x03E0, 0x0178, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD6_SAI1_RX_DATA6 = IOMUX_PAD(0x03E4, 0x017C, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD6_SAI6_TX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 1, 0x0520, 0, 0), + IMX8MM_PAD_SAI1_RXD6_SAI6_RX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 2, 0x0518, 0, 0), + IMX8MM_PAD_SAI1_RXD6_ARM_PLATFORM_TRACE6 = IOMUX_PAD(0x03E4, 0x017C, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD6_GPIO4_IO8 = IOMUX_PAD(0x03E4, 0x017C, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD6_SRC_BOOT_CFG6 = IOMUX_PAD(0x03E4, 0x017C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD7_SAI1_RX_DATA7 = IOMUX_PAD(0x03E8, 0x0180, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD7_SAI6_MCLK = IOMUX_PAD(0x03E8, 0x0180, 1, 0x0530, 0, 0), + IMX8MM_PAD_SAI1_RXD7_SAI1_TX_SYNC = IOMUX_PAD(0x03E8, 0x0180, 2, 0x04CC, 4, 0), + IMX8MM_PAD_SAI1_RXD7_SAI1_TX_DATA4 = IOMUX_PAD(0x03E8, 0x0180, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD7_ARM_PLATFORM_TRACE7 = IOMUX_PAD(0x03E8, 0x0180, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD7_GPIO4_IO9 = IOMUX_PAD(0x03E8, 0x0180, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD7_SRC_BOOT_CFG7 = IOMUX_PAD(0x03E8, 0x0180, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXFS_SAI1_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 0, 0x04CC, 3, 0), + IMX8MM_PAD_SAI1_TXFS_SAI5_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 1, 0x04EC, 1, 0), + IMX8MM_PAD_SAI1_TXFS_ARM_PLATFORM_EVENTO = IOMUX_PAD(0x03EC, 0x0184, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXFS_GPIO4_IO10 = IOMUX_PAD(0x03EC, 0x0184, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXC_SAI1_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 0, 0x04C8, 1, 0), + IMX8MM_PAD_SAI1_TXC_SAI5_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 1, 0x04E8, 1, 0), + IMX8MM_PAD_SAI1_TXC_ARM_PLATFORM_EVENTI = IOMUX_PAD(0x03F0, 0x0188, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXC_GPIO4_IO11 = IOMUX_PAD(0x03F0, 0x0188, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD0_SAI1_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD0_SAI5_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD0_ARM_PLATFORM_TRACE8 = IOMUX_PAD(0x03F4, 0x018C, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD0_GPIO4_IO12 = IOMUX_PAD(0x03F4, 0x018C, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD0_SRC_BOOT_CFG8 = IOMUX_PAD(0x03F4, 0x018C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD1_SAI1_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD1_SAI5_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD1_ARM_PLATFORM_TRACE9 = IOMUX_PAD(0x03F8, 0x0190, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD1_GPIO4_IO13 = IOMUX_PAD(0x03F8, 0x0190, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD1_SRC_BOOT_CFG9 = IOMUX_PAD(0x03F8, 0x0190, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD2_SAI1_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD2_SAI5_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD2_ARM_PLATFORM_TRACE10 = IOMUX_PAD(0x03FC, 0x0194, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD2_GPIO4_IO14 = IOMUX_PAD(0x03FC, 0x0194, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD2_SRC_BOOT_CFG10 = IOMUX_PAD(0x03FC, 0x0194, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD3_SAI1_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD3_SAI5_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD3_ARM_PLATFORM_TRACE11 = IOMUX_PAD(0x0400, 0x0198, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD3_GPIO4_IO15 = IOMUX_PAD(0x0400, 0x0198, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD3_SRC_BOOT_CFG11 = IOMUX_PAD(0x0400, 0x0198, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD4_SAI1_TX_DATA4 = IOMUX_PAD(0x0404, 0x019C, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD4_SAI6_RX_BCLK = IOMUX_PAD(0x0404, 0x019C, 1, 0x0510, 1, 0), + IMX8MM_PAD_SAI1_TXD4_SAI6_TX_BCLK = IOMUX_PAD(0x0404, 0x019C, 2, 0x051C, 1, 0), + IMX8MM_PAD_SAI1_TXD4_ARM_PLATFORM_TRACE12 = IOMUX_PAD(0x0404, 0x019C, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD4_GPIO4_IO16 = IOMUX_PAD(0x0404, 0x019C, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD4_SRC_BOOT_CFG12 = IOMUX_PAD(0x0404, 0x019C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD5_SAI1_TX_DATA5 = IOMUX_PAD(0x0408, 0x01A0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD5_SAI6_RX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 1, 0x0514, 1, 0), + IMX8MM_PAD_SAI1_TXD5_SAI6_TX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 2, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD5_ARM_PLATFORM_TRACE13 = IOMUX_PAD(0x0408, 0x01A0, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD5_GPIO4_IO17 = IOMUX_PAD(0x0408, 0x01A0, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD5_SRC_BOOT_CFG13 = IOMUX_PAD(0x0408, 0x01A0, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD6_SAI1_TX_DATA6 = IOMUX_PAD(0x040C, 0x01A4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD6_SAI6_RX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 1, 0x0518, 1, 0), + IMX8MM_PAD_SAI1_TXD6_SAI6_TX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 2, 0x0520, 1, 0), + IMX8MM_PAD_SAI1_TXD6_ARM_PLATFORM_TRACE14 = IOMUX_PAD(0x040C, 0x01A4, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD6_GPIO4_IO18 = IOMUX_PAD(0x040C, 0x01A4, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD6_SRC_BOOT_CFG14 = IOMUX_PAD(0x040C, 0x01A4, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD7_SAI1_TX_DATA7 = IOMUX_PAD(0x0410, 0x01A8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD7_SAI6_MCLK = IOMUX_PAD(0x0410, 0x01A8, 1, 0x0530, 1, 0), + IMX8MM_PAD_SAI1_TXD7_PDM_CLK = IOMUX_PAD(0x0410, 0x01A8, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD7_ARM_PLATFORM_TRACE15 = IOMUX_PAD(0x0410, 0x01A8, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD7_GPIO4_IO19 = IOMUX_PAD(0x0410, 0x01A8, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD7_SRC_BOOT_CFG15 = IOMUX_PAD(0x0410, 0x01A8, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_MCLK_SAI1_MCLK = IOMUX_PAD(0x0414, 0x01AC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_MCLK_SAI5_MCLK = IOMUX_PAD(0x0414, 0x01AC, 1, 0x052C, 1, 0), + IMX8MM_PAD_SAI1_MCLK_SAI1_TX_BCLK = IOMUX_PAD(0x0414, 0x01AC, 2, 0x04C8, 2, 0), + IMX8MM_PAD_SAI1_MCLK_PDM_CLK = IOMUX_PAD(0x0414, 0x01AC, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_MCLK_GPIO4_IO20 = IOMUX_PAD(0x0414, 0x01AC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_RXFS_SAI2_RX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXFS_SAI5_TX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 1, 0x04EC, 2, 0), + IMX8MM_PAD_SAI2_RXFS_SAI5_TX_DATA1 = IOMUX_PAD(0x0418, 0x01B0, 2, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXFS_SAI2_RX_DATA1 = IOMUX_PAD(0x0418, 0x01B0, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXFS_UART1_TX = IOMUX_PAD(0x0418, 0x01B0, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXFS_UART1_RX = IOMUX_PAD(0x0418, 0x01B0, 4, 0x04F4, 2, 0), + IMX8MM_PAD_SAI2_RXFS_GPIO4_IO21 = IOMUX_PAD(0x0418, 0x01B0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_RXC_SAI2_RX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXC_SAI5_TX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 1, 0x04E8, 2, 0), + IMX8MM_PAD_SAI2_RXC_UART1_RX = IOMUX_PAD(0x041C, 0x01B4, 4, 0x04F4, 3, 0), + IMX8MM_PAD_SAI2_RXC_UART1_TX = IOMUX_PAD(0x041C, 0x01B4, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXC_GPIO4_IO22 = IOMUX_PAD(0x041C, 0x01B4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_RXD0_SAI2_RX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXD0_SAI5_TX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXD0_UART1_RTS_B = IOMUX_PAD(0x0420, 0x01B8, 4, 0x04F0, 2, 0), + IMX8MM_PAD_SAI2_RXD0_UART1_CTS_B = IOMUX_PAD(0x0420, 0x01B8, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXD0_GPIO4_IO23 = IOMUX_PAD(0x0420, 0x01B8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_TXFS_SAI2_TX_SYNC = IOMUX_PAD(0x0424, 0x01BC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXFS_SAI5_TX_DATA1 = IOMUX_PAD(0x0424, 0x01BC, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXFS_SAI2_TX_DATA1 = IOMUX_PAD(0x0424, 0x01BC, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXFS_UART1_CTS_B = IOMUX_PAD(0x0424, 0x01BC, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXFS_UART1_RTS_B = IOMUX_PAD(0x0424, 0x01BC, 4, 0x04F0, 3, 0), + IMX8MM_PAD_SAI2_TXFS_GPIO4_IO24 = IOMUX_PAD(0x0424, 0x01BC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_TXC_SAI2_TX_BCLK = IOMUX_PAD(0x0428, 0x01C0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXC_SAI5_TX_DATA2 = IOMUX_PAD(0x0428, 0x01C0, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXC_GPIO4_IO25 = IOMUX_PAD(0x0428, 0x01C0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_TXD0_SAI2_TX_DATA0 = IOMUX_PAD(0x042C, 0x01C4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXD0_SAI5_TX_DATA3 = IOMUX_PAD(0x042C, 0x01C4, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXD0_GPIO4_IO26 = IOMUX_PAD(0x042C, 0x01C4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_MCLK_SAI2_MCLK = IOMUX_PAD(0x0430, 0x01C8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_MCLK_SAI5_MCLK = IOMUX_PAD(0x0430, 0x01C8, 1, 0x052C, 2, 0), + IMX8MM_PAD_SAI2_MCLK_GPIO4_IO27 = IOMUX_PAD(0x0430, 0x01C8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_RXFS_SAI3_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXFS_GPT1_CAPTURE1 = IOMUX_PAD(0x0434, 0x01CC, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXFS_SAI5_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 2, 0x04E4, 2, 0), + IMX8MM_PAD_SAI3_RXFS_SAI3_RX_DATA1 = IOMUX_PAD(0x0434, 0x01CC, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXFS_GPIO4_IO28 = IOMUX_PAD(0x0434, 0x01CC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_RXC_SAI3_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXC_GPT1_CLK = IOMUX_PAD(0x0438, 0x01D0, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXC_SAI5_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 2, 0x04D0, 2, 0), + IMX8MM_PAD_SAI3_RXC_UART2_CTS_B = IOMUX_PAD(0x0438, 0x01D0, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXC_UART2_RTS_B = IOMUX_PAD(0x0438, 0x01D0, 4, 0x04F8, 2, 0), + IMX8MM_PAD_SAI3_RXC_GPIO4_IO29 = IOMUX_PAD(0x0438, 0x01D0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_RXD_SAI3_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXD_GPT1_COMPARE1 = IOMUX_PAD(0x043C, 0x01D4, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXD_SAI5_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 2, 0x04D4, 2, 0), + IMX8MM_PAD_SAI3_RXD_UART2_RTS_B = IOMUX_PAD(0x043C, 0x01D4, 4, 0x04F8, 3, 0), + IMX8MM_PAD_SAI3_RXD_UART2_CTS_B = IOMUX_PAD(0x043C, 0x01D4, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXD_GPIO4_IO30 = IOMUX_PAD(0x043C, 0x01D4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_TXFS_SAI3_TX_SYNC = IOMUX_PAD(0x0440, 0x01D8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXFS_GPT1_CAPTURE2 = IOMUX_PAD(0x0440, 0x01D8, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXFS_SAI5_RX_DATA1 = IOMUX_PAD(0x0440, 0x01D8, 2, 0x04D8, 2, 0), + IMX8MM_PAD_SAI3_TXFS_SAI3_TX_DATA1 = IOMUX_PAD(0x0440, 0x01D8, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXFS_UART2_RX = IOMUX_PAD(0x0440, 0x01D8, 4, 0x04FC, 2, 0), + IMX8MM_PAD_SAI3_TXFS_UART2_TX = IOMUX_PAD(0x0440, 0x01D8, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXFS_GPIO4_IO31 = IOMUX_PAD(0x0440, 0x01D8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_TXC_SAI3_TX_BCLK = IOMUX_PAD(0x0444, 0x01DC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXC_GPT1_COMPARE2 = IOMUX_PAD(0x0444, 0x01DC, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXC_SAI5_RX_DATA2 = IOMUX_PAD(0x0444, 0x01DC, 2, 0x04DC, 2, 0), + IMX8MM_PAD_SAI3_TXC_UART2_TX = IOMUX_PAD(0x0444, 0x01DC, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXC_UART2_RX = IOMUX_PAD(0x0444, 0x01DC, 4, 0x04FC, 3, 0), + IMX8MM_PAD_SAI3_TXC_GPIO5_IO0 = IOMUX_PAD(0x0444, 0x01DC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_TXD_SAI3_TX_DATA0 = IOMUX_PAD(0x0448, 0x01E0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXD_GPT1_COMPARE3 = IOMUX_PAD(0x0448, 0x01E0, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXD_SAI5_RX_DATA3 = IOMUX_PAD(0x0448, 0x01E0, 2, 0x04E0, 2, 0), + IMX8MM_PAD_SAI3_TXD_GPIO5_IO1 = IOMUX_PAD(0x0448, 0x01E0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_MCLK_SAI3_MCLK = IOMUX_PAD(0x044C, 0x01E4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_MCLK_PWM4_OUT = IOMUX_PAD(0x044C, 0x01E4, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_MCLK_SAI5_MCLK = IOMUX_PAD(0x044C, 0x01E4, 2, 0x052C, 3, 0), + IMX8MM_PAD_SAI3_MCLK_GPIO5_IO2 = IOMUX_PAD(0x044C, 0x01E4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SPDIF_TX_SPDIF1_OUT = IOMUX_PAD(0x0450, 0x01E8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SPDIF_TX_PWM3_OUT = IOMUX_PAD(0x0450, 0x01E8, 1, 0x0000, 0, 0), + IMX8MM_PAD_SPDIF_TX_GPIO5_IO3 = IOMUX_PAD(0x0450, 0x01E8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SPDIF_RX_SPDIF1_IN = IOMUX_PAD(0x0454, 0x01EC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SPDIF_RX_PWM2_OUT = IOMUX_PAD(0x0454, 0x01EC, 1, 0x0000, 0, 0), + IMX8MM_PAD_SPDIF_RX_GPIO5_IO4 = IOMUX_PAD(0x0454, 0x01EC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK = IOMUX_PAD(0x0458, 0x01F0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SPDIF_EXT_CLK_PWM1_OUT = IOMUX_PAD(0x0458, 0x01F0, 1, 0x0000, 0, 0), + IMX8MM_PAD_SPDIF_EXT_CLK_GPIO5_IO5 = IOMUX_PAD(0x0458, 0x01F0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI1_SCLK_ECSPI1_SCLK = IOMUX_PAD(0x045C, 0x01F4, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_SCLK_UART3_RX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0504, 0, 0), + IMX8MM_PAD_ECSPI1_SCLK_UART3_TX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_SCLK_GPIO5_IO6 = IOMUX_PAD(0x045C, 0x01F4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI1_MOSI_ECSPI1_MOSI = IOMUX_PAD(0x0460, 0x01F8, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_MOSI_UART3_TX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_MOSI_UART3_RX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0504, 1, 0), + IMX8MM_PAD_ECSPI1_MOSI_GPIO5_IO7 = IOMUX_PAD(0x0460, 0x01F8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI1_MISO_ECSPI1_MISO = IOMUX_PAD(0x0464, 0x01FC, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_MISO_UART3_CTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_MISO_UART3_RTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0500, 0, 0), + IMX8MM_PAD_ECSPI1_MISO_GPIO5_IO8 = IOMUX_PAD(0x0464, 0x01FC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI1_SS0_ECSPI1_SS0 = IOMUX_PAD(0x0468, 0x0200, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_SS0_UART3_RTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0500, 1, 0), + IMX8MM_PAD_ECSPI1_SS0_UART3_CTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_SS0_GPIO5_IO9 = IOMUX_PAD(0x0468, 0x0200, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI2_SCLK_ECSPI2_SCLK = IOMUX_PAD(0x046C, 0x0204, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_SCLK_UART4_RX = IOMUX_PAD(0x046C, 0x0204, 1, 0x050C, 0, 0), + IMX8MM_PAD_ECSPI2_SCLK_UART4_TX = IOMUX_PAD(0x046C, 0x0204, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_SCLK_GPIO5_IO10 = IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI2_MOSI_ECSPI2_MOSI = IOMUX_PAD(0x0470, 0x0208, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_MOSI_UART4_TX = IOMUX_PAD(0x0470, 0x0208, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_MOSI_UART4_RX = IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0), + IMX8MM_PAD_ECSPI2_MOSI_GPIO5_IO11 = IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI2_MISO_ECSPI2_MISO = IOMUX_PAD(0x0474, 0x020C, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_MISO_UART4_CTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_MISO_UART4_RTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0508, 0, 0), + IMX8MM_PAD_ECSPI2_MISO_GPIO5_IO12 = IOMUX_PAD(0x0474, 0x020C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI2_SS0_ECSPI2_SS0 = IOMUX_PAD(0x0478, 0x0210, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_SS0_UART4_RTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0508, 1, 0), + IMX8MM_PAD_ECSPI2_SS0_UART4_CTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_SS0_GPIO5_IO13 = IOMUX_PAD(0x0478, 0x0210, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C1_SCL_I2C1_SCL = IOMUX_PAD(0x047C, 0x0214, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + IMX8MM_PAD_I2C1_SCL_ENET1_MDC = IOMUX_PAD(0x047C, 0x0214, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C1_SCL_GPIO5_IO14 = IOMUX_PAD(0x047C, 0x0214, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C1_SDA_I2C1_SDA = IOMUX_PAD(0x0480, 0x0218, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + IMX8MM_PAD_I2C1_SDA_ENET1_MDIO = IOMUX_PAD(0x0480, 0x0218, 1, 0x04C0, 2, 0), + IMX8MM_PAD_I2C1_SDA_GPIO5_IO15 = IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C2_SCL_I2C2_SCL = IOMUX_PAD(0x0484, 0x021C, 0, 0x0000, 0, 0), + IMX8MM_PAD_I2C2_SCL_ENET1_1588_EVENT1_IN = IOMUX_PAD(0x0484, 0x021C, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C2_SCL_USDHC3_CD_B = IOMUX_PAD(0x0484, 0x021C, 2, 0x0544, 1, 0), + IMX8MM_PAD_I2C2_SCL_GPIO5_IO16 = IOMUX_PAD(0x0484, 0x021C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C2_SDA_I2C2_SDA = IOMUX_PAD(0x0488, 0x0220, 0, 0x0000, 0, 0), + IMX8MM_PAD_I2C2_SDA_ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x0488, 0x0220, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C2_SDA_USDHC3_WP = IOMUX_PAD(0x0488, 0x0220, 2, 0x0548, 1, 0), + IMX8MM_PAD_I2C2_SDA_GPIO5_IO17 = IOMUX_PAD(0x0488, 0x0220, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C3_SCL_I2C3_SCL = IOMUX_PAD(0x048C, 0x0224, 0, 0x0000, 0, 0), + IMX8MM_PAD_I2C3_SCL_PWM4_OUT = IOMUX_PAD(0x048C, 0x0224, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C3_SCL_GPT2_CLK = IOMUX_PAD(0x048C, 0x0224, 2, 0x0000, 0, 0), + IMX8MM_PAD_I2C3_SCL_GPIO5_IO18 = IOMUX_PAD(0x048C, 0x0224, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C3_SDA_I2C3_SDA = IOMUX_PAD(0x0490, 0x0228, 0, 0x0000, 0, 0), + IMX8MM_PAD_I2C3_SDA_PWM3_OUT = IOMUX_PAD(0x0490, 0x0228, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C3_SDA_GPT3_CLK = IOMUX_PAD(0x0490, 0x0228, 2, 0x0000, 0, 0), + IMX8MM_PAD_I2C3_SDA_GPIO5_IO19 = IOMUX_PAD(0x0490, 0x0228, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C4_SCL_I2C4_SCL = IOMUX_PAD(0x0494, 0x022C, 0, 0x0000, 0, 0), + IMX8MM_PAD_I2C4_SCL_PWM2_OUT = IOMUX_PAD(0x0494, 0x022C, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C4_SCL_PCIE1_CLKREQ_B = IOMUX_PAD(0x0494, 0x022C, 2, 0x0524, 0, 0), + IMX8MM_PAD_I2C4_SCL_GPIO5_IO20 = IOMUX_PAD(0x0494, 0x022C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C4_SDA_I2C4_SDA = IOMUX_PAD(0x0498, 0x0230, 0, 0x0000, 0, 0), + IMX8MM_PAD_I2C4_SDA_PWM1_OUT = IOMUX_PAD(0x0498, 0x0230, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C4_SDA_GPIO5_IO21 = IOMUX_PAD(0x0498, 0x0230, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART1_RXD_UART1_RX = IOMUX_PAD(0x049C, 0x0234, 0, 0x04F4, 0, 0), + IMX8MM_PAD_UART1_RXD_UART1_TX = IOMUX_PAD(0x049C, 0x0234, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART1_RXD_ECSPI3_SCLK = IOMUX_PAD(0x049C, 0x0234, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART1_RXD_GPIO5_IO22 = IOMUX_PAD(0x049C, 0x0234, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART1_TXD_UART1_TX = IOMUX_PAD(0x04A0, 0x0238, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART1_TXD_UART1_RX = IOMUX_PAD(0x04A0, 0x0238, 0, 0x04F4, 1, 0), + IMX8MM_PAD_UART1_TXD_ECSPI3_MOSI = IOMUX_PAD(0x04A0, 0x0238, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART1_TXD_GPIO5_IO23 = IOMUX_PAD(0x04A0, 0x0238, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART2_RXD_UART2_RX = IOMUX_PAD(0x04A4, 0x023C, 0, 0x04FC, 0, 0), + IMX8MM_PAD_UART2_RXD_UART2_TX = IOMUX_PAD(0x04A4, 0x023C, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART2_RXD_ECSPI3_MISO = IOMUX_PAD(0x04A4, 0x023C, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART2_RXD_GPIO5_IO24 = IOMUX_PAD(0x04A4, 0x023C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART2_TXD_UART2_TX = IOMUX_PAD(0x04A8, 0x0240, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART2_TXD_UART2_RX = IOMUX_PAD(0x04A8, 0x0240, 0, 0x04FC, 1, 0), + IMX8MM_PAD_UART2_TXD_ECSPI3_SS0 = IOMUX_PAD(0x04A8, 0x0240, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART2_TXD_GPIO5_IO25 = IOMUX_PAD(0x04A8, 0x0240, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART3_RXD_UART3_RX = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0504, 2, 0), + IMX8MM_PAD_UART3_RXD_UART3_TX = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART3_RXD_UART1_CTS_B = IOMUX_PAD(0x04AC, 0x0244, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART3_RXD_UART1_RTS_B = IOMUX_PAD(0x04AC, 0x0244, 1, 0x04F0, 0, 0), + IMX8MM_PAD_UART3_RXD_USDHC3_RESET_B = IOMUX_PAD(0x04AC, 0x0244, 2, 0x0000, 0, 0), + IMX8MM_PAD_UART3_RXD_GPIO5_IO26 = IOMUX_PAD(0x04AC, 0x0244, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART3_TXD_UART3_TX = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART3_TXD_UART3_RX = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0504, 3, 0), + IMX8MM_PAD_UART3_TXD_UART1_RTS_B = IOMUX_PAD(0x04B0, 0x0248, 1, 0x04F0, 1, 0), + IMX8MM_PAD_UART3_TXD_UART1_CTS_B = IOMUX_PAD(0x04B0, 0x0248, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART3_TXD_USDHC3_VSELECT = IOMUX_PAD(0x04B0, 0x0248, 2, 0x0000, 0, 0), + IMX8MM_PAD_UART3_TXD_GPIO5_IO27 = IOMUX_PAD(0x04B0, 0x0248, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART4_RXD_UART4_RX = IOMUX_PAD(0x04B4, 0x024C, 0, 0x050C, 2, 0), + IMX8MM_PAD_UART4_RXD_UART4_TX = IOMUX_PAD(0x04B4, 0x024C, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART4_RXD_UART2_CTS_B = IOMUX_PAD(0x04B4, 0x024C, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART4_RXD_UART2_RTS_B = IOMUX_PAD(0x04B4, 0x024C, 1, 0x04F8, 0, 0), + IMX8MM_PAD_UART4_RXD_PCIE1_CLKREQ_B = IOMUX_PAD(0x04B4, 0x024C, 2, 0x0524, 1, 0), + IMX8MM_PAD_UART4_RXD_GPIO5_IO28 = IOMUX_PAD(0x04B4, 0x024C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART4_TXD_UART4_TX = IOMUX_PAD(0x04B8, 0x0250, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART4_TXD_UART4_RX = IOMUX_PAD(0x04B8, 0x0250, 0, 0x050C, 3, 0), + IMX8MM_PAD_UART4_TXD_UART2_RTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x04F8, 1, 0), + IMX8MM_PAD_UART4_TXD_UART2_CTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART4_TXD_GPIO5_IO29 = IOMUX_PAD(0x04B8, 0x0250, 5, 0x0000, 0, 0), +}; + +static inline void imx8mm_setup_pad(iomux_v3_cfg_t pad) +{ + void __iomem *iomux = IOMEM(MX8MM_IOMUXC_BASE_ADDR); + + imx8m_setup_pad(iomux, pad); +} + +#endif -- cgit v1.2.3 From 8764645099f700b38198294c5f68ecb2f380944e Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 11 Feb 2020 09:36:54 +0100 Subject: ARM: i.MX8M: Add imx8mm-regs.h Add various base addresses for the i.MX8MM. Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/include/mach/imx8mm-regs.h | 46 ++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 arch/arm/mach-imx/include/mach/imx8mm-regs.h (limited to 'arch/arm/mach-imx/include') diff --git a/arch/arm/mach-imx/include/mach/imx8mm-regs.h b/arch/arm/mach-imx/include/mach/imx8mm-regs.h new file mode 100644 index 0000000000..1325c78dbc --- /dev/null +++ b/arch/arm/mach-imx/include/mach/imx8mm-regs.h @@ -0,0 +1,46 @@ +#ifndef __MACH_IMX8MM_REGS_H +#define __MACH_IMX8MM_REGS_H + +#include + +#define MX8MM_M4_BOOTROM_BASE_ADDR 0x007e0000 + +#define MX8MM_GPIO1_BASE_ADDR 0x30200000 +#define MX8MM_GPIO2_BASE_ADDR 0x30210000 +#define MX8MM_GPIO3_BASE_ADDR 0x30220000 +#define MX8MM_GPIO4_BASE_ADDR 0x30230000 +#define MX8MM_GPIO5_BASE_ADDR 0x30240000 +#define MX8MM_WDOG1_BASE_ADDR 0x30280000 +#define MX8MM_WDOG2_BASE_ADDR 0x30290000 +#define MX8MM_WDOG3_BASE_ADDR 0x302a0000 +#define MX8MM_IOMUXC_BASE_ADDR 0x30330000 +#define MX8MM_IOMUXC_GPR_BASE_ADDR 0x30340000 +#define MX8MM_OCOTP_BASE_ADDR 0x30350000 +#define MX8MM_ANATOP_BASE_ADDR 0x30360000 +#define MX8MM_CCM_BASE_ADDR 0x30380000 +#define MX8MM_SRC_BASE_ADDR 0x30390000 +#define MX8MM_GPC_BASE_ADDR 0x303a0000 +#define MX8MM_SYSCNT_RD_BASE_ADDR 0x306a0000 +#define MX8MM_SYSCNT_CMP_BASE_ADDR 0x306b0000 +#define MX8MM_SYSCNT_CTRL_BASE_ADDR 0x306c0000 +#define MX8MM_UART1_BASE_ADDR 0x30860000 +#define MX8MM_UART3_BASE_ADDR 0x30880000 +#define MX8MM_UART2_BASE_ADDR 0x30890000 +#define MX8MM_I2C1_BASE_ADDR 0x30a20000 +#define MX8MM_I2C2_BASE_ADDR 0x30a30000 +#define MX8MM_I2C3_BASE_ADDR 0x30a40000 +#define MX8MM_I2C4_BASE_ADDR 0x30a50000 +#define MX8MM_UART4_BASE_ADDR 0x30a60000 +#define MX8MM_USDHC1_BASE_ADDR 0x30b40000 +#define MX8MM_USDHC2_BASE_ADDR 0x30b50000 +#define MX8MM_USDHC3_BASE_ADDR 0x30b60000 +#define MX8MM_USB1_BASE_ADDR 0x32e40000 +#define MX8MM_USB2_BASE_ADDR 0x32e50000 +#define MX8MM_TZASC_BASE_ADDR 0x32f80000 +#define MX8MM_SRC_IPS_BASE_ADDR 0x30390000 +#define MX8MM_SRC_DDRC_RCR_ADDR 0x30391000 +#define MX8MM_SRC_DDRC2_RCR_ADDR 0x30391004 +#define MX8MM_DDRC_DDR_SS_GPR0 0x3d000000 +#define MX8MM_DDR_CSD1_BASE_ADDR 0x40000000 + +#endif /* __MACH_IMX8MM_REGS_H */ -- cgit v1.2.3 From e42d463de2ce0c49576bac58c1ab8b1885294f9c Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 12 Feb 2020 16:29:21 +0100 Subject: ARM: i.MX8M: rename imx8_* bootsource functions to imx8mq_* Those will differ between i.MX8MQ and i.MX8MM, so give them the appropriate prefix before introducing i.MX8MM support. Signed-off-by: Sascha Hauer --- arch/arm/boards/nxp-imx8mq-evk/lowlevel.c | 2 +- arch/arm/boards/phytec-som-imx8mq/lowlevel.c | 2 +- arch/arm/boards/zii-imx8mq-dev/lowlevel.c | 2 +- arch/arm/mach-imx/boot.c | 6 +++--- arch/arm/mach-imx/imx8m.c | 2 +- arch/arm/mach-imx/include/mach/generic.h | 4 ++-- 6 files changed, 9 insertions(+), 9 deletions(-) (limited to 'arch/arm/mach-imx/include') diff --git a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c index 68464e330d..58dafe7aac 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c +++ b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c @@ -84,7 +84,7 @@ static __noreturn noinline void nxp_imx8mq_evk_start(void) * for the piggy data, so we need to ensure that we are running * the same code in DRAM. */ - imx8_get_boot_source(&src, &instance); + imx8mq_get_boot_source(&src, &instance); if (src == BOOTSOURCE_MMC) ret = imx8_esdhc_load_image(instance, false); BUG_ON(ret); diff --git a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c index 4ce5c4ecde..cdbf88e8c1 100644 --- a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c +++ b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c @@ -52,7 +52,7 @@ static void phytec_imx8mq_som_sram_setup(void) ddr_init(); - imx8_get_boot_source(&src, &instance); + imx8mq_get_boot_source(&src, &instance); if (src == BOOTSOURCE_MMC) ret = imx8_esdhc_load_image(instance, true); diff --git a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c index 63f87eede0..81ef4de421 100644 --- a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c +++ b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c @@ -74,7 +74,7 @@ static void zii_imx8mq_dev_sram_setup(void) if (running_as_ddr_helper()) ddr_helper_halt(); - imx8_get_boot_source(&src, &instance); + imx8mq_get_boot_source(&src, &instance); if (src == BOOTSOURCE_MMC) ret = imx8_esdhc_load_image(instance, true); diff --git a/arch/arm/mach-imx/boot.c b/arch/arm/mach-imx/boot.c index 0c51767c42..350355fb41 100644 --- a/arch/arm/mach-imx/boot.c +++ b/arch/arm/mach-imx/boot.c @@ -579,7 +579,7 @@ void vf610_boot_save_loc(void) imx_boot_save_loc(vf610_get_boot_source); } -void imx8_get_boot_source(enum bootsource *src, int *instance) +void imx8mq_get_boot_source(enum bootsource *src, int *instance) { unsigned long addr; @@ -590,7 +590,7 @@ void imx8_get_boot_source(enum bootsource *src, int *instance) __imx7_get_boot_source(src, instance, addr); } -void imx8_boot_save_loc(void) +void imx8mq_boot_save_loc(void) { - imx_boot_save_loc(imx8_get_boot_source); + imx_boot_save_loc(imx8mq_get_boot_source); } diff --git a/arch/arm/mach-imx/imx8m.c b/arch/arm/mach-imx/imx8m.c index d06ba098c3..031b25bfc1 100644 --- a/arch/arm/mach-imx/imx8m.c +++ b/arch/arm/mach-imx/imx8m.c @@ -42,7 +42,7 @@ int imx8mq_init(void) struct arm_smccc_res res; const char *cputypestr; - imx8_boot_save_loc(); + imx8mq_boot_save_loc(); switch (type) { case IMX8M_CPUTYPE_IMX8MQ: diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h index 5102c34e4c..3666fd4f8b 100644 --- a/arch/arm/mach-imx/include/mach/generic.h +++ b/arch/arm/mach-imx/include/mach/generic.h @@ -16,7 +16,7 @@ void imx53_boot_save_loc(void); void imx6_boot_save_loc(void); void imx7_boot_save_loc(void); void vf610_boot_save_loc(void); -void imx8_boot_save_loc(void); +void imx8mq_boot_save_loc(void); void imx25_get_boot_source(enum bootsource *src, int *instance); void imx27_get_boot_source(enum bootsource *src, int *instance); @@ -26,7 +26,7 @@ void imx53_get_boot_source(enum bootsource *src, int *instance); void imx6_get_boot_source(enum bootsource *src, int *instance); void imx7_get_boot_source(enum bootsource *src, int *instance); void vf610_get_boot_source(enum bootsource *src, int *instance); -void imx8_get_boot_source(enum bootsource *src, int *instance); +void imx8mq_get_boot_source(enum bootsource *src, int *instance); int imx1_init(void); int imx21_init(void); -- cgit v1.2.3 From 26c4e01dbdb3e002e9e013329a43313786058fbb Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 14 Feb 2020 09:34:55 +0100 Subject: ARM: i.MX8M: rename i.MX8M specific function The big i.MX8 variants have completely other UARTs than the i.MX8M variants, so rename imx8_uart_setup_ll() to imx8m_uart_setup_ll(). Signed-off-by: Sascha Hauer --- arch/arm/boards/nxp-imx8mq-evk/lowlevel.c | 2 +- arch/arm/boards/phytec-som-imx8mq/lowlevel.c | 2 +- arch/arm/boards/zii-imx8mq-dev/lowlevel.c | 2 +- arch/arm/mach-imx/include/mach/debug_ll.h | 4 ++-- 4 files changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm/mach-imx/include') diff --git a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c index 58dafe7aac..bf84189139 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c +++ b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c @@ -36,7 +36,7 @@ static void setup_uart(void) imx8mq_setup_pad(IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL); - imx8_uart_setup_ll(); + imx8m_uart_setup_ll(); putc_ll('>'); } diff --git a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c index cdbf88e8c1..6983d44b95 100644 --- a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c +++ b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c @@ -39,7 +39,7 @@ static void setup_uart(void) imx8mq_setup_pad(IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL); - imx8_uart_setup_ll(); + imx8m_uart_setup_ll(); putc_ll('>'); } diff --git a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c index 81ef4de421..232de71483 100644 --- a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c +++ b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c @@ -38,7 +38,7 @@ static void setup_uart(void) imx8mq_setup_pad(IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL); - imx8_uart_setup_ll(); + imx8m_uart_setup_ll(); putc_ll('>'); } diff --git a/arch/arm/mach-imx/include/mach/debug_ll.h b/arch/arm/mach-imx/include/mach/debug_ll.h index 1550e059ed..5eed01631c 100644 --- a/arch/arm/mach-imx/include/mach/debug_ll.h +++ b/arch/arm/mach-imx/include/mach/debug_ll.h @@ -98,7 +98,7 @@ static inline void vf610_uart_setup_ll(void) lpuart_setup(base, 66000000); } -static inline void imx8_uart_setup_ll(void) +static inline void imx8m_uart_setup_ll(void) { void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC, CONFIG_DEBUG_IMX_UART_PORT)); @@ -127,7 +127,7 @@ static inline void imx53_uart_setup_ll(void) {} static inline void imx6_uart_setup_ll(void) {} static inline void imx7_uart_setup_ll(void) {} static inline void vf610_uart_setup_ll(void) {} -static inline void imx8_uart_setup_ll(void) {} +static inline void imx8m_uart_setup_ll(void) {} #endif /* CONFIG_DEBUG_LL */ -- cgit v1.2.3 From b2b23193ea3e1ebdef18dccf5f4139a9bdcc14b7 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 14 Feb 2020 09:39:55 +0100 Subject: ARM: i.MX8M: rename functions to be i.MX8M specific imx8_esdhc_load_image() and friends can't be used on the big variants of the i.MX8, so rename to imx8m_esdhc_load_image() Signed-off-by: Sascha Hauer --- arch/arm/boards/nxp-imx8mq-evk/lowlevel.c | 2 +- arch/arm/boards/phytec-som-imx8mq/lowlevel.c | 2 +- arch/arm/boards/zii-imx8mq-dev/lowlevel.c | 2 +- arch/arm/mach-imx/include/mach/xload.h | 2 +- drivers/mci/imx-esdhc-pbl.c | 12 ++++++------ 5 files changed, 10 insertions(+), 10 deletions(-) (limited to 'arch/arm/mach-imx/include') diff --git a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c index bf84189139..a501f03722 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c +++ b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c @@ -86,7 +86,7 @@ static __noreturn noinline void nxp_imx8mq_evk_start(void) */ imx8mq_get_boot_source(&src, &instance); if (src == BOOTSOURCE_MMC) - ret = imx8_esdhc_load_image(instance, false); + ret = imx8m_esdhc_load_image(instance, false); BUG_ON(ret); memcpy((void *)MX8MQ_ATF_BL33_BASE_ADDR, diff --git a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c index 6983d44b95..f14366a27b 100644 --- a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c +++ b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c @@ -55,7 +55,7 @@ static void phytec_imx8mq_som_sram_setup(void) imx8mq_get_boot_source(&src, &instance); if (src == BOOTSOURCE_MMC) - ret = imx8_esdhc_load_image(instance, true); + ret = imx8m_esdhc_load_image(instance, true); BUG_ON(ret); } diff --git a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c index 232de71483..482d70cb01 100644 --- a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c +++ b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c @@ -77,7 +77,7 @@ static void zii_imx8mq_dev_sram_setup(void) imx8mq_get_boot_source(&src, &instance); if (src == BOOTSOURCE_MMC) - ret = imx8_esdhc_load_image(instance, true); + ret = imx8m_esdhc_load_image(instance, true); BUG_ON(ret); } diff --git a/arch/arm/mach-imx/include/mach/xload.h b/arch/arm/mach-imx/include/mach/xload.h index 9709b13dfb..dca05aa5d4 100644 --- a/arch/arm/mach-imx/include/mach/xload.h +++ b/arch/arm/mach-imx/include/mach/xload.h @@ -5,7 +5,7 @@ int imx53_nand_start_image(void); int imx6_spi_load_image(int instance, unsigned int flash_offset, void *buf, int len); int imx6_spi_start_image(int instance); int imx6_esdhc_start_image(int instance); -int imx8_esdhc_load_image(int instance, bool start); +int imx8m_esdhc_load_image(int instance, bool start); int imx_image_size(void); int piggydata_size(void); diff --git a/drivers/mci/imx-esdhc-pbl.c b/drivers/mci/imx-esdhc-pbl.c index 2579cfd9d1..6610cee3b5 100644 --- a/drivers/mci/imx-esdhc-pbl.c +++ b/drivers/mci/imx-esdhc-pbl.c @@ -201,9 +201,9 @@ static void imx_esdhc_init(struct fsl_esdhc_host *host, FIELD_PREP(WML_RD_WML_MASK, SECTOR_WML)); } -static int imx8_esdhc_init(struct fsl_esdhc_host *host, - struct esdhc_soc_data *data, - int instance) +static int imx8m_esdhc_init(struct fsl_esdhc_host *host, + struct esdhc_soc_data *data, + int instance) { switch (instance) { case 0: @@ -261,7 +261,7 @@ int imx6_esdhc_start_image(int instance) } /** - * imx8_esdhc_load_image - Load and optionally start an image from USDHC controller + * imx8m_esdhc_load_image - Load and optionally start an image from USDHC controller * @instance: The USDHC controller instance (0..2) * @start: Whether to directly start the loaded image * @@ -273,13 +273,13 @@ int imx6_esdhc_start_image(int instance) * Return: If successful, this function does not return (if directly started) * or 0. A negative error code is returned when this function fails. */ -int imx8_esdhc_load_image(int instance, bool start) +int imx8m_esdhc_load_image(int instance, bool start) { struct esdhc_soc_data data; struct fsl_esdhc_host host; int ret; - ret = imx8_esdhc_init(&host, &data, instance); + ret = imx8m_esdhc_init(&host, &data, instance); if (ret) return ret; -- cgit v1.2.3 From 1f33b72b9570c57590426afdd955cbb5693f1404 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 13 Feb 2020 15:10:47 +0100 Subject: ARM: i.MX: Add SoC namespace to imx7/8m CCM defines The CCM defines used on i.MX7 and i.MX8M do not have any SoC namespace. Add it to make clear where they are supposed to be used. Since it looks confusing to call i.MX7 specific defines on i.MX8M and vice versa, duplicate them for both SoCs. Signed-off-by: Sascha Hauer --- arch/arm/boards/freescale-mx7-sabresd/lowlevel.c | 12 ++++----- arch/arm/boards/nxp-imx8mq-evk/lowlevel.c | 12 ++++----- arch/arm/boards/phytec-som-imx8mq/lowlevel.c | 12 ++++----- arch/arm/boards/zii-imx7d-dev/lowlevel.c | 12 ++++----- arch/arm/boards/zii-imx8mq-dev/lowlevel.c | 12 ++++----- arch/arm/mach-imx/include/mach/imx7-ccm-regs.h | 33 +++++++++++++++++------- arch/arm/mach-imx/include/mach/imx8-ccm-regs.h | 25 ++++++++++++++---- 7 files changed, 74 insertions(+), 44 deletions(-) (limited to 'arch/arm/mach-imx/include') diff --git a/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c b/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c index edd965e4ec..995bf6cca9 100644 --- a/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c +++ b/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c @@ -17,12 +17,12 @@ static inline void setup_uart(void) { void __iomem *ccm = IOMEM(MX7_CCM_BASE_ADDR); - writel(CCM_CCGR_SETTINGn_NEEDED(0), - ccm + CCM_CCGRn_CLR(CCM_CCGR_UART1)); - writel(CCM_TARGET_ROOTn_ENABLE | UART1_CLK_ROOT__OSC_24M, - ccm + CCM_TARGET_ROOTn(UART1_CLK_ROOT)); - writel(CCM_CCGR_SETTINGn_NEEDED(0), - ccm + CCM_CCGRn_SET(CCM_CCGR_UART1)); + writel(IMX7_CCM_CCGR_SETTINGn_NEEDED(0), + ccm + IMX7_CCM_CCGRn_CLR(IMX7_CCM_CCGR_UART1)); + writel(IMX7_CCM_TARGET_ROOTn_ENABLE | IMX7_UART1_CLK_ROOT__OSC_24M, + ccm + IMX7_CCM_TARGET_ROOTn(IMX7_UART1_CLK_ROOT)); + writel(IMX7_CCM_CCGR_SETTINGn_NEEDED(0), + ccm + IMX7_CCM_CCGRn_SET(IMX7_CCM_CCGR_UART1)); imx7_setup_pad(MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX); diff --git a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c index a501f03722..0f4b27a9af 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c +++ b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c @@ -27,12 +27,12 @@ static void setup_uart(void) { void __iomem *ccm = IOMEM(MX8MQ_CCM_BASE_ADDR); - writel(CCM_CCGR_SETTINGn_NEEDED(0), - ccm + CCM_CCGRn_CLR(CCM_CCGR_UART1)); - writel(CCM_TARGET_ROOTn_ENABLE | UART1_CLK_ROOT__25M_REF_CLK, - ccm + CCM_TARGET_ROOTn(UART1_CLK_ROOT)); - writel(CCM_CCGR_SETTINGn_NEEDED(0), - ccm + CCM_CCGRn_SET(CCM_CCGR_UART1)); + writel(IMX8M_CCM_CCGR_SETTINGn_NEEDED(0), + ccm + IMX8M_CCM_CCGRn_CLR(IMX8M_CCM_CCGR_UART1)); + writel(IMX8M_CCM_TARGET_ROOTn_ENABLE | IMX8M_UART1_CLK_ROOT__25M_REF_CLK, + ccm + IMX8M_CCM_TARGET_ROOTn(IMX8M_UART1_CLK_ROOT)); + writel(IMX8M_CCM_CCGR_SETTINGn_NEEDED(0), + ccm + IMX8M_CCM_CCGRn_SET(IMX8M_CCM_CCGR_UART1)); imx8mq_setup_pad(IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL); diff --git a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c index f14366a27b..0abe0a6bc2 100644 --- a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c +++ b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c @@ -30,12 +30,12 @@ static void setup_uart(void) { void __iomem *ccm = IOMEM(MX8MQ_CCM_BASE_ADDR); - writel(CCM_CCGR_SETTINGn_NEEDED(0), - ccm + CCM_CCGRn_CLR(CCM_CCGR_UART1)); - writel(CCM_TARGET_ROOTn_ENABLE | UART1_CLK_ROOT__25M_REF_CLK, - ccm + CCM_TARGET_ROOTn(UART1_CLK_ROOT)); - writel(CCM_CCGR_SETTINGn_NEEDED(0), - ccm + CCM_CCGRn_SET(CCM_CCGR_UART1)); + writel(IMX8M_CCM_CCGR_SETTINGn_NEEDED(0), + ccm + IMX8M_CCM_CCGRn_CLR(IMX8M_CCM_CCGR_UART1)); + writel(IMX8M_CCM_TARGET_ROOTn_ENABLE | IMX8M_UART1_CLK_ROOT__25M_REF_CLK, + ccm + IMX8M_CCM_TARGET_ROOTn(IMX8M_UART1_CLK_ROOT)); + writel(IMX8M_CCM_CCGR_SETTINGn_NEEDED(0), + ccm + IMX8M_CCM_CCGRn_SET(IMX8M_CCM_CCGR_UART1)); imx8mq_setup_pad(IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL); diff --git a/arch/arm/boards/zii-imx7d-dev/lowlevel.c b/arch/arm/boards/zii-imx7d-dev/lowlevel.c index 83d01446b9..83fb646fd6 100644 --- a/arch/arm/boards/zii-imx7d-dev/lowlevel.c +++ b/arch/arm/boards/zii-imx7d-dev/lowlevel.c @@ -25,12 +25,12 @@ static inline void setup_uart(void) { void __iomem *ccm = IOMEM(MX7_CCM_BASE_ADDR); - writel(CCM_CCGR_SETTINGn_NEEDED(0), - ccm + CCM_CCGRn_CLR(CCM_CCGR_UART2)); - writel(CCM_TARGET_ROOTn_ENABLE | UART2_CLK_ROOT__OSC_24M, - ccm + CCM_TARGET_ROOTn(UART2_CLK_ROOT)); - writel(CCM_CCGR_SETTINGn_NEEDED(0), - ccm + CCM_CCGRn_SET(CCM_CCGR_UART2)); + writel(IMX7_CCM_CCGR_SETTINGn_NEEDED(0), + ccm + IMX7_CCM_CCGRn_CLR(IMX7_CCM_CCGR_UART2)); + writel(IMX7_CCM_TARGET_ROOTn_ENABLE | IMX7_UART2_CLK_ROOT__OSC_24M, + ccm + IMX7_CCM_TARGET_ROOTn(IMX7_UART2_CLK_ROOT)); + writel(IMX7_CCM_CCGR_SETTINGn_NEEDED(0), + ccm + IMX7_CCM_CCGRn_SET(IMX7_CCM_CCGR_UART2)); imx7_setup_pad(MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX); diff --git a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c index 482d70cb01..0bb141fbf2 100644 --- a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c +++ b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c @@ -29,12 +29,12 @@ static void setup_uart(void) { void __iomem *ccm = IOMEM(MX8MQ_CCM_BASE_ADDR); - writel(CCM_CCGR_SETTINGn_NEEDED(0), - ccm + CCM_CCGRn_CLR(CCM_CCGR_UART1)); - writel(CCM_TARGET_ROOTn_ENABLE | UART1_CLK_ROOT__25M_REF_CLK, - ccm + CCM_TARGET_ROOTn(UART1_CLK_ROOT)); - writel(CCM_CCGR_SETTINGn_NEEDED(0), - ccm + CCM_CCGRn_SET(CCM_CCGR_UART1)); + writel(IMX8M_CCM_CCGR_SETTINGn_NEEDED(0), + ccm + IMX8M_CCM_CCGRn_CLR(IMX8M_CCM_CCGR_UART1)); + writel(IMX8M_CCM_TARGET_ROOTn_ENABLE | IMX8M_UART1_CLK_ROOT__25M_REF_CLK, + ccm + IMX8M_CCM_TARGET_ROOTn(IMX8M_UART1_CLK_ROOT)); + writel(IMX8M_CCM_CCGR_SETTINGn_NEEDED(0), + ccm + IMX8M_CCM_CCGRn_SET(IMX8M_CCM_CCGR_UART1)); imx8mq_setup_pad(IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL); diff --git a/arch/arm/mach-imx/include/mach/imx7-ccm-regs.h b/arch/arm/mach-imx/include/mach/imx7-ccm-regs.h index 43b9425df2..b78adf9f1c 100644 --- a/arch/arm/mach-imx/include/mach/imx7-ccm-regs.h +++ b/arch/arm/mach-imx/include/mach/imx7-ccm-regs.h @@ -1,21 +1,36 @@ #ifndef __MACH_IMX7_CCM_REGS_H__ #define __MACH_IMX7_CCM_REGS_H__ -#include "ccm.h" +#define IMX7_CCM_CCGR_UART1 148 +#define IMX7_CCM_CCGR_UART2 149 -#define CCM_CCGR_UART1 148 -#define CCM_CCGR_UART2 149 - -#define CLOCK_ROOT_INDEX(x) (((x) - 0x8000) / 128) +#define IMX7_CLOCK_ROOT_INDEX(x) (((x) - 0x8000) / 128) /* * Taken from "Table 5-11. Clock Root Table" from i.MX7 Dual Processor * Reference Manual */ -#define UART1_CLK_ROOT CLOCK_ROOT_INDEX(0xaf80) -#define UART1_CLK_ROOT__OSC_24M CCM_TARGET_ROOTn_MUX(0b000) +#define IMX7_UART1_CLK_ROOT IMX7_CLOCK_ROOT_INDEX(0xaf80) +#define IMX7_UART1_CLK_ROOT__OSC_24M IMX7_CCM_TARGET_ROOTn_MUX(0b000) + +#define IMX7_UART2_CLK_ROOT IMX7_CLOCK_ROOT_INDEX(0xb000) +#define IMX7_UART2_CLK_ROOT__OSC_24M IMX7_CCM_TARGET_ROOTn_MUX(0b000) + +/* 0 <= n <= 190 */ +#define IMX7_CCM_CCGRn_SET(n) (0x4004 + 16 * (n)) +#define IMX7_CCM_CCGRn_CLR(n) (0x4008 + 16 * (n)) + +/* 0 <= n <= 120 */ +#define IMX7_CCM_TARGET_ROOTn(n) (0x8000 + 128 * (n)) + +#define IMX7_CCM_TARGET_ROOTn_MUX(x) ((x) << 24) +#define IMX7_CCM_TARGET_ROOTn_ENABLE BIT(28) + -#define UART2_CLK_ROOT CLOCK_ROOT_INDEX(0xb000) -#define UART2_CLK_ROOT__OSC_24M CCM_TARGET_ROOTn_MUX(0b000) +#define IMX7_CCM_CCGR_SETTINGn(n, s) ((s) << ((n) * 4)) +#define IMX7_CCM_CCGR_SETTINGn_NOT_NEEDED(n) IMX7_CCM_CCGR_SETTINGn(n, 0b00) +#define IMX7_CCM_CCGR_SETTINGn_NEEDED_RUN(n) IMX7_CCM_CCGR_SETTINGn(n, 0b01) +#define IMX7_CCM_CCGR_SETTINGn_NEEDED_RUN_WAIT(n) IMX7_CCM_CCGR_SETTINGn(n, 0b10) +#define IMX7_CCM_CCGR_SETTINGn_NEEDED(n) IMX7_CCM_CCGR_SETTINGn(n, 0b11) #endif diff --git a/arch/arm/mach-imx/include/mach/imx8-ccm-regs.h b/arch/arm/mach-imx/include/mach/imx8-ccm-regs.h index 93b584ebe2..59d25d797f 100644 --- a/arch/arm/mach-imx/include/mach/imx8-ccm-regs.h +++ b/arch/arm/mach-imx/include/mach/imx8-ccm-regs.h @@ -1,15 +1,30 @@ #ifndef __MACH_IMX8_CCM_REGS_H__ #define __MACH_IMX8_CCM_REGS_H__ -#include "ccm.h" - -#define CCM_CCGR_UART1 73 +#define IMX8M_CCM_CCGR_UART1 73 /* * Taken from "Table 5-1. Clock Root Table" from i.MX8M Quad * Applications Processor Reference Manual */ -#define UART1_CLK_ROOT 94 -#define UART1_CLK_ROOT__25M_REF_CLK CCM_TARGET_ROOTn_MUX(0b000) +#define IMX8M_UART1_CLK_ROOT 94 +#define IMX8M_UART1_CLK_ROOT__25M_REF_CLK IMX8M_CCM_TARGET_ROOTn_MUX(0b000) + +/* 0 <= n <= 190 */ +#define IMX8M_CCM_CCGRn_SET(n) (0x4004 + 16 * (n)) +#define IMX8M_CCM_CCGRn_CLR(n) (0x4008 + 16 * (n)) + +/* 0 <= n <= 120 */ +#define IMX8M_CCM_TARGET_ROOTn(n) (0x8000 + 128 * (n)) + +#define IMX8M_CCM_TARGET_ROOTn_MUX(x) ((x) << 24) +#define IMX8M_CCM_TARGET_ROOTn_ENABLE BIT(28) + + +#define IMX8M_CCM_CCGR_SETTINGn(n, s) ((s) << ((n) * 4)) +#define IMX8M_CCM_CCGR_SETTINGn_NOT_NEEDED(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b00) +#define IMX8M_CCM_CCGR_SETTINGn_NEEDED_RUN(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b01) +#define IMX8M_CCM_CCGR_SETTINGn_NEEDED_RUN_WAIT(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b10) +#define IMX8M_CCM_CCGR_SETTINGn_NEEDED(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b11) #endif -- cgit v1.2.3 From 450955bc9d49e8112833e6bf8f88b51816840d1b Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 14 Feb 2020 12:24:15 +0100 Subject: Add some CCM defines for i.MX8M This adds some clock slice indices and CCGR defines needed for the lowlevel i.MX8M code. Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/include/mach/imx8-ccm-regs.h | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-imx/include') diff --git a/arch/arm/mach-imx/include/mach/imx8-ccm-regs.h b/arch/arm/mach-imx/include/mach/imx8-ccm-regs.h index 59d25d797f..66ace0f1c4 100644 --- a/arch/arm/mach-imx/include/mach/imx8-ccm-regs.h +++ b/arch/arm/mach-imx/include/mach/imx8-ccm-regs.h @@ -1,13 +1,33 @@ #ifndef __MACH_IMX8_CCM_REGS_H__ #define __MACH_IMX8_CCM_REGS_H__ -#define IMX8M_CCM_CCGR_UART1 73 +#include + +#define IMX8M_CCM_CCGR_DDR1 5 +#define IMX8M_CCM_CCGR_I2C1 23 +#define IMX8M_CCM_CCGR_I2C2 24 +#define IMX8M_CCM_CCGR_I2C3 25 +#define IMX8M_CCM_CCGR_I2C4 26 +#define IMX8M_CCM_CCGR_SCTR 57 +#define IMX8M_CCM_CCGR_UART1 73 +#define IMX8M_CCM_CCGR_UART2 74 +#define IMX8M_CCM_CCGR_UART3 75 +#define IMX8M_CCM_CCGR_UART4 76 +#define IMX8M_CCM_CCGR_GIC 92 /* * Taken from "Table 5-1. Clock Root Table" from i.MX8M Quad * Applications Processor Reference Manual */ +#define IMX8M_ARM_A53_CLK_ROOT 0 +#define IMX8M_DRAM_SEL_CFG 48 +#define IMX8M_DRAM_ALT_CLK_ROOT 64 +#define IMX8M_DRAM_APB_CLK_ROOT 65 #define IMX8M_UART1_CLK_ROOT 94 +#define IMX8M_UART2_CLK_ROOT 95 +#define IMX8M_UART3_CLK_ROOT 96 +#define IMX8M_UART4_CLK_ROOT 97 +#define IMX8M_GIC_CLK_ROOT 100 #define IMX8M_UART1_CLK_ROOT__25M_REF_CLK IMX8M_CCM_TARGET_ROOTn_MUX(0b000) /* 0 <= n <= 190 */ @@ -17,10 +37,11 @@ /* 0 <= n <= 120 */ #define IMX8M_CCM_TARGET_ROOTn(n) (0x8000 + 128 * (n)) +#define IMX8M_CCM_TARGET_ROOTn_POST_DIV(n) ((n) & 0x0000003f) +#define IMX8M_CCM_TARGET_ROOTn_PRE_DIV(n) (((n) << 16) & 0x00070000) #define IMX8M_CCM_TARGET_ROOTn_MUX(x) ((x) << 24) #define IMX8M_CCM_TARGET_ROOTn_ENABLE BIT(28) - #define IMX8M_CCM_CCGR_SETTINGn(n, s) ((s) << ((n) * 4)) #define IMX8M_CCM_CCGR_SETTINGn_NOT_NEEDED(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b00) #define IMX8M_CCM_CCGR_SETTINGn_NEEDED_RUN(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b01) -- cgit v1.2.3 From 3ccc8873c1dc10b63e75223622dfc6301d72df68 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 13 Feb 2020 15:16:24 +0100 Subject: ARM: i.MX8M: rename imx8-ccm-regs.h to imx8m-ccm-regs.h i.MX8 is something different than the i.MX8M and both will not share this header file, so rename it to imx8m-ccm-regs.h Signed-off-by: Sascha Hauer --- arch/arm/boards/nxp-imx8mq-evk/lowlevel.c | 2 +- arch/arm/boards/phytec-som-imx8mq/lowlevel.c | 2 +- arch/arm/boards/zii-imx8mq-dev/lowlevel.c | 2 +- arch/arm/mach-imx/include/mach/imx8-ccm-regs.h | 51 ------------------------- arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h | 51 +++++++++++++++++++++++++ 5 files changed, 54 insertions(+), 54 deletions(-) delete mode 100644 arch/arm/mach-imx/include/mach/imx8-ccm-regs.h create mode 100644 arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h (limited to 'arch/arm/mach-imx/include') diff --git a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c index 0f4b27a9af..ac97023631 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c +++ b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c @@ -5,7 +5,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c index 0abe0a6bc2..08287a135f 100644 --- a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c +++ b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c index 0bb141fbf2..bc966589c3 100644 --- a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c +++ b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/include/mach/imx8-ccm-regs.h b/arch/arm/mach-imx/include/mach/imx8-ccm-regs.h deleted file mode 100644 index 66ace0f1c4..0000000000 --- a/arch/arm/mach-imx/include/mach/imx8-ccm-regs.h +++ /dev/null @@ -1,51 +0,0 @@ -#ifndef __MACH_IMX8_CCM_REGS_H__ -#define __MACH_IMX8_CCM_REGS_H__ - -#include - -#define IMX8M_CCM_CCGR_DDR1 5 -#define IMX8M_CCM_CCGR_I2C1 23 -#define IMX8M_CCM_CCGR_I2C2 24 -#define IMX8M_CCM_CCGR_I2C3 25 -#define IMX8M_CCM_CCGR_I2C4 26 -#define IMX8M_CCM_CCGR_SCTR 57 -#define IMX8M_CCM_CCGR_UART1 73 -#define IMX8M_CCM_CCGR_UART2 74 -#define IMX8M_CCM_CCGR_UART3 75 -#define IMX8M_CCM_CCGR_UART4 76 -#define IMX8M_CCM_CCGR_GIC 92 - -/* - * Taken from "Table 5-1. Clock Root Table" from i.MX8M Quad - * Applications Processor Reference Manual - */ -#define IMX8M_ARM_A53_CLK_ROOT 0 -#define IMX8M_DRAM_SEL_CFG 48 -#define IMX8M_DRAM_ALT_CLK_ROOT 64 -#define IMX8M_DRAM_APB_CLK_ROOT 65 -#define IMX8M_UART1_CLK_ROOT 94 -#define IMX8M_UART2_CLK_ROOT 95 -#define IMX8M_UART3_CLK_ROOT 96 -#define IMX8M_UART4_CLK_ROOT 97 -#define IMX8M_GIC_CLK_ROOT 100 -#define IMX8M_UART1_CLK_ROOT__25M_REF_CLK IMX8M_CCM_TARGET_ROOTn_MUX(0b000) - -/* 0 <= n <= 190 */ -#define IMX8M_CCM_CCGRn_SET(n) (0x4004 + 16 * (n)) -#define IMX8M_CCM_CCGRn_CLR(n) (0x4008 + 16 * (n)) - -/* 0 <= n <= 120 */ -#define IMX8M_CCM_TARGET_ROOTn(n) (0x8000 + 128 * (n)) - -#define IMX8M_CCM_TARGET_ROOTn_POST_DIV(n) ((n) & 0x0000003f) -#define IMX8M_CCM_TARGET_ROOTn_PRE_DIV(n) (((n) << 16) & 0x00070000) -#define IMX8M_CCM_TARGET_ROOTn_MUX(x) ((x) << 24) -#define IMX8M_CCM_TARGET_ROOTn_ENABLE BIT(28) - -#define IMX8M_CCM_CCGR_SETTINGn(n, s) ((s) << ((n) * 4)) -#define IMX8M_CCM_CCGR_SETTINGn_NOT_NEEDED(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b00) -#define IMX8M_CCM_CCGR_SETTINGn_NEEDED_RUN(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b01) -#define IMX8M_CCM_CCGR_SETTINGn_NEEDED_RUN_WAIT(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b10) -#define IMX8M_CCM_CCGR_SETTINGn_NEEDED(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b11) - -#endif diff --git a/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h b/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h new file mode 100644 index 0000000000..66ace0f1c4 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h @@ -0,0 +1,51 @@ +#ifndef __MACH_IMX8_CCM_REGS_H__ +#define __MACH_IMX8_CCM_REGS_H__ + +#include + +#define IMX8M_CCM_CCGR_DDR1 5 +#define IMX8M_CCM_CCGR_I2C1 23 +#define IMX8M_CCM_CCGR_I2C2 24 +#define IMX8M_CCM_CCGR_I2C3 25 +#define IMX8M_CCM_CCGR_I2C4 26 +#define IMX8M_CCM_CCGR_SCTR 57 +#define IMX8M_CCM_CCGR_UART1 73 +#define IMX8M_CCM_CCGR_UART2 74 +#define IMX8M_CCM_CCGR_UART3 75 +#define IMX8M_CCM_CCGR_UART4 76 +#define IMX8M_CCM_CCGR_GIC 92 + +/* + * Taken from "Table 5-1. Clock Root Table" from i.MX8M Quad + * Applications Processor Reference Manual + */ +#define IMX8M_ARM_A53_CLK_ROOT 0 +#define IMX8M_DRAM_SEL_CFG 48 +#define IMX8M_DRAM_ALT_CLK_ROOT 64 +#define IMX8M_DRAM_APB_CLK_ROOT 65 +#define IMX8M_UART1_CLK_ROOT 94 +#define IMX8M_UART2_CLK_ROOT 95 +#define IMX8M_UART3_CLK_ROOT 96 +#define IMX8M_UART4_CLK_ROOT 97 +#define IMX8M_GIC_CLK_ROOT 100 +#define IMX8M_UART1_CLK_ROOT__25M_REF_CLK IMX8M_CCM_TARGET_ROOTn_MUX(0b000) + +/* 0 <= n <= 190 */ +#define IMX8M_CCM_CCGRn_SET(n) (0x4004 + 16 * (n)) +#define IMX8M_CCM_CCGRn_CLR(n) (0x4008 + 16 * (n)) + +/* 0 <= n <= 120 */ +#define IMX8M_CCM_TARGET_ROOTn(n) (0x8000 + 128 * (n)) + +#define IMX8M_CCM_TARGET_ROOTn_POST_DIV(n) ((n) & 0x0000003f) +#define IMX8M_CCM_TARGET_ROOTn_PRE_DIV(n) (((n) << 16) & 0x00070000) +#define IMX8M_CCM_TARGET_ROOTn_MUX(x) ((x) << 24) +#define IMX8M_CCM_TARGET_ROOTn_ENABLE BIT(28) + +#define IMX8M_CCM_CCGR_SETTINGn(n, s) ((s) << ((n) * 4)) +#define IMX8M_CCM_CCGR_SETTINGn_NOT_NEEDED(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b00) +#define IMX8M_CCM_CCGR_SETTINGn_NEEDED_RUN(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b01) +#define IMX8M_CCM_CCGR_SETTINGn_NEEDED_RUN_WAIT(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b10) +#define IMX8M_CCM_CCGR_SETTINGn_NEEDED(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b11) + +#endif -- cgit v1.2.3 From d97b8f93ee35b09d6a76cfb137c708470e3e47b2 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 14 Feb 2020 12:30:45 +0100 Subject: ARM: i.MX8M: Add some lowlevel clock functions U-Boot has some lowlevel clock functions which take a clock slice index as argument. Add them for barebox as well to make the code better comparable to U-Boot. Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/imx8m.c | 24 ++++++++++++++++++++++++ arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h | 4 ++++ 2 files changed, 28 insertions(+) (limited to 'arch/arm/mach-imx/include') diff --git a/arch/arm/mach-imx/imx8m.c b/arch/arm/mach-imx/imx8m.c index 031b25bfc1..596c4140b3 100644 --- a/arch/arm/mach-imx/imx8m.c +++ b/arch/arm/mach-imx/imx8m.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -28,6 +29,29 @@ #define FSL_SIP_BUILDINFO 0xC2000003 #define FSL_SIP_BUILDINFO_GET_COMMITHASH 0x00 +void imx8m_clock_set_target_val(int clock_id, u32 val) +{ + void *ccm = IOMEM(MX8M_CCM_BASE_ADDR); + + writel(val, ccm + IMX8M_CCM_TARGET_ROOTn(clock_id)); +} + +void imx8m_ccgr_clock_enable(int index) +{ + void *ccm = IOMEM(MX8M_CCM_BASE_ADDR); + + writel(IMX8M_CCM_CCGR_SETTINGn_NEEDED(0), + ccm + IMX8M_CCM_CCGRn_SET(index)); +} + +void imx8m_ccgr_clock_disable(int index) +{ + void *ccm = IOMEM(MX8M_CCM_BASE_ADDR); + + writel(IMX8M_CCM_CCGR_SETTINGn_NEEDED(0), + ccm + IMX8M_CCM_CCGRn_CLR(index)); +} + u64 imx8mq_uid(void) { return imx_ocotp_read_uid(IOMEM(MX8MQ_OCOTP_BASE_ADDR)); diff --git a/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h b/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h index 66ace0f1c4..ff207b80f9 100644 --- a/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h +++ b/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h @@ -48,4 +48,8 @@ #define IMX8M_CCM_CCGR_SETTINGn_NEEDED_RUN_WAIT(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b10) #define IMX8M_CCM_CCGR_SETTINGn_NEEDED(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b11) +void imx8m_clock_set_target_val(int clock_id, u32 val); +void imx8m_ccgr_clock_enable(int index); +void imx8m_ccgr_clock_disable(int index); + #endif -- cgit v1.2.3 From cc76af2676a995a34aa7aad01ce0752f62bff7e0 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 13 Feb 2020 15:14:52 +0100 Subject: ARM: i.MX7: Add and use function for early UART clock setup The i.MX7 boards have the same code for setting up the UART clock. Add a common helper function for it. Signed-off-by: Sascha Hauer --- arch/arm/boards/freescale-mx7-sabresd/lowlevel.c | 9 +-------- arch/arm/boards/zii-imx7d-dev/lowlevel.c | 9 +-------- arch/arm/mach-imx/include/mach/imx7-ccm-regs.h | 12 ++++++++++++ 3 files changed, 14 insertions(+), 16 deletions(-) (limited to 'arch/arm/mach-imx/include') diff --git a/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c b/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c index 995bf6cca9..8db46ca696 100644 --- a/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c +++ b/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c @@ -15,14 +15,7 @@ extern char __dtb_imx7d_sdb_start[]; static inline void setup_uart(void) { - void __iomem *ccm = IOMEM(MX7_CCM_BASE_ADDR); - - writel(IMX7_CCM_CCGR_SETTINGn_NEEDED(0), - ccm + IMX7_CCM_CCGRn_CLR(IMX7_CCM_CCGR_UART1)); - writel(IMX7_CCM_TARGET_ROOTn_ENABLE | IMX7_UART1_CLK_ROOT__OSC_24M, - ccm + IMX7_CCM_TARGET_ROOTn(IMX7_UART1_CLK_ROOT)); - writel(IMX7_CCM_CCGR_SETTINGn_NEEDED(0), - ccm + IMX7_CCM_CCGRn_SET(IMX7_CCM_CCGR_UART1)); + imx7_early_setup_uart_clock(); imx7_setup_pad(MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX); diff --git a/arch/arm/boards/zii-imx7d-dev/lowlevel.c b/arch/arm/boards/zii-imx7d-dev/lowlevel.c index 83fb646fd6..7579a2a8a0 100644 --- a/arch/arm/boards/zii-imx7d-dev/lowlevel.c +++ b/arch/arm/boards/zii-imx7d-dev/lowlevel.c @@ -23,14 +23,7 @@ extern char __dtb_z_imx7d_zii_rmu2_start[]; static inline void setup_uart(void) { - void __iomem *ccm = IOMEM(MX7_CCM_BASE_ADDR); - - writel(IMX7_CCM_CCGR_SETTINGn_NEEDED(0), - ccm + IMX7_CCM_CCGRn_CLR(IMX7_CCM_CCGR_UART2)); - writel(IMX7_CCM_TARGET_ROOTn_ENABLE | IMX7_UART2_CLK_ROOT__OSC_24M, - ccm + IMX7_CCM_TARGET_ROOTn(IMX7_UART2_CLK_ROOT)); - writel(IMX7_CCM_CCGR_SETTINGn_NEEDED(0), - ccm + IMX7_CCM_CCGRn_SET(IMX7_CCM_CCGR_UART2)); + imx7_early_setup_uart_clock(); imx7_setup_pad(MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX); diff --git a/arch/arm/mach-imx/include/mach/imx7-ccm-regs.h b/arch/arm/mach-imx/include/mach/imx7-ccm-regs.h index b78adf9f1c..de6eb1bbd1 100644 --- a/arch/arm/mach-imx/include/mach/imx7-ccm-regs.h +++ b/arch/arm/mach-imx/include/mach/imx7-ccm-regs.h @@ -33,4 +33,16 @@ #define IMX7_CCM_CCGR_SETTINGn_NEEDED_RUN_WAIT(n) IMX7_CCM_CCGR_SETTINGn(n, 0b10) #define IMX7_CCM_CCGR_SETTINGn_NEEDED(n) IMX7_CCM_CCGR_SETTINGn(n, 0b11) +static inline void imx7_early_setup_uart_clock(void) +{ + void __iomem *ccm = IOMEM(MX7_CCM_BASE_ADDR); + + writel(IMX7_CCM_CCGR_SETTINGn_NEEDED(0), + ccm + IMX7_CCM_CCGRn_CLR(IMX7_CCM_CCGR_UART1)); + writel(IMX7_CCM_TARGET_ROOTn_ENABLE | IMX7_UART1_CLK_ROOT__OSC_24M, + ccm + IMX7_CCM_TARGET_ROOTn(IMX7_UART1_CLK_ROOT)); + writel(IMX7_CCM_CCGR_SETTINGn_NEEDED(0), + ccm + IMX7_CCM_CCGRn_SET(IMX7_CCM_CCGR_UART1)); +} + #endif -- cgit v1.2.3 From 4fce211e966c33ca882b05b1cc45ea5f137af9f8 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 13 Feb 2020 15:15:02 +0100 Subject: ARM: i.MX8M: Add and use function for early UART clock setup The i.MX8M boards all have the same code for setting up the UART clock. Add a common helper for it. In the helper just setup the clocks for all UARTs as it's not worth it to have separate functions for each UART. Signed-off-by: Sascha Hauer --- arch/arm/boards/nxp-imx8mq-evk/lowlevel.c | 9 +-------- arch/arm/boards/phytec-som-imx8mq/lowlevel.c | 9 +-------- arch/arm/boards/zii-imx8mq-dev/lowlevel.c | 9 +-------- arch/arm/mach-imx/imx8m.c | 26 +++++++++++++++++++++++++ arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h | 1 + 5 files changed, 30 insertions(+), 24 deletions(-) (limited to 'arch/arm/mach-imx/include') diff --git a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c index ac97023631..ebf6203f3a 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c +++ b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c @@ -25,14 +25,7 @@ extern char __dtb_imx8mq_evk_start[]; static void setup_uart(void) { - void __iomem *ccm = IOMEM(MX8MQ_CCM_BASE_ADDR); - - writel(IMX8M_CCM_CCGR_SETTINGn_NEEDED(0), - ccm + IMX8M_CCM_CCGRn_CLR(IMX8M_CCM_CCGR_UART1)); - writel(IMX8M_CCM_TARGET_ROOTn_ENABLE | IMX8M_UART1_CLK_ROOT__25M_REF_CLK, - ccm + IMX8M_CCM_TARGET_ROOTn(IMX8M_UART1_CLK_ROOT)); - writel(IMX8M_CCM_CCGR_SETTINGn_NEEDED(0), - ccm + IMX8M_CCM_CCGRn_SET(IMX8M_CCM_CCGR_UART1)); + imx8m_early_setup_uart_clock(); imx8mq_setup_pad(IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL); diff --git a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c index 08287a135f..9a48c1dded 100644 --- a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c +++ b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c @@ -28,14 +28,7 @@ extern char __dtb_imx8mq_phytec_phycore_som_start[]; static void setup_uart(void) { - void __iomem *ccm = IOMEM(MX8MQ_CCM_BASE_ADDR); - - writel(IMX8M_CCM_CCGR_SETTINGn_NEEDED(0), - ccm + IMX8M_CCM_CCGRn_CLR(IMX8M_CCM_CCGR_UART1)); - writel(IMX8M_CCM_TARGET_ROOTn_ENABLE | IMX8M_UART1_CLK_ROOT__25M_REF_CLK, - ccm + IMX8M_CCM_TARGET_ROOTn(IMX8M_UART1_CLK_ROOT)); - writel(IMX8M_CCM_CCGR_SETTINGn_NEEDED(0), - ccm + IMX8M_CCM_CCGRn_SET(IMX8M_CCM_CCGR_UART1)); + imx8m_early_setup_uart_clock(); imx8mq_setup_pad(IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL); diff --git a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c index bc966589c3..c1ec827184 100644 --- a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c +++ b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c @@ -27,14 +27,7 @@ static void setup_uart(void) { - void __iomem *ccm = IOMEM(MX8MQ_CCM_BASE_ADDR); - - writel(IMX8M_CCM_CCGR_SETTINGn_NEEDED(0), - ccm + IMX8M_CCM_CCGRn_CLR(IMX8M_CCM_CCGR_UART1)); - writel(IMX8M_CCM_TARGET_ROOTn_ENABLE | IMX8M_UART1_CLK_ROOT__25M_REF_CLK, - ccm + IMX8M_CCM_TARGET_ROOTn(IMX8M_UART1_CLK_ROOT)); - writel(IMX8M_CCM_CCGR_SETTINGn_NEEDED(0), - ccm + IMX8M_CCM_CCGRn_SET(IMX8M_CCM_CCGR_UART1)); + imx8m_early_setup_uart_clock(); imx8mq_setup_pad(IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL); diff --git a/arch/arm/mach-imx/imx8m.c b/arch/arm/mach-imx/imx8m.c index 596c4140b3..d044531520 100644 --- a/arch/arm/mach-imx/imx8m.c +++ b/arch/arm/mach-imx/imx8m.c @@ -133,3 +133,29 @@ static int imx8mq_report_hdmi_firmware(void) return 0; } console_initcall(imx8mq_report_hdmi_firmware); + +void imx8m_early_setup_uart_clock(void) +{ + imx8m_ccgr_clock_disable(IMX8M_CCM_CCGR_UART1); + imx8m_ccgr_clock_disable(IMX8M_CCM_CCGR_UART2); + imx8m_ccgr_clock_disable(IMX8M_CCM_CCGR_UART3); + imx8m_ccgr_clock_disable(IMX8M_CCM_CCGR_UART4); + + imx8m_clock_set_target_val(IMX8M_UART1_CLK_ROOT, + IMX8M_CCM_TARGET_ROOTn_ENABLE | + IMX8M_UART1_CLK_ROOT__25M_REF_CLK); + imx8m_clock_set_target_val(IMX8M_UART2_CLK_ROOT, + IMX8M_CCM_TARGET_ROOTn_ENABLE | + IMX8M_UART1_CLK_ROOT__25M_REF_CLK); + imx8m_clock_set_target_val(IMX8M_UART3_CLK_ROOT, + IMX8M_CCM_TARGET_ROOTn_ENABLE | + IMX8M_UART1_CLK_ROOT__25M_REF_CLK); + imx8m_clock_set_target_val(IMX8M_UART4_CLK_ROOT, + IMX8M_CCM_TARGET_ROOTn_ENABLE | + IMX8M_UART1_CLK_ROOT__25M_REF_CLK); + + imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_UART1); + imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_UART2); + imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_UART3); + imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_UART4); +} diff --git a/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h b/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h index ff207b80f9..70a7e4af9d 100644 --- a/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h +++ b/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h @@ -48,6 +48,7 @@ #define IMX8M_CCM_CCGR_SETTINGn_NEEDED_RUN_WAIT(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b10) #define IMX8M_CCM_CCGR_SETTINGn_NEEDED(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b11) +void imx8m_early_setup_uart_clock(void); void imx8m_clock_set_target_val(int clock_id, u32 val); void imx8m_ccgr_clock_enable(int index); void imx8m_ccgr_clock_disable(int index); -- cgit v1.2.3 From 0266042714b2e0a17e397fe5d8a29a4487785df4 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 14 Feb 2020 11:53:38 +0100 Subject: ARM: i.MX8M: Add DDR controller support This adds the DDR driver for the i.MX8MQ/i.MX8MM. It's taken from U-Boot v2020.04-rc1 with slight modifications for barebox The i.MX8MQ boards in the tree currently use the output of an earlier version of the NXP i.MX8M DDR Tool which doesn't use a controller driver but instead does most stuff in board code. It seems this can coexist with the new driver, only a few helper functions that previously lived in arch/arm/mach-imx/imx8-ddrc.c are now provided by the new driver. Tested on an i.MX8MM EVK Signed-off-by: Sascha Hauer --- arch/arm/boards/nxp-imx8mq-evk/ddr.h | 9 +- arch/arm/boards/nxp-imx8mq-evk/lowlevel.c | 2 +- arch/arm/boards/phytec-som-imx8mq/ddr.h | 7 +- arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c | 1 - arch/arm/boards/phytec-som-imx8mq/lowlevel.c | 2 +- arch/arm/boards/zii-imx8mq-dev/ddr.h | 9 +- arch/arm/boards/zii-imx8mq-dev/lowlevel.c | 2 +- arch/arm/mach-imx/Kconfig | 1 + arch/arm/mach-imx/Makefile | 2 +- arch/arm/mach-imx/imx8-ddrc.c | 91 --- arch/arm/mach-imx/include/mach/imx8-ddrc.h | 66 -- drivers/ddr/Kconfig | 1 + drivers/ddr/Makefile | 1 + drivers/ddr/imx8m/Kconfig | 7 + drivers/ddr/imx8m/Makefile | 7 + drivers/ddr/imx8m/ddr_init.c | 211 +++++++ drivers/ddr/imx8m/ddrphy_csr.c | 732 +++++++++++++++++++++++ drivers/ddr/imx8m/ddrphy_train.c | 112 ++++ drivers/ddr/imx8m/ddrphy_utils.c | 306 ++++++++++ drivers/ddr/imx8m/helper.c | 86 +++ include/soc/imx8m/ddr.h | 407 +++++++++++++ include/soc/imx8m/lpddr4_define.h | 97 +++ 22 files changed, 1975 insertions(+), 184 deletions(-) delete mode 100644 arch/arm/mach-imx/imx8-ddrc.c delete mode 100644 arch/arm/mach-imx/include/mach/imx8-ddrc.h create mode 100644 drivers/ddr/imx8m/Kconfig create mode 100644 drivers/ddr/imx8m/Makefile create mode 100644 drivers/ddr/imx8m/ddr_init.c create mode 100644 drivers/ddr/imx8m/ddrphy_csr.c create mode 100644 drivers/ddr/imx8m/ddrphy_train.c create mode 100644 drivers/ddr/imx8m/ddrphy_utils.c create mode 100644 drivers/ddr/imx8m/helper.c create mode 100644 include/soc/imx8m/ddr.h create mode 100644 include/soc/imx8m/lpddr4_define.h (limited to 'arch/arm/mach-imx/include') diff --git a/arch/arm/boards/nxp-imx8mq-evk/ddr.h b/arch/arm/boards/nxp-imx8mq-evk/ddr.h index 65115dba1e..fd09ad6bf1 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/ddr.h +++ b/arch/arm/boards/nxp-imx8mq-evk/ddr.h @@ -8,7 +8,7 @@ */ #include #include -#include +#include /* * Code generated by i.MX8 M DDR Tool doesn't have any prefixes in the @@ -20,10 +20,3 @@ void nxp_imx8mq_evk_ddr_init(void); void nxp_imx8mq_evk_ddr_cfg_phy(void); - -#define FW_1D_IMAGE lpddr4_pmu_train_1d_imem_bin, \ - lpddr4_pmu_train_1d_dmem_bin -#define FW_2D_IMAGE lpddr4_pmu_train_2d_imem_bin, \ - lpddr4_pmu_train_2d_dmem_bin - - diff --git a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c index bf3d43b9a3..39358afad1 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c +++ b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/boards/phytec-som-imx8mq/ddr.h b/arch/arm/boards/phytec-som-imx8mq/ddr.h index 18ae6e9022..e125feaaf0 100644 --- a/arch/arm/boards/phytec-som-imx8mq/ddr.h +++ b/arch/arm/boards/phytec-som-imx8mq/ddr.h @@ -7,7 +7,7 @@ */ #include #include -#include +#include /* * Code generated by i.MX8 M DDR Tool doesn't have any prefixes in the @@ -19,8 +19,3 @@ void phytec_imx8mq_phycore_ddr_init(void); void phytec_imx8mq_phycore_ddr_cfg_phy(void); - -#define FW_1D_IMAGE lpddr4_pmu_train_1d_imem_bin, \ - lpddr4_pmu_train_1d_dmem_bin -#define FW_2D_IMAGE lpddr4_pmu_train_2d_imem_bin, \ - lpddr4_pmu_train_2d_dmem_bin diff --git a/arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c b/arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c index 56af647821..cc00527649 100644 --- a/arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c +++ b/arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c @@ -9,7 +9,6 @@ #include "ddr.h" -extern void wait_ddrphy_training_complete(void); void ddr_cfg_phy(void) { unsigned int tmp, tmp_t; diff --git a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c index f460901a2c..f5b9b6c008 100644 --- a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c +++ b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/boards/zii-imx8mq-dev/ddr.h b/arch/arm/boards/zii-imx8mq-dev/ddr.h index 1293ad3f34..a395211e62 100644 --- a/arch/arm/boards/zii-imx8mq-dev/ddr.h +++ b/arch/arm/boards/zii-imx8mq-dev/ddr.h @@ -8,7 +8,7 @@ */ #include #include -#include +#include /* * Code generated by i.MX8 M DDR Tool doesn't have any prefixes in the @@ -20,10 +20,3 @@ void zii_imx8mq_rdu3_ddr_init(void); void zii_imx8mq_rdu3_ddr_cfg_phy(void); - -#define FW_1D_IMAGE lpddr4_pmu_train_1d_imem_bin, \ - lpddr4_pmu_train_1d_dmem_bin -#define FW_2D_IMAGE lpddr4_pmu_train_2d_imem_bin, \ - lpddr4_pmu_train_2d_dmem_bin - - diff --git a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c index 2646f5fc3e..6400833809 100644 --- a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c +++ b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index d717d83865..7b79d80748 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -183,6 +183,7 @@ config ARCH_IMX8M select COMMON_CLK_OF_PROVIDER select ARCH_HAS_FEC_IMX select HW_HAS_PCI + select IMX8M_DRAM select PBL_VERIFY_PIGGY if HABV4 config ARCH_IMX8MQ diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 862dc78ff2..105785ba1b 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -16,7 +16,7 @@ lwl-$(CONFIG_ARCH_IMX6) += imx6-mmdc.o obj-$(CONFIG_ARCH_IMX7) += imx7.o obj-$(CONFIG_ARCH_VF610) += vf610.o obj-$(CONFIG_ARCH_IMX8M) += imx8m.o -lwl-$(CONFIG_ARCH_IMX8MQ) += imx8-ddrc.o atf.o +lwl-$(CONFIG_ARCH_IMX8MQ) += atf.o obj-$(CONFIG_IMX_IIM) += iim.o obj-$(CONFIG_NAND_IMX) += nand.o lwl-$(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND) += external-nand-boot.o diff --git a/arch/arm/mach-imx/imx8-ddrc.c b/arch/arm/mach-imx/imx8-ddrc.c deleted file mode 100644 index 8bb2672102..0000000000 --- a/arch/arm/mach-imx/imx8-ddrc.c +++ /dev/null @@ -1,91 +0,0 @@ -#include -#include -#include -#include - -void ddrc_phy_load_firmware(void __iomem *phy, - enum ddrc_phy_firmware_offset offset, - const u16 *blob, size_t size) -{ - while (size) { - writew(*blob++, phy + DDRC_PHY_REG(offset)); - offset++; - size -= sizeof(*blob); - } -} - -enum pmc_constants { - PMC_MESSAGE_ID, - PMC_MESSAGE_STREAM, - - PMC_TRAIN_SUCCESS = 0x07, - PMC_TRAIN_STREAM_START = 0x08, - PMC_TRAIN_FAIL = 0xff, -}; - -static u32 ddrc_phy_get_message(void __iomem *phy, int type) -{ - u32 r, message; - - /* - * When BIT0 set to 0, the PMU has a message for the user - * Wait for it indefinitely. - */ - readl_poll_timeout(phy + DDRC_PHY_REG(0xd0004), - r, !(r & BIT(0)), 0); - - switch (type) { - case PMC_MESSAGE_ID: - /* - * Get the major message ID - */ - message = readl(phy + DDRC_PHY_REG(0xd0032)); - break; - case PMC_MESSAGE_STREAM: - message = readl(phy + DDRC_PHY_REG(0xd0034)); - message <<= 16; - message |= readl(phy + DDRC_PHY_REG(0xd0032)); - break; - } - - /* - * By setting this register to 0, the user acknowledges the - * receipt of the message. - */ - writel(0x00000000, phy + DDRC_PHY_REG(0xd0031)); - /* - * When BIT0 set to 0, the PMU has a message for the user - */ - readl_poll_timeout(phy + DDRC_PHY_REG(0xd0004), - r, r & BIT(0), 0); - - writel(0x00000001, phy + DDRC_PHY_REG(0xd0031)); - - return message; -} - -static void ddrc_phy_fetch_streaming_message(void __iomem *phy) -{ - const u16 index = ddrc_phy_get_message(phy, PMC_MESSAGE_STREAM); - u16 i; - - for (i = 0; i < index; i++) - ddrc_phy_get_message(phy, PMC_MESSAGE_STREAM); -} - -void ddrc_phy_wait_training_complete(void __iomem *phy) -{ - for (;;) { - const u32 m = ddrc_phy_get_message(phy, PMC_MESSAGE_ID); - - switch (m) { - case PMC_TRAIN_STREAM_START: - ddrc_phy_fetch_streaming_message(phy); - break; - case PMC_TRAIN_SUCCESS: - return; - case PMC_TRAIN_FAIL: - hang(); - } - } -} diff --git a/arch/arm/mach-imx/include/mach/imx8-ddrc.h b/arch/arm/mach-imx/include/mach/imx8-ddrc.h deleted file mode 100644 index d49e29f263..0000000000 --- a/arch/arm/mach-imx/include/mach/imx8-ddrc.h +++ /dev/null @@ -1,66 +0,0 @@ -#ifndef __IMX8_DDRC_H__ -#define __IMX8_DDRC_H__ - -#include -#include -#include -#include - -enum ddrc_phy_firmware_offset { - DDRC_PHY_IMEM = 0x00050000U, - DDRC_PHY_DMEM = 0x00054000U, -}; - -void ddrc_phy_load_firmware(void __iomem *, - enum ddrc_phy_firmware_offset, - const u16 *, size_t); - -#define DDRC_PHY_REG(x) ((x) * 4) - -void ddrc_phy_wait_training_complete(void __iomem *phy); - - -/* - * i.MX8M DDR Tool compatibility layer - */ - -#define reg32_write(a, v) writel(v, a) -#define reg32_read(a) readl(a) - -static inline void wait_ddrphy_training_complete(void) -{ - ddrc_phy_wait_training_complete(IOMEM(MX8MQ_DDRC_PHY_BASE_ADDR)); -} - -#define __ddr_load_train_code(imem, dmem) \ - do { \ - const u16 *__mem; \ - size_t __size; \ - \ - get_builtin_firmware(imem, &__mem, &__size); \ - ddrc_phy_load_firmware(IOMEM(MX8MQ_DDRC_PHY_BASE_ADDR), \ - DDRC_PHY_IMEM, __mem, __size); \ - \ - get_builtin_firmware(dmem, &__mem, &__size); \ - ddrc_phy_load_firmware(IOMEM(MX8MQ_DDRC_PHY_BASE_ADDR), \ - DDRC_PHY_DMEM, __mem, __size); \ - } while (0) - -#define ddr_load_train_code(imem_dmem) __ddr_load_train_code(imem_dmem) - -#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + (X * 0x2000000)) - -#define DDRC_STAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x04) -#define DDRC_MRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18) -#define DDRC_PWRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x30) -#define DDRC_RFSHCTL3(X) (DDRC_IPS_BASE_ADDR(X) + 0x60) -#define DDRC_CRCPARSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xcc) -#define DDRC_DFIMISC(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b0) -#define DDRC_DFISTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1bc) -#define DDRC_SWCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x320) -#define DDRC_SWSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x324) -#define DDRC_PCTRL_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x490) - -#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000)) - -#endif \ No newline at end of file diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig index 4ea71598af..d92c272b58 100644 --- a/drivers/ddr/Kconfig +++ b/drivers/ddr/Kconfig @@ -1 +1,2 @@ source "drivers/ddr/fsl/Kconfig" +source "drivers/ddr/imx8m/Kconfig" diff --git a/drivers/ddr/Makefile b/drivers/ddr/Makefile index faf2f9e1d6..7e33182cbc 100644 --- a/drivers/ddr/Makefile +++ b/drivers/ddr/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_DDR_FSL) += fsl/ +obj-$(CONFIG_IMX8M_DRAM) += imx8m/ diff --git a/drivers/ddr/imx8m/Kconfig b/drivers/ddr/imx8m/Kconfig new file mode 100644 index 0000000000..e8bce8c49d --- /dev/null +++ b/drivers/ddr/imx8m/Kconfig @@ -0,0 +1,7 @@ +menu "i.MX8M DDR controllers" + depends on ARCH_IMX8MQ || ARCH_IMX8MM + +config IMX8M_DRAM + bool "imx8m dram controller support" + +endmenu diff --git a/drivers/ddr/imx8m/Makefile b/drivers/ddr/imx8m/Makefile new file mode 100644 index 0000000000..2be313900f --- /dev/null +++ b/drivers/ddr/imx8m/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +pbl-$(CONFIG_IMX8M_DRAM) += helper.o ddrphy_utils.o ddrphy_train.o ddrphy_csr.o ddr_init.o diff --git a/drivers/ddr/imx8m/ddr_init.c b/drivers/ddr/imx8m/ddr_init.c new file mode 100644 index 0000000000..374601b786 --- /dev/null +++ b/drivers/ddr/imx8m/ddr_init.c @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2019 NXP + */ +#define DEBUG +#include +#include +#include +#include +#include +#include +#include + +#define SRC_DDRC_RCR_ADDR MX8MQ_SRC_DDRC_RCR_ADDR + +static void ddr_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) +{ + int i = 0; + + for (i = 0; i < num; i++) { + reg32_write((unsigned long)ddrc_cfg->reg, ddrc_cfg->val); + ddrc_cfg++; + } +} + +static int imx8m_ddr_init(unsigned long src_ddrc_rcr, + struct dram_timing_info *dram_timing) +{ + unsigned int tmp, initial_drate, target_freq; + int ret; + + debug("DDRINFO: start DRAM init\n"); + + debug("DDRINFO: cfg clk\n"); + + /* disable iso */ + reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */ + reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */ + + initial_drate = dram_timing->fsp_msg[0].drate; + /* default to the frequency point 0 clock */ + ddrphy_init_set_dfi_clk(initial_drate); + + /* D-aasert the presetn */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006); + + /* Step2: Program the dwc_ddr_umctl2 registers */ + debug("DDRINFO: ddrc config start\n"); + ddr_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num); + debug("DDRINFO: ddrc config done\n"); + + /* Step3: De-assert reset signal(core_ddrc_rstn & aresetn_n) */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004); + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000); + + /* + * Step4: Disable auto-refreshes, self-refresh, powerdown, and + * assertion of dfi_dram_clk_disable by setting RFSHCTL3.dis_auto_refresh = 1, + * PWRCTL.powerdown_en = 0, and PWRCTL.selfref_en = 0, + * PWRCTL.en_dfi_dram_clk_disable = 0 + */ + reg32_write(DDRC_DBG1(0), 0x00000000); + reg32_write(DDRC_RFSHCTL3(0), 0x0000001); + reg32_write(DDRC_PWRCTL(0), 0xa0); + + /* if ddr type is LPDDR4, do it */ + tmp = reg32_read(DDRC_MSTR(0)); + if (tmp & (0x1 << 5)) + reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */ + + /* determine the initial boot frequency */ + target_freq = reg32_read(DDRC_MSTR2(0)) & 0x3; + target_freq = (tmp & (0x1 << 29)) ? target_freq : 0x0; + + /* Step5: Set SWCT.sw_done to 0 */ + reg32_write(DDRC_SWCTL(0), 0x00000000); + + /* Set the default boot frequency point */ + clrsetbits_le32(DDRC_DFIMISC(0), (0x1f << 8), target_freq << 8); + /* Step6: Set DFIMISC.dfi_init_complete_en to 0 */ + clrbits_le32(DDRC_DFIMISC(0), 0x1); + + /* Step7: Set SWCTL.sw_done to 1; need to polling SWSTAT.sw_done_ack */ + reg32_write(DDRC_SWCTL(0), 0x00000001); + do { + tmp = reg32_read(DDRC_SWSTAT(0)); + } while ((tmp & 0x1) == 0x0); + + /* + * Step8 ~ Step13: Start PHY initialization and training by + * accessing relevant PUB registers + */ + debug("DDRINFO:ddrphy config start\n"); + + ret = ddr_cfg_phy(dram_timing); + if (ret) + return ret; + + debug("DDRINFO: ddrphy config done\n"); + + /* + * step14 CalBusy.0 =1, indicates the calibrator is actively + * calibrating. Wait Calibrating done. + */ + do { + tmp = reg32_read(DDRPHY_CalBusy(0)); + } while ((tmp & 0x1)); + + debug("DDRINFO:ddrphy calibration done\n"); + + /* Step15: Set SWCTL.sw_done to 0 */ + reg32_write(DDRC_SWCTL(0), 0x00000000); + + /* Step16: Set DFIMISC.dfi_init_start to 1 */ + setbits_le32(DDRC_DFIMISC(0), (0x1 << 5)); + + /* Step17: Set SWCTL.sw_done to 1; need to polling SWSTAT.sw_done_ack */ + reg32_write(DDRC_SWCTL(0), 0x00000001); + do { + tmp = reg32_read(DDRC_SWSTAT(0)); + } while ((tmp & 0x1) == 0x0); + + /* Step18: Polling DFISTAT.dfi_init_complete = 1 */ + do { + tmp = reg32_read(DDRC_DFISTAT(0)); + } while ((tmp & 0x1) == 0x0); + + /* Step19: Set SWCTL.sw_done to 0 */ + reg32_write(DDRC_SWCTL(0), 0x00000000); + + /* Step20: Set DFIMISC.dfi_init_start to 0 */ + clrbits_le32(DDRC_DFIMISC(0), (0x1 << 5)); + + /* Step21: optional */ + + /* Step22: Set DFIMISC.dfi_init_complete_en to 1 */ + setbits_le32(DDRC_DFIMISC(0), 0x1); + + /* Step23: Set PWRCTL.selfref_sw to 0 */ + clrbits_le32(DDRC_PWRCTL(0), (0x1 << 5)); + + /* Step24: Set SWCTL.sw_done to 1; need polling SWSTAT.sw_done_ack */ + reg32_write(DDRC_SWCTL(0), 0x00000001); + do { + tmp = reg32_read(DDRC_SWSTAT(0)); + } while ((tmp & 0x1) == 0x0); + + /* Step25: Wait for dwc_ddr_umctl2 to move to normal operating mode by monitoring + * STAT.operating_mode signal */ + do { + tmp = reg32_read(DDRC_STAT(0)); + } while ((tmp & 0x3) != 0x1); + + /* Step26: Set back register in Step4 to the original values if desired */ + reg32_write(DDRC_RFSHCTL3(0), 0x0000000); + /* enable selfref_en by default */ + setbits_le32(DDRC_PWRCTL(0), 0x1 << 3); + + /* enable port 0 */ + reg32_write(DDRC_PCTRL_0(0), 0x00000001); + debug("DDRINFO: ddrmix config done\n"); + + return 0; +} + +/* + * We store the timing parameters here. the TF-A will pick these up. + * Note that the timing used we leave the driver with is a PLL bypass 25MHz + * mode. So if your board runs horribly slow you'll likely have to provide a + * TF-A binary. + */ +#define IMX8M_SAVED_DRAM_TIMING_BASE 0x180000 + +int imx8mm_ddr_init(struct dram_timing_info *dram_timing) +{ + unsigned long src_ddrc_rcr = MX8M_SRC_DDRC_RCR_ADDR; + int ret; + + /* Step1: Follow the power up procedure */ + reg32_write(src_ddrc_rcr, 0x8f00001f); + reg32_write(src_ddrc_rcr, 0x8f00000f); + + ret = imx8m_ddr_init(src_ddrc_rcr, dram_timing); + if (ret) + return ret; + + /* save the dram timing config into memory */ + dram_config_save(dram_timing, IMX8M_SAVED_DRAM_TIMING_BASE); + + return 0; +} + +int imx8mq_ddr_init(struct dram_timing_info *dram_timing) +{ + unsigned long src_ddrc_rcr = MX8MQ_SRC_DDRC_RCR_ADDR; + int ret; + + /* Step1: Follow the power up procedure */ + reg32_write(src_ddrc_rcr + 0x04, 0x8f00000f); + reg32_write(src_ddrc_rcr, 0x8f00000f); + reg32_write(src_ddrc_rcr + 0x04, 0x8f000000); + + ret = imx8m_ddr_init(src_ddrc_rcr, dram_timing); + if (ret) + return ret; + + /* save the dram timing config into memory */ + dram_config_save(dram_timing, IMX8M_SAVED_DRAM_TIMING_BASE); + + return 0; +} diff --git a/drivers/ddr/imx8m/ddrphy_csr.c b/drivers/ddr/imx8m/ddrphy_csr.c new file mode 100644 index 0000000000..98ac5db3c0 --- /dev/null +++ b/drivers/ddr/imx8m/ddrphy_csr.c @@ -0,0 +1,732 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include +#include + +/* ddr phy trained csr */ +struct dram_cfg_param ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, 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0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; + +uint32_t ddrphy_trained_csr_num = ARRAY_SIZE(ddrphy_trained_csr); diff --git a/drivers/ddr/imx8m/ddrphy_train.c b/drivers/ddr/imx8m/ddrphy_train.c new file mode 100644 index 0000000000..c2238cc66b --- /dev/null +++ b/drivers/ddr/imx8m/ddrphy_train.c @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ +#define DEBUG +#include +#include +#include +#include +#include + +void ddr_load_train_code(enum fw_type type) +{ + const u16 *imem, *dmem; + size_t isize, dsize; + + if (type == FW_1D_IMAGE) { + get_builtin_firmware(lpddr4_pmu_train_1d_imem_bin, &imem, &isize); + get_builtin_firmware(lpddr4_pmu_train_1d_dmem_bin, &dmem, &dsize); + } else { + get_builtin_firmware(lpddr4_pmu_train_2d_imem_bin, &imem, &isize); + get_builtin_firmware(lpddr4_pmu_train_2d_dmem_bin, &dmem, &dsize); + } + + ddrc_phy_load_firmware(IOMEM(MX8M_DDRC_PHY_BASE_ADDR), + DDRC_PHY_IMEM, imem, isize); + + ddrc_phy_load_firmware(IOMEM(MX8M_DDRC_PHY_BASE_ADDR), + DDRC_PHY_DMEM, dmem, dsize); +} + +int ddr_cfg_phy(struct dram_timing_info *dram_timing) +{ + struct dram_cfg_param *dram_cfg; + struct dram_fsp_msg *fsp_msg; + unsigned int num; + int i = 0; + int j = 0; + int ret; + + /* initialize PHY configuration */ + dram_cfg = dram_timing->ddrphy_cfg; + num = dram_timing->ddrphy_cfg_num; + for (i = 0; i < num; i++) { + /* config phy reg */ + dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val); + dram_cfg++; + } + + /* load the frequency setpoint message block config */ + fsp_msg = dram_timing->fsp_msg; + for (i = 0; i < dram_timing->fsp_msg_num; i++) { + debug("DRAM PHY training for %dMTS\n", fsp_msg->drate); + /* set dram PHY input clocks to desired frequency */ + ddrphy_init_set_dfi_clk(fsp_msg->drate); + + /* load the dram training firmware image */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); + ddr_load_train_code(fsp_msg->fw_type); + + /* load the frequency set point message block parameter */ + dram_cfg = fsp_msg->fsp_cfg; + num = fsp_msg->fsp_cfg_num; + for (j = 0; j < num; j++) { + dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val); + dram_cfg++; + } + + /* + * -------------------- excute the firmware -------------------- + * Running the firmware is a simply process to taking the + * PMU out of reset and stall, then the firwmare will be run + * 1. reset the PMU; + * 2. begin the excution; + * 3. wait for the training done; + * 4. read the message block result. + * ------------------------------------------------------------- + */ + dwc_ddrphy_apb_wr(0xd0000, 0x1); + dwc_ddrphy_apb_wr(0xd0099, 0x9); + dwc_ddrphy_apb_wr(0xd0099, 0x1); + dwc_ddrphy_apb_wr(0xd0099, 0x0); + + /* Wait for the training firmware to complete */ + ret = wait_ddrphy_training_complete(); + if (ret) + return ret; + + /* Halt the microcontroller. */ + dwc_ddrphy_apb_wr(0xd0099, 0x1); + + /* Read the Message Block results */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); + ddrphy_init_read_msg_block(fsp_msg->fw_type); + dwc_ddrphy_apb_wr(0xd0000, 0x1); + + fsp_msg++; + } + + /* Load PHY Init Engine Image */ + dram_cfg = dram_timing->ddrphy_pie; + num = dram_timing->ddrphy_pie_num; + for (i = 0; i < num; i++) { + dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val); + dram_cfg++; + } + + /* save the ddr PHY trained CSR in memory for low power use */ + ddrphy_trained_csr_save(ddrphy_trained_csr, ddrphy_trained_csr_num); + + return 0; +} diff --git a/drivers/ddr/imx8m/ddrphy_utils.c b/drivers/ddr/imx8m/ddrphy_utils.c new file mode 100644 index 0000000000..651bb4b698 --- /dev/null +++ b/drivers/ddr/imx8m/ddrphy_utils.c @@ -0,0 +1,306 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* +* Copyright 2018 NXP +*/ + +#include +#include +#include +#include +#include +#include +#include + +void ddrc_phy_load_firmware(void __iomem *phy, + enum ddrc_phy_firmware_offset offset, + const u16 *blob, size_t size) +{ + while (size) { + writew(*blob++, phy + DDRC_PHY_REG(offset)); + offset++; + size -= sizeof(*blob); + } +} + +enum pmc_constants { + PMC_MESSAGE_ID, + PMC_MESSAGE_STREAM, + + PMC_TRAIN_SUCCESS = 0x07, + PMC_TRAIN_STREAM_START = 0x08, + PMC_TRAIN_FAIL = 0xff, +}; + +static u32 ddrc_phy_get_message(void __iomem *phy, int type) +{ + u32 r, message; + + /* + * When BIT0 set to 0, the PMU has a message for the user + * Wait for it indefinitely. + */ + readl_poll_timeout(phy + DDRC_PHY_REG(0xd0004), + r, !(r & BIT(0)), 0); + + switch (type) { + case PMC_MESSAGE_ID: + /* + * Get the major message ID + */ + message = readl(phy + DDRC_PHY_REG(0xd0032)); + break; + case PMC_MESSAGE_STREAM: + message = readl(phy + DDRC_PHY_REG(0xd0034)); + message <<= 16; + message |= readl(phy + DDRC_PHY_REG(0xd0032)); + break; + } + + /* + * By setting this register to 0, the user acknowledges the + * receipt of the message. + */ + writel(0x00000000, phy + DDRC_PHY_REG(0xd0031)); + /* + * When BIT0 set to 0, the PMU has a message for the user + */ + readl_poll_timeout(phy + DDRC_PHY_REG(0xd0004), + r, r & BIT(0), 0); + + writel(0x00000001, phy + DDRC_PHY_REG(0xd0031)); + + return message; +} + +static void ddrc_phy_fetch_streaming_message(void __iomem *phy) +{ + const u16 index = ddrc_phy_get_message(phy, PMC_MESSAGE_STREAM); + u16 i; + + for (i = 0; i < index; i++) + ddrc_phy_get_message(phy, PMC_MESSAGE_STREAM); +} + +int wait_ddrphy_training_complete(void) +{ + void __iomem *phy = IOMEM(MX8M_DDRC_PHY_BASE_ADDR); + + for (;;) { + const u32 m = ddrc_phy_get_message(phy, PMC_MESSAGE_ID); + + switch (m) { + case PMC_TRAIN_STREAM_START: + ddrc_phy_fetch_streaming_message(phy); + break; + case PMC_TRAIN_SUCCESS: + return 0; + case PMC_TRAIN_FAIL: + hang(); + } + } +} + +struct dram_bypass_clk_setting { + ulong clk; + int alt_root_sel; + int alt_pre_div; + int apb_root_sel; + int apb_pre_div; +}; + +#define MHZ(x) (1000000UL * (x)) + +static struct dram_bypass_clk_setting imx8mq_dram_bypass_tbl[] = { + { + .clk = MHZ(100), + .alt_root_sel = 2, + .alt_pre_div = 1 - 1, + .apb_root_sel = 2, + .apb_pre_div = 2 - 1, + } , { + .clk = MHZ(250), + .alt_root_sel = 3, + .alt_pre_div = 2 - 1, + .apb_root_sel = 2, + .apb_pre_div = 2 - 1, + }, { + .clk = MHZ(400), + .alt_root_sel = 1, + .alt_pre_div = 2 - 1, + .apb_root_sel = 3, + .apb_pre_div = 2 - 1, + }, +}; + +static void dram_enable_bypass(ulong clk_val) +{ + int i; + struct dram_bypass_clk_setting *config; + + for (i = 0; i < ARRAY_SIZE(imx8mq_dram_bypass_tbl); i++) { + if (clk_val == imx8mq_dram_bypass_tbl[i].clk) + break; + } + + if (i == ARRAY_SIZE(imx8mq_dram_bypass_tbl)) { + printf("No matched freq table %lu\n", clk_val); + return; + } + + config = &imx8mq_dram_bypass_tbl[i]; + + imx8m_clock_set_target_val(IMX8M_DRAM_ALT_CLK_ROOT, + IMX8M_CCM_TARGET_ROOTn_ENABLE | + IMX8M_CCM_TARGET_ROOTn_MUX(config->alt_root_sel) | + IMX8M_CCM_TARGET_ROOTn_PRE_DIV(config->alt_pre_div)); + imx8m_clock_set_target_val(IMX8M_DRAM_APB_CLK_ROOT, + IMX8M_CCM_TARGET_ROOTn_ENABLE | + IMX8M_CCM_TARGET_ROOTn_MUX(config->apb_root_sel) | + IMX8M_CCM_TARGET_ROOTn_PRE_DIV(config->apb_pre_div)); + imx8m_clock_set_target_val(IMX8M_DRAM_SEL_CFG, IMX8M_CCM_TARGET_ROOTn_ENABLE | + IMX8M_CCM_TARGET_ROOTn_MUX(1)); +} + +static void dram_disable_bypass(void) +{ + imx8m_clock_set_target_val(IMX8M_DRAM_SEL_CFG, + IMX8M_CCM_TARGET_ROOTn_ENABLE | + IMX8M_CCM_TARGET_ROOTn_MUX(0)); + imx8m_clock_set_target_val(IMX8M_DRAM_APB_CLK_ROOT, + IMX8M_CCM_TARGET_ROOTn_ENABLE | + IMX8M_CCM_TARGET_ROOTn_MUX(4) | + IMX8M_CCM_TARGET_ROOTn_PRE_DIV(5 - 1)); +} + +struct imx_int_pll_rate_table { + u32 rate; + u32 r1; + u32 r2; +}; + +#define MDIV(x) ((x) << 12) +#define PDIV(x) ((x) << 4) +#define SDIV(x) ((x) << 0) + +#define LOCK_STATUS BIT(31) +#define LOCK_SEL_MASK BIT(29) +#define CLKE_MASK BIT(11) +#define RST_MASK BIT(9) +#define BYPASS_MASK BIT(4) + +static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = { + { .rate = 1000000000U, .r1 = MDIV(250) | PDIV(3) | SDIV(1), .r2 = 0 }, + { .rate = 800000000U, .r1 = MDIV(300) | PDIV(9) | SDIV(0), .r2 = 0 }, + { .rate = 750000000U, .r1 = MDIV(250) | PDIV(8) | SDIV(0), .r2 = 0 }, + { .rate = 650000000U, .r1 = MDIV(325) | PDIV(3) | SDIV(2), .r2 = 0 }, + { .rate = 600000000U, .r1 = MDIV(300) | PDIV(3) | SDIV(2), .r2 = 0 }, + { .rate = 594000000U, .r1 = MDIV( 99) | PDIV(1) | SDIV(2), .r2 = 0 }, + { .rate = 400000000U, .r1 = MDIV(300) | PDIV(9) | SDIV(1), .r2 = 0 }, + { .rate = 266666667U, .r1 = MDIV(400) | PDIV(9) | SDIV(2), .r2 = 0 }, + { .rate = 167000000U, .r1 = MDIV(334) | PDIV(3) | SDIV(4), .r2 = 0 }, + { .rate = 100000000U, .r1 = MDIV(300) | PDIV(9) | SDIV(3), .r2 = 0 }, +}; + +static struct imx_int_pll_rate_table *fracpll(u32 freq) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(imx8mm_fracpll_tbl); i++) + if (freq == imx8mm_fracpll_tbl[i].rate) + return &imx8mm_fracpll_tbl[i]; + + return NULL; +} + +static int dram_pll_init(u32 freq) +{ + volatile int i; + u32 tmp; + void *pll_base; + struct imx_int_pll_rate_table *rate; + + rate = fracpll(freq); + if (!rate) { + printf("No matched freq table %u\n", freq); + return -EINVAL; + } + + setbits_le32(MX8M_GPC_BASE_ADDR + 0xec, 1 << 7); + setbits_le32(MX8M_GPC_BASE_ADDR + 0xf8, 1 << 5); + writel(0x8F000000UL, MX8M_SRC_BASE_ADDR + 0x1004); + + pll_base = IOMEM(MX8M_ANATOP_BASE_ADDR) + 0x50; + + /* Bypass clock and set lock to pll output lock */ + tmp = readl(pll_base); + tmp |= BYPASS_MASK; + writel(tmp, pll_base); + + /* Enable RST */ + tmp &= ~RST_MASK; + writel(tmp, pll_base); + + writel(rate->r1, pll_base + 4); + writel(rate->r2, pll_base + 8); + + for (i = 0; i < 1000; i++); + + /* Disable RST */ + tmp |= RST_MASK; + writel(tmp, pll_base); + + /* Wait Lock*/ + while (!(readl(pll_base) & LOCK_STATUS)); + + /* Bypass */ + tmp &= ~BYPASS_MASK; + writel(tmp, pll_base); + + return 0; +} + +void ddrphy_init_set_dfi_clk(unsigned int drate) +{ + switch (drate) { + case 4000: + dram_pll_init(MHZ(1000)); + dram_disable_bypass(); + break; + case 3200: + dram_pll_init(MHZ(800)); + dram_disable_bypass(); + break; + case 3000: + dram_pll_init(MHZ(750)); + dram_disable_bypass(); + break; + case 2400: + dram_pll_init(MHZ(600)); + dram_disable_bypass(); + break; + case 1600: + dram_pll_init(MHZ(400)); + dram_disable_bypass(); + break; + case 1066: + dram_pll_init(MHZ(266)); + dram_disable_bypass(); + break; + case 667: + dram_pll_init(MHZ(167)); + dram_disable_bypass(); + break; + case 400: + dram_enable_bypass(MHZ(400)); + break; + case 100: + dram_enable_bypass(MHZ(100)); + break; + default: + return; + } +} + +void ddrphy_init_read_msg_block(enum fw_type type) +{ +} diff --git a/drivers/ddr/imx8m/helper.c b/drivers/ddr/imx8m/helper.c new file mode 100644 index 0000000000..9e32ef9376 --- /dev/null +++ b/drivers/ddr/imx8m/helper.c @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include +#include +#include +#include + +#define IMEM_LEN 32768 /* byte */ +#define DMEM_LEN 16384 /* byte */ +#define IMEM_2D_OFFSET 49152 + +#define IMEM_OFFSET_ADDR 0x00050000 +#define DMEM_OFFSET_ADDR 0x00054000 +#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0) + +void ddrphy_trained_csr_save(struct dram_cfg_param *ddrphy_csr, + unsigned int num) +{ + int i = 0; + + /* enable the ddrphy apb */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); + dwc_ddrphy_apb_wr(0xc0080, 0x3); + for (i = 0; i < num; i++) { + ddrphy_csr->val = dwc_ddrphy_apb_rd(ddrphy_csr->reg); + ddrphy_csr++; + } + /* disable the ddrphy apb */ + dwc_ddrphy_apb_wr(0xc0080, 0x2); + dwc_ddrphy_apb_wr(0xd0000, 0x1); +} + +void dram_config_save(struct dram_timing_info *timing_info, + unsigned long saved_timing_base) +{ + int i = 0; + struct dram_timing_info *saved_timing = (void *)saved_timing_base; + struct dram_cfg_param *cfg; + + saved_timing->ddrc_cfg_num = timing_info->ddrc_cfg_num; + saved_timing->ddrphy_cfg_num = timing_info->ddrphy_cfg_num; + saved_timing->ddrphy_trained_csr_num = ddrphy_trained_csr_num; + saved_timing->ddrphy_pie_num = timing_info->ddrphy_pie_num; + + /* save the fsp table */ + for (i = 0; i < 4; i++) + saved_timing->fsp_table[i] = timing_info->fsp_table[i]; + + cfg = (struct dram_cfg_param *)(saved_timing_base + + sizeof(*timing_info)); + + /* save ddrc config */ + saved_timing->ddrc_cfg = cfg; + for (i = 0; i < timing_info->ddrc_cfg_num; i++) { + cfg->reg = timing_info->ddrc_cfg[i].reg; + cfg->val = timing_info->ddrc_cfg[i].val; + cfg++; + } + + /* save ddrphy config */ + saved_timing->ddrphy_cfg = cfg; + for (i = 0; i < timing_info->ddrphy_cfg_num; i++) { + cfg->reg = timing_info->ddrphy_cfg[i].reg; + cfg->val = timing_info->ddrphy_cfg[i].val; + cfg++; + } + + /* save the ddrphy csr */ + saved_timing->ddrphy_trained_csr = cfg; + for (i = 0; i < ddrphy_trained_csr_num; i++) { + cfg->reg = ddrphy_trained_csr[i].reg; + cfg->val = ddrphy_trained_csr[i].val; + cfg++; + } + + /* save the ddrphy pie */ + saved_timing->ddrphy_pie = cfg; + for (i = 0; i < timing_info->ddrphy_pie_num; i++) { + cfg->reg = timing_info->ddrphy_pie[i].reg; + cfg->val = timing_info->ddrphy_pie[i].val; + cfg++; + } +} diff --git a/include/soc/imx8m/ddr.h b/include/soc/imx8m/ddr.h new file mode 100644 index 0000000000..5b2747ed1f --- /dev/null +++ b/include/soc/imx8m/ddr.h @@ -0,0 +1,407 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017 NXP + */ + +#ifndef __ASM_ARCH_IMX8M_DDR_H +#define __ASM_ARCH_IMX8M_DDR_H + +#include +#include +#include + +#define DDRC_DDR_SS_GPR0 0x3d000000 +#define DDRC_IPS_BASE_ADDR_0 0x3f400000 +#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000)) +#define DDRPHY_MEM(X) (0x3c000000 + (X * 0x2000000) + 0x50000) + +#define DDRC_MSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x00) +#define DDRC_STAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x04) +#define DDRC_MSTR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x08) +#define DDRC_MRCTRL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x10) +#define DDRC_MRCTRL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x14) +#define DDRC_MRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18) +#define DDRC_MRCTRL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c) +#define DDRC_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x20) +#define DDRC_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x24) +#define DDRC_MSTR2(X) (DDRC_IPS_BASE_ADDR(X) + 0x28) +#define DDRC_PWRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x30) +#define DDRC_PWRTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x34) +#define DDRC_HWLPCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x38) +#define DDRC_HWFFCCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x3c) +#define DDRC_HWFFCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x40) +#define DDRC_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x50) +#define DDRC_RFSHCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x54) +#define DDRC_RFSHCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x58) +#define DDRC_RFSHCTL3(X) (DDRC_IPS_BASE_ADDR(X) + 0x60) +#define DDRC_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x64) +#define DDRC_ECCCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x70) +#define DDRC_ECCCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x74) +#define DDRC_ECCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x78) +#define DDRC_ECCCLR(X) (DDRC_IPS_BASE_ADDR(X) + 0x7c) +#define DDRC_ECCERRCNT(X) (DDRC_IPS_BASE_ADDR(X) + 0x80) +#define DDRC_ECCCADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0x84) +#define DDRC_ECCCADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x88) +#define DDRC_ECCCSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0x8c) +#define DDRC_ECCCSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0x90) +#define DDRC_ECCCSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0x94) +#define DDRC_ECCBITMASK0(X) (DDRC_IPS_BASE_ADDR(X) + 0x98) +#define DDRC_ECCBITMASK1(X) (DDRC_IPS_BASE_ADDR(X) + 0x9c) +#define DDRC_ECCBITMASK2(X) (DDRC_IPS_BASE_ADDR(X) + 0xa0) +#define DDRC_ECCUADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xa4) +#define DDRC_ECCUADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xa8) +#define DDRC_ECCUSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0xac) +#define DDRC_ECCUSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0xb0) +#define DDRC_ECCUSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0xb4) +#define DDRC_ECCPOISONADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xb8) +#define DDRC_ECCPOISONADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xbc) +#define DDRC_CRCPARCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0xc0) +#define DDRC_CRCPARCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0xc4) +#define DDRC_CRCPARCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0xc8) +#define DDRC_CRCPARSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xcc) +#define DDRC_INIT0(X) (DDRC_IPS_BASE_ADDR(X) + 0xd0) +#define DDRC_INIT1(X) (DDRC_IPS_BASE_ADDR(X) + 0xd4) +#define DDRC_INIT2(X) (DDRC_IPS_BASE_ADDR(X) + 0xd8) +#define DDRC_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0xdc) +#define DDRC_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0xe0) +#define DDRC_INIT5(X) (DDRC_IPS_BASE_ADDR(X) + 0xe4) +#define DDRC_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0xe8) +#define DDRC_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0xec) +#define DDRC_DIMMCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf0) +#define DDRC_RANKCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf4) +#define DDRC_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x100) +#define DDRC_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x104) +#define DDRC_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x108) +#define DDRC_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x10c) +#define DDRC_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x110) +#define DDRC_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x114) +#define DDRC_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x118) +#define DDRC_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x11c) +#define DDRC_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x120) +#define DDRC_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x124) +#define DDRC_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x128) +#define DDRC_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x12c) +#define DDRC_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x130) +#define DDRC_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x134) +#define DDRC_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x138) +#define DDRC_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x13C) +#define DDRC_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x140) +#define DDRC_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x144) +#define DDRC_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x180) +#define DDRC_ZQCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x184) +#define DDRC_ZQCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x188) +#define DDRC_ZQSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18c) +#define DDRC_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x190) +#define DDRC_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x194) +#define DDRC_DFILPCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x198) +#define DDRC_DFILPCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x19c) +#define DDRC_DFIUPD0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a0) +#define DDRC_DFIUPD1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a4) +#define DDRC_DFIUPD2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a8) +#define DDRC_DFIMISC(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b0) +#define DDRC_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b4) +#define DDRC_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b8) +#define DDRC_DFISTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1bc) +#define DDRC_DBICTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c0) +#define DDRC_DFIPHYMSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c4) +#define DDRC_TRAINCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d0) +#define DDRC_TRAINCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d4) +#define DDRC_TRAINCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d8) +#define DDRC_TRAINSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1dc) +#define DDRC_ADDRMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x200) +#define DDRC_ADDRMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x204) +#define DDRC_ADDRMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x208) +#define DDRC_ADDRMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20c) +#define DDRC_ADDRMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x210) +#define DDRC_ADDRMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x214) +#define DDRC_ADDRMAP6(X) (DDRC_IPS_BASE_ADDR(X) + 0x218) +#define DDRC_ADDRMAP7(X) (DDRC_IPS_BASE_ADDR(X) + 0x21c) +#define DDRC_ADDRMAP8(X) (DDRC_IPS_BASE_ADDR(X) + 0x220) +#define DDRC_ADDRMAP9(X) (DDRC_IPS_BASE_ADDR(X) + 0x224) +#define DDRC_ADDRMAP10(X) (DDRC_IPS_BASE_ADDR(X) + 0x228) +#define DDRC_ADDRMAP11(X) (DDRC_IPS_BASE_ADDR(X) + 0x22c) +#define DDRC_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x240) +#define DDRC_ODTMAP(X) (DDRC_IPS_BASE_ADDR(X) + 0x244) +#define DDRC_SCHED(X) (DDRC_IPS_BASE_ADDR(X) + 0x250) +#define DDRC_SCHED1(X) (DDRC_IPS_BASE_ADDR(X) + 0x254) +#define DDRC_PERFHPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x25c) +#define DDRC_PERFLPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x264) +#define DDRC_PERFWR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x26c) +#define DDRC_PERFVPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x274) +#define DDRC_PERFVPW1(X) (DDRC_IPS_BASE_ADDR(X) + 0x278) +#define DDRC_DQMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x280) +#define DDRC_DQMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x284) +#define DDRC_DQMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x288) +#define DDRC_DQMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x28c) +#define DDRC_DQMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x290) +#define DDRC_DQMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x294) +#define DDRC_DBG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x300) +#define DDRC_DBG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x304) +#define DDRC_DBGCAM(X) (DDRC_IPS_BASE_ADDR(X) + 0x308) +#define DDRC_DBGCMD(X) (DDRC_IPS_BASE_ADDR(X) + 0x30c) +#define DDRC_DBGSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x310) +#define DDRC_SWCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x320) +#define DDRC_SWSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x324) +#define DDRC_OCPARCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x330) +#define DDRC_OCPARCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x334) +#define DDRC_OCPARCFG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x338) +#define DDRC_OCPARCFG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x33c) +#define DDRC_OCPARSTAT0(X) (DDRC_IPS_BASE_ADDR(X) + 0x340) +#define DDRC_OCPARSTAT1(X) (DDRC_IPS_BASE_ADDR(X) + 0x344) +#define DDRC_OCPARWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x348) +#define DDRC_OCPARWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x34c) +#define DDRC_OCPARWLOG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x350) +#define DDRC_OCPARAWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x354) +#define DDRC_OCPARAWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x358) +#define DDRC_OCPARRLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x35c) +#define DDRC_OCPARRLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x360) +#define DDRC_OCPARARLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x364) +#define DDRC_OCPARARLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x368) +#define DDRC_POISONCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x36C) +#define DDRC_POISONSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x370) + +#define DDRC_PSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3fc) +#define DDRC_PCCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x400) +#define DDRC_PCFGR_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x404) +#define DDRC_PCFGR_1(X) (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x404) +#define DDRC_PCFGR_2(X) (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x404) +#define DDRC_PCFGR_3(X) (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x404) +#define DDRC_PCFGW_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x408) +#define DDRC_PCFGW_1(X) (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x408) +#define DDRC_PCFGW_2(X) (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x408) +#define DDRC_PCFGW_3(X) (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x408) +#define DDRC_PCFGC_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x40c) +#define DDRC_PCFGIDMASKCH(X) (DDRC_IPS_BASE_ADDR(X) + 0x410) +#define DDRC_PCFGIDVALUECH(X) (DDRC_IPS_BASE_ADDR(X) + 0x414) +#define DDRC_PCTRL_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x490) +#define DDRC_PCTRL_1(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 1 * 0xb0) +#define DDRC_PCTRL_2(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 2 * 0xb0) +#define DDRC_PCTRL_3(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 3 * 0xb0) +#define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494) +#define DDRC_PCFGQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x498) +#define DDRC_PCFGWQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x49c) +#define DDRC_PCFGWQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4a0) +#define DDRC_SARBASE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf04) +#define DDRC_SARSIZE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf08) +#define DDRC_SBRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf24) +#define DDRC_SBRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xf28) +#define DDRC_SBRWDATA0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf2c) +#define DDRC_SBRWDATA1(X) (DDRC_IPS_BASE_ADDR(X) + 0xf30) +#define DDRC_PDCH(X) (DDRC_IPS_BASE_ADDR(X) + 0xf34) + +#define DDRC_FREQ1_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x2020) +#define DDRC_FREQ1_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x2024) +#define DDRC_FREQ1_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2050) +#define DDRC_FREQ1_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2064) +#define DDRC_FREQ1_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20dc) +#define DDRC_FREQ1_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e0) +#define DDRC_FREQ1_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e8) +#define DDRC_FREQ1_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x20ec) +#define DDRC_FREQ1_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2100) +#define DDRC_FREQ1_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2104) +#define DDRC_FREQ1_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x2108) +#define DDRC_FREQ1_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x210c) +#define DDRC_FREQ1_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x2110) +#define DDRC_FREQ1_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x2114) +#define DDRC_FREQ1_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x2118) +#define DDRC_FREQ1_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x211c) +#define DDRC_FREQ1_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x2120) +#define DDRC_FREQ1_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x2124) +#define DDRC_FREQ1_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x2128) +#define DDRC_FREQ1_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x212c) +#define DDRC_FREQ1_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x2130) +#define DDRC_FREQ1_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x2134) +#define DDRC_FREQ1_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x2138) +#define DDRC_FREQ1_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x213C) +#define DDRC_FREQ1_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x2140) +#define DDRC_FREQ1_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x2144) +#define DDRC_FREQ1_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2180) +#define DDRC_FREQ1_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190) +#define DDRC_FREQ1_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194) +#define DDRC_FREQ1_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4) +#define DDRC_FREQ1_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8) +#define DDRC_FREQ1_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240) + +#define DDRC_FREQ2_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x3020) +#define DDRC_FREQ2_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3024) +#define DDRC_FREQ2_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3050) +#define DDRC_FREQ2_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3064) +#define DDRC_FREQ2_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x30dc) +#define DDRC_FREQ2_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e0) +#define DDRC_FREQ2_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e8) +#define DDRC_FREQ2_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x30ec) +#define DDRC_FREQ2_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3100) +#define DDRC_FREQ2_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3104) +#define DDRC_FREQ2_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x3108) +#define DDRC_FREQ2_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x310c) +#define DDRC_FREQ2_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x3110) +#define DDRC_FREQ2_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x3114) +#define DDRC_FREQ2_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x3118) +#define DDRC_FREQ2_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x311c) +#define DDRC_FREQ2_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x3120) +#define DDRC_FREQ2_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x3124) +#define DDRC_FREQ2_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x3128) +#define DDRC_FREQ2_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x312c) +#define DDRC_FREQ2_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x3130) +#define DDRC_FREQ2_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x3134) +#define DDRC_FREQ2_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x3138) +#define DDRC_FREQ2_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x313C) +#define DDRC_FREQ2_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x3140) +#define DDRC_FREQ2_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x3144) +#define DDRC_FREQ2_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3180) +#define DDRC_FREQ2_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3190) +#define DDRC_FREQ2_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3194) +#define DDRC_FREQ2_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b4) +#define DDRC_FREQ2_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b8) +#define DDRC_FREQ2_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3240) + +#define DDRC_FREQ3_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x4020) +#define DDRC_FREQ3_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x4024) +#define DDRC_FREQ3_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4050) +#define DDRC_FREQ3_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4064) +#define DDRC_FREQ3_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x40dc) +#define DDRC_FREQ3_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e0) +#define DDRC_FREQ3_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e8) +#define DDRC_FREQ3_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x40ec) +#define DDRC_FREQ3_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4100) +#define DDRC_FREQ3_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4104) +#define DDRC_FREQ3_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x4108) +#define DDRC_FREQ3_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x410c) +#define DDRC_FREQ3_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x4110) +#define DDRC_FREQ3_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x4114) +#define DDRC_FREQ3_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x4118) +#define DDRC_FREQ3_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x411c) +#define DDRC_FREQ3_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x4120) +#define DDRC_FREQ3_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x4124) +#define DDRC_FREQ3_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x4128) +#define DDRC_FREQ3_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x412c) +#define DDRC_FREQ3_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x4130) +#define DDRC_FREQ3_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x4134) +#define DDRC_FREQ3_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x4138) +#define DDRC_FREQ3_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x413C) +#define DDRC_FREQ3_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x4140) + +#define DDRC_FREQ3_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4180) +#define DDRC_FREQ3_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4190) +#define DDRC_FREQ3_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4194) +#define DDRC_FREQ3_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b4) +#define DDRC_FREQ3_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b8) +#define DDRC_FREQ3_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4240) +#define DDRC_DFITMG0_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190) +#define DDRC_DFITMG1_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194) +#define DDRC_DFITMG2_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4) +#define DDRC_DFITMG3_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8) +#define DDRC_ODTCFG_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240) + +#define DDRPHY_CalBusy(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4 * 0x020097) + +#define DRC_PERF_MON_BASE_ADDR(X) (0x3d800000 + ((X) * 0x2000000)) +#define DRC_PERF_MON_CNT0_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x0) +#define DRC_PERF_MON_CNT1_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x4) +#define DRC_PERF_MON_CNT2_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x8) +#define DRC_PERF_MON_CNT3_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0xC) +#define DRC_PERF_MON_CNT0_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x20) +#define DRC_PERF_MON_CNT1_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x24) +#define DRC_PERF_MON_CNT2_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x28) +#define DRC_PERF_MON_CNT3_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x2C) +#define DRC_PERF_MON_MRR0_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x40) +#define DRC_PERF_MON_MRR1_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x44) +#define DRC_PERF_MON_MRR2_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x48) +#define DRC_PERF_MON_MRR3_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x4C) +#define DRC_PERF_MON_MRR4_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x50) +#define DRC_PERF_MON_MRR5_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x54) +#define DRC_PERF_MON_MRR6_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x58) +#define DRC_PERF_MON_MRR7_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x5C) +#define DRC_PERF_MON_MRR8_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x60) +#define DRC_PERF_MON_MRR9_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x64) +#define DRC_PERF_MON_MRR10_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x68) +#define DRC_PERF_MON_MRR11_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x6C) +#define DRC_PERF_MON_MRR12_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x70) +#define DRC_PERF_MON_MRR13_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x74) +#define DRC_PERF_MON_MRR14_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x78) +#define DRC_PERF_MON_MRR15_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x7C) + +#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + (X * 0x2000000)) + +/* user data type */ +enum fw_type { + FW_1D_IMAGE, + FW_2D_IMAGE, +}; + +struct dram_cfg_param { + unsigned int reg; + unsigned int val; +}; + +struct dram_fsp_msg { + unsigned int drate; + enum fw_type fw_type; + struct dram_cfg_param *fsp_cfg; + unsigned int fsp_cfg_num; +}; + +struct dram_timing_info { + /* umctl2 config */ + struct dram_cfg_param *ddrc_cfg; + unsigned int ddrc_cfg_num; + /* ddrphy config */ + struct dram_cfg_param *ddrphy_cfg; + unsigned int ddrphy_cfg_num; + /* ddr fsp train info */ + struct dram_fsp_msg *fsp_msg; + unsigned int fsp_msg_num; + /* ddr phy trained CSR */ + struct dram_cfg_param *ddrphy_trained_csr; + unsigned int ddrphy_trained_csr_num; + /* ddr phy PIE */ + struct dram_cfg_param *ddrphy_pie; + unsigned int ddrphy_pie_num; + /* initialized drate table */ + unsigned int fsp_table[4]; +}; + +extern struct dram_timing_info dram_timing; + +int imx8mm_ddr_init(struct dram_timing_info *timing_info); +int imx8mq_ddr_init(struct dram_timing_info *timing_info); +int ddr_cfg_phy(struct dram_timing_info *timing_info); +void load_lpddr4_phy_pie(void); +void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num); +void dram_config_save(struct dram_timing_info *info, unsigned long base); + +/* utils function for ddr phy training */ +int wait_ddrphy_training_complete(void); +void ddrphy_init_set_dfi_clk(unsigned int drate); +void ddrphy_init_read_msg_block(enum fw_type type); + +#define reg32_write(a, v) writel(v, a) +#define reg32_read(a) readl(a) + +static inline void reg32setbit(unsigned long addr, u32 bit) +{ + setbits_le32(addr, (1 << bit)); +} + +#define dwc_ddrphy_apb_wr(addr, data) \ + reg32_write(IOMEM(IP2APB_DDRPHY_IPS_BASE_ADDR(0)) + 4 * (addr), data) +#define dwc_ddrphy_apb_rd(addr) \ + reg32_read(IOMEM(IP2APB_DDRPHY_IPS_BASE_ADDR(0)) + 4 * (addr)) + +extern struct dram_cfg_param ddrphy_trained_csr[]; +extern uint32_t ddrphy_trained_csr_num; + +enum ddrc_phy_firmware_offset { + DDRC_PHY_IMEM = 0x00050000U, + DDRC_PHY_DMEM = 0x00054000U, +}; + +void ddr_load_train_code(enum fw_type type); + +void ddrc_phy_load_firmware(void __iomem *, + enum ddrc_phy_firmware_offset, + const u16 *, size_t); + +#define DDRC_PHY_REG(x) ((x) * 4) + +#endif diff --git a/include/soc/imx8m/lpddr4_define.h b/include/soc/imx8m/lpddr4_define.h new file mode 100644 index 0000000000..caf5bafb6d --- /dev/null +++ b/include/soc/imx8m/lpddr4_define.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __LPDDR4_DEFINE_H_ +#define __LPDDR4_DEFINE_H_ + +#define LPDDR4_DVFS_DBI +#define DDR_ONE_RANK +/* #define LPDDR4_DBI_ON */ +#define DFI_BUG_WR +#define M845S_4GBx2 +#define PRETRAIN + +/* DRAM MR setting */ +#ifdef LPDDR4_DBI_ON +#define LPDDR4_MR3 0xf1 +#define LPDDR4_PHY_DMIPinPresent 0x1 +#else +#define LPDDR4_MR3 0x31 +#define LPDDR4_PHY_DMIPinPresent 0x0 +#endif + +#ifdef DDR_ONE_RANK +#define LPDDR4_CS 0x1 +#else +#define LPDDR4_CS 0x3 +#endif + +/* PHY training feature */ +#define LPDDR4_HDT_CTL_2D 0xC8 +#define LPDDR4_HDT_CTL_3200_1D 0xC8 +#define LPDDR4_HDT_CTL_400_1D 0xC8 +#define LPDDR4_HDT_CTL_100_1D 0xC8 + +/* 400/100 training seq */ +#define LPDDR4_TRAIN_SEQ_P2 0x121f +#define LPDDR4_TRAIN_SEQ_P1 0x121f +#define LPDDR4_TRAIN_SEQ_P0 0x121f +#define LPDDR4_TRAIN_SEQ_100 0x121f +#define LPDDR4_TRAIN_SEQ_400 0x121f + +/* 2D share & weight */ +#define LPDDR4_2D_WEIGHT 0x1f7f +#define LPDDR4_2D_SHARE 1 +#define LPDDR4_CATRAIN_3200_1d 0 +#define LPDDR4_CATRAIN_400 0 +#define LPDDR4_CATRAIN_100 0 +#define LPDDR4_CATRAIN_3200_2d 0 + +/* MRS parameter */ +/* for LPDDR4 Rtt */ +#define LPDDR4_RTT40 6 +#define LPDDR4_RTT48 5 +#define LPDDR4_RTT60 4 +#define LPDDR4_RTT80 3 +#define LPDDR4_RTT120 2 +#define LPDDR4_RTT240 1 +#define LPDDR4_RTT_DIS 0 + +/* for LPDDR4 Ron */ +#define LPDDR4_RON34 7 +#define LPDDR4_RON40 6 +#define LPDDR4_RON48 5 +#define LPDDR4_RON60 4 +#define LPDDR4_RON80 3 + +#define LPDDR4_PHY_ADDR_RON60 0x1 +#define LPDDR4_PHY_ADDR_RON40 0x3 +#define LPDDR4_PHY_ADDR_RON30 0x7 +#define LPDDR4_PHY_ADDR_RON24 0xf +#define LPDDR4_PHY_ADDR_RON20 0x1f + +/* for read channel */ +#define LPDDR4_RON LPDDR4_RON40 +#define LPDDR4_PHY_RTT 30 +#define LPDDR4_PHY_VREF_VALUE 17 + +/* for write channel */ +#define LPDDR4_PHY_RON 30 +#define LPDDR4_PHY_ADDR_RON LPDDR4_PHY_ADDR_RON40 +#define LPDDR4_RTT_DQ LPDDR4_RTT40 +#define LPDDR4_RTT_CA LPDDR4_RTT40 +#define LPDDR4_RTT_CA_BANK0 LPDDR4_RTT40 +#define LPDDR4_RTT_CA_BANK1 LPDDR4_RTT40 +#define LPDDR4_VREF_VALUE_CA ((1 << 6) | (0xd)) +#define LPDDR4_VREF_VALUE_DQ_RANK0 ((1 << 6) | (0xd)) +#define LPDDR4_VREF_VALUE_DQ_RANK1 ((1 << 6) | (0xd)) +#define LPDDR4_MR22_RANK0 ((0 << 5) | (1 << 4) | (0 << 3) | \ + (LPDDR4_RTT40)) +#define LPDDR4_MR22_RANK1 ((1 << 5) | (1 << 4) | (1 << 3) | \ + (LPDDR4_RTT40)) + +#define LPDDR4_MR3_PU_CAL 1 + +#endif /* __LPDDR4_DEFINE_H__ */ -- cgit v1.2.3 From 783777153fb69c15a91a9e7d4e77c44d70ea0480 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 12 Feb 2020 13:04:03 +0100 Subject: ARM: i.MX8M: Add TF-A loading support for i.MX8MM Basically the same as for i.MX8MQ, just some function split up needed to account for different base addresses for the TF-A on both SoCs. Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/Makefile | 2 +- arch/arm/mach-imx/atf.c | 26 +++++++++++++++++++------- arch/arm/mach-imx/include/mach/atf.h | 9 +++++++-- firmware/Kconfig | 3 +++ firmware/Makefile | 1 + 5 files changed, 31 insertions(+), 10 deletions(-) (limited to 'arch/arm/mach-imx/include') diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 105785ba1b..30ced0e202 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -16,7 +16,7 @@ lwl-$(CONFIG_ARCH_IMX6) += imx6-mmdc.o obj-$(CONFIG_ARCH_IMX7) += imx7.o obj-$(CONFIG_ARCH_VF610) += vf610.o obj-$(CONFIG_ARCH_IMX8M) += imx8m.o -lwl-$(CONFIG_ARCH_IMX8MQ) += atf.o +lwl-$(CONFIG_ARCH_IMX8M) += atf.o obj-$(CONFIG_IMX_IIM) += iim.o obj-$(CONFIG_NAND_IMX) += nand.o lwl-$(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND) += external-nand-boot.o diff --git a/arch/arm/mach-imx/atf.c b/arch/arm/mach-imx/atf.c index c1b358d125..4ced8cd083 100644 --- a/arch/arm/mach-imx/atf.c +++ b/arch/arm/mach-imx/atf.c @@ -2,13 +2,14 @@ #include /** - * imx8mq_atf_load_bl31 - Load ATF BL31 blob and transfer control to it + * imx8m_atf_load_bl31 - Load ATF BL31 blob and transfer control to it * * @fw: Pointer to the BL31 blob * @fw_size: Size of the BL31 blob + * @atf_dest: Place where the BL31 is copied to and executed * * This function: - + * * 1. Copies built-in BL31 blob to an address i.MX8M's BL31 * expects to be placed * @@ -25,17 +26,28 @@ * any other implementation may or may not work * */ -void imx8mq_atf_load_bl31(const void *fw, size_t fw_size) + +static void imx8m_atf_load_bl31(const void *fw, size_t fw_size, void *atf_dest) { - void __noreturn (*bl31)(void) = (void *)MX8MQ_ATF_BL31_BASE_ADDR; + void __noreturn (*bl31)(void) = atf_dest; - if (WARN_ON(fw_size > MX8MQ_ATF_BL31_SIZE_LIMIT)) + if (WARN_ON(fw_size > MX8M_ATF_BL31_SIZE_LIMIT)) return; memcpy(bl31, fw, fw_size); asm volatile("msr sp_el2, %0" : : - "r" (MX8MQ_ATF_BL33_BASE_ADDR - 16) : + "r" (atf_dest - 16) : "cc"); bl31(); -} \ No newline at end of file +} + +void imx8mm_atf_load_bl31(const void *fw, size_t fw_size) +{ + imx8m_atf_load_bl31(fw, fw_size, (void *)MX8MM_ATF_BL31_BASE_ADDR); +} + +void imx8mq_atf_load_bl31(const void *fw, size_t fw_size) +{ + imx8m_atf_load_bl31(fw, fw_size, (void *)MX8MQ_ATF_BL31_BASE_ADDR); +} diff --git a/arch/arm/mach-imx/include/mach/atf.h b/arch/arm/mach-imx/include/mach/atf.h index aeb24bad00..f64a9dd2ba 100644 --- a/arch/arm/mach-imx/include/mach/atf.h +++ b/arch/arm/mach-imx/include/mach/atf.h @@ -4,10 +4,15 @@ #include #include -#define MX8MQ_ATF_BL31_SIZE_LIMIT SZ_64K +#define MX8M_ATF_BL31_SIZE_LIMIT SZ_64K + +#define MX8MM_ATF_BL31_BASE_ADDR 0x00920000 #define MX8MQ_ATF_BL31_BASE_ADDR 0x00910000 -#define MX8MQ_ATF_BL33_BASE_ADDR 0x40200000 +#define MX8M_ATF_BL33_BASE_ADDR 0x40200000 +#define MX8MM_ATF_BL33_BASE_ADDR MX8M_ATF_BL33_BASE_ADDR +#define MX8MQ_ATF_BL33_BASE_ADDR MX8M_ATF_BL33_BASE_ADDR +void imx8mm_atf_load_bl31(const void *fw, size_t fw_size); void imx8mq_atf_load_bl31(const void *fw, size_t fw_size); #endif \ No newline at end of file diff --git a/firmware/Kconfig b/firmware/Kconfig index a6f79e8a97..169c6ee915 100644 --- a/firmware/Kconfig +++ b/firmware/Kconfig @@ -7,6 +7,9 @@ config EXTRA_FIRMWARE_DIR config FIRMWARE_IMX_LPDDR4_PMU_TRAIN bool +config FIRMWARE_IMX8MM_ATF + bool + config FIRMWARE_IMX8MQ_ATF bool diff --git a/firmware/Makefile b/firmware/Makefile index 9581ee6116..a0f40d3f4e 100644 --- a/firmware/Makefile +++ b/firmware/Makefile @@ -9,6 +9,7 @@ firmware-$(CONFIG_FIRMWARE_IMX_LPDDR4_PMU_TRAIN) += \ lpddr4_pmu_train_2d_dmem.bin \ lpddr4_pmu_train_2d_imem.bin +firmware-$(CONFIG_FIRMWARE_IMX8MM_ATF) += imx8mm-bl31.bin firmware-$(CONFIG_FIRMWARE_IMX8MQ_ATF) += imx8mq-bl31.bin firmware-$(CONFIG_DRIVER_NET_FSL_FMAN) += fsl_fman_ucode_ls1046_r1.0_106_4_18.bin -- cgit v1.2.3 From 61a0d63c755dae9c31e0cc0e5a5cb9a885fa6141 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 14 Feb 2020 12:10:14 +0100 Subject: ARM: i.MX8M: Add i.MX8MM support This adds support for the i.MX8MM. Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/Kconfig | 4 + arch/arm/mach-imx/Makefile | 2 +- arch/arm/mach-imx/boot.c | 19 ++- arch/arm/mach-imx/cpu_init.c | 14 ++- arch/arm/mach-imx/esdctl.c | 5 + arch/arm/mach-imx/imx-bbu-internal.c | 4 +- arch/arm/mach-imx/imx.c | 4 + arch/arm/mach-imx/imx8m.c | 154 +++++++++++++++++++++--- arch/arm/mach-imx/include/mach/esdctl.h | 1 + arch/arm/mach-imx/include/mach/generic.h | 18 +++ arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h | 1 + arch/arm/mach-imx/include/mach/imx8mq.h | 13 +- arch/arm/mach-imx/include/mach/imx_cpu_types.h | 1 + 13 files changed, 215 insertions(+), 25 deletions(-) (limited to 'arch/arm/mach-imx/include') diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 7b79d80748..9dad4ceae2 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -186,6 +186,10 @@ config ARCH_IMX8M select IMX8M_DRAM select PBL_VERIFY_PIGGY if HABV4 +config ARCH_IMX8MM + select ARCH_IMX8M + bool + config ARCH_IMX8MQ select ARCH_IMX8M bool diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 30ced0e202..e45f758e9c 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -15,7 +15,7 @@ CFLAGS_imx6.o := -march=armv7-a lwl-$(CONFIG_ARCH_IMX6) += imx6-mmdc.o obj-$(CONFIG_ARCH_IMX7) += imx7.o obj-$(CONFIG_ARCH_VF610) += vf610.o -obj-$(CONFIG_ARCH_IMX8M) += imx8m.o +obj-pbl-$(CONFIG_ARCH_IMX8M) += imx8m.o lwl-$(CONFIG_ARCH_IMX8M) += atf.o obj-$(CONFIG_IMX_IIM) += iim.o obj-$(CONFIG_NAND_IMX) += nand.o diff --git a/arch/arm/mach-imx/boot.c b/arch/arm/mach-imx/boot.c index 7d1af106d1..7bce1c710c 100644 --- a/arch/arm/mach-imx/boot.c +++ b/arch/arm/mach-imx/boot.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -593,7 +594,7 @@ void vf610_boot_save_loc(void) void imx8mq_get_boot_source(enum bootsource *src, int *instance) { unsigned long addr; - void __iomem *src_base = IOMEM(MX8MQ_SRC_BASE_ADDR); + void __iomem *src_base = IOMEM(MX8M_SRC_BASE_ADDR); uint32_t sbmr2 = readl(src_base + 0x70); addr = (imx8mq_cpu_revision() == IMX_CHIP_REV_1_0) ? @@ -607,3 +608,19 @@ void imx8mq_boot_save_loc(void) { imx_boot_save_loc(imx8mq_get_boot_source); } + +void imx8mm_get_boot_source(enum bootsource *src, int *instance) +{ + unsigned long addr; + void __iomem *src_base = IOMEM(MX8MM_SRC_BASE_ADDR); + uint32_t sbmr2 = readl(src_base + 0x70); + + addr = IMX8M_BOOT_SW_INFO_POINTER_ADDR_A0; + + __imx7_get_boot_source(src, instance, addr, sbmr2); +} + +void imx8mm_boot_save_loc(void) +{ + imx_boot_save_loc(imx8mm_get_boot_source); +} diff --git a/arch/arm/mach-imx/cpu_init.c b/arch/arm/mach-imx/cpu_init.c index aa6e050e94..c6a0ac7c50 100644 --- a/arch/arm/mach-imx/cpu_init.c +++ b/arch/arm/mach-imx/cpu_init.c @@ -69,11 +69,21 @@ void vf610_cpu_lowlevel_init(void) arm_cpu_lowlevel_init(); } #else -void imx8mq_cpu_lowlevel_init(void) +static void imx8m_cpu_lowlevel_init(void) { arm_cpu_lowlevel_init(); if (current_el() == 3) - imx_cpu_timer_init(IOMEM(MX8MQ_SYSCNT_CTRL_BASE_ADDR)); + imx_cpu_timer_init(IOMEM(MX8M_SYSCNT_CTRL_BASE_ADDR)); +} + +void imx8mm_cpu_lowlevel_init(void) +{ + imx8m_cpu_lowlevel_init(); +} + +void imx8mq_cpu_lowlevel_init(void) +{ + imx8m_cpu_lowlevel_init(); } #endif diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c index 411836debd..25e7c83ad9 100644 --- a/arch/arm/mach-imx/esdctl.c +++ b/arch/arm/mach-imx/esdctl.c @@ -887,6 +887,11 @@ static void __noreturn imx8m_barebox_entry(void *boarddata) barebox_arm_entry(MX8M_DDR_CSD1_BASE_ADDR, size, boarddata); } +void __noreturn imx8mm_barebox_entry(void *boarddata) +{ + imx8m_barebox_entry(boarddata); +} + void __noreturn imx8mq_barebox_entry(void *boarddata) { imx8m_barebox_entry(boarddata); diff --git a/arch/arm/mach-imx/imx-bbu-internal.c b/arch/arm/mach-imx/imx-bbu-internal.c index 946a3e9a77..f6f66364c0 100644 --- a/arch/arm/mach-imx/imx-bbu-internal.c +++ b/arch/arm/mach-imx/imx-bbu-internal.c @@ -375,7 +375,7 @@ out: static enum filetype imx_bbu_expected_filetype(void) { - if (cpu_is_mx8mq() || + if (cpu_is_mx8m() || cpu_is_mx7() || cpu_is_mx6() || cpu_is_vf610() || @@ -393,7 +393,7 @@ static unsigned long imx_bbu_flash_header_offset_mmc(void) * i.MX8MQ moved the header by 32K to accomodate for GPT * partition tables */ - if (cpu_is_mx8mq()) + if (cpu_is_mx8m()) offset += SZ_32K; return offset; diff --git a/arch/arm/mach-imx/imx.c b/arch/arm/mach-imx/imx.c index 0942d50695..ca2e77befe 100644 --- a/arch/arm/mach-imx/imx.c +++ b/arch/arm/mach-imx/imx.c @@ -80,6 +80,8 @@ static int imx_soc_from_dt(void) return IMX_CPU_IMX7; if (of_machine_is_compatible("fsl,imx8mq")) return IMX_CPU_IMX8MQ; + if (of_machine_is_compatible("fsl,imx8mm")) + return IMX_CPU_IMX8MM; if (of_machine_is_compatible("fsl,vf610")) return IMX_CPU_VF610; @@ -120,6 +122,8 @@ static int imx_init(void) ret = imx6_init(); else if (cpu_is_mx7()) ret = imx7_init(); + else if (cpu_is_mx8mm()) + ret = imx8mm_init(); else if (cpu_is_mx8mq()) ret = imx8mq_init(); else if (cpu_is_vf610()) diff --git a/arch/arm/mach-imx/imx8m.c b/arch/arm/mach-imx/imx8m.c index d044531520..d2ed7d52a9 100644 --- a/arch/arm/mach-imx/imx8m.c +++ b/arch/arm/mach-imx/imx8m.c @@ -22,6 +22,9 @@ #include #include #include +#include +#include +#include #include #include @@ -52,18 +55,61 @@ void imx8m_ccgr_clock_disable(int index) ccm + IMX8M_CCM_CCGRn_CLR(index)); } -u64 imx8mq_uid(void) +u64 imx8m_uid(void) { - return imx_ocotp_read_uid(IOMEM(MX8MQ_OCOTP_BASE_ADDR)); + return imx_ocotp_read_uid(IOMEM(MX8M_OCOTP_BASE_ADDR)); +} + +static int imx8m_init(const char *cputypestr) +{ + void __iomem *src = IOMEM(MX8M_SRC_BASE_ADDR); + struct arm_smccc_res res; + + /* + * Reset reasons seem to be identical to that of i.MX7 + */ + imx_set_reset_reason(src + IMX7_SRC_SRSR, imx7_reset_reasons); + pr_info("%s unique ID: %llx\n", cputypestr, imx8m_uid()); + + if (IS_ENABLED(CONFIG_ARM_SMCCC) && + IS_ENABLED(CONFIG_FIRMWARE_IMX8MQ_ATF)) { + arm_smccc_smc(FSL_SIP_BUILDINFO, + FSL_SIP_BUILDINFO_GET_COMMITHASH, + 0, 0, 0, 0, 0, 0, &res); + pr_info("i.MX ARM Trusted Firmware: %s\n", (char *)&res.a0); + } + + return 0; +} + +int imx8mm_init(void) +{ + void __iomem *anatop = IOMEM(MX8M_ANATOP_BASE_ADDR); + uint32_t type = FIELD_GET(DIGPROG_MAJOR, + readl(anatop + MX8MM_ANATOP_DIGPROG)); + const char *cputypestr; + + imx8mm_boot_save_loc(); + + switch (type) { + case IMX8M_CPUTYPE_IMX8MM: + cputypestr = "i.MX8MM"; + break; + default: + cputypestr = "unknown i.MX8M"; + break; + }; + + imx_set_silicon_revision(cputypestr, imx8mm_cpu_revision()); + + return imx8m_init(cputypestr); } int imx8mq_init(void) { - void __iomem *anatop = IOMEM(MX8MQ_ANATOP_BASE_ADDR); - void __iomem *src = IOMEM(MX8MQ_SRC_BASE_ADDR); + void __iomem *anatop = IOMEM(MX8M_ANATOP_BASE_ADDR); uint32_t type = FIELD_GET(DIGPROG_MAJOR, readl(anatop + MX8MQ_ANATOP_DIGPROG)); - struct arm_smccc_res res; const char *cputypestr; imx8mq_boot_save_loc(); @@ -78,21 +124,93 @@ int imx8mq_init(void) }; imx_set_silicon_revision(cputypestr, imx8mq_cpu_revision()); - /* - * Reset reasons seem to be identical to that of i.MX7 - */ - imx_set_reset_reason(src + IMX7_SRC_SRSR, imx7_reset_reasons); - pr_info("%s unique ID: %llx\n", cputypestr, imx8mq_uid()); - if (IS_ENABLED(CONFIG_ARM_SMCCC) && - IS_ENABLED(CONFIG_FIRMWARE_IMX8MQ_ATF)) { - arm_smccc_smc(FSL_SIP_BUILDINFO, - FSL_SIP_BUILDINFO_GET_COMMITHASH, - 0, 0, 0, 0, 0, 0, &res); - pr_info("i.MX ARM Trusted Firmware: %s\n", (char *)&res.a0); - } + return imx8m_init(cputypestr); +} - return 0; +#define INTPLL_DIV20_CLKE_MASK BIT(27) +#define INTPLL_DIV10_CLKE_MASK BIT(25) +#define INTPLL_DIV8_CLKE_MASK BIT(23) +#define INTPLL_DIV6_CLKE_MASK BIT(21) +#define INTPLL_DIV5_CLKE_MASK BIT(19) +#define INTPLL_DIV4_CLKE_MASK BIT(17) +#define INTPLL_DIV3_CLKE_MASK BIT(15) +#define INTPLL_DIV2_CLKE_MASK BIT(13) +#define INTPLL_CLKE_MASK BIT(11) + +#define CCM_TARGET_ROOT0_DIV GENMASK(1, 0) + +#define IMX8MM_CCM_ANALOG_ARM_PLL_GEN_CTRL 0x84 +#define IMX8MM_CCM_ANALOG_SYS_PLL1_GEN_CTRL 0x94 +#define IMX8MM_CCM_ANALOG_SYS_PLL2_GEN_CTRL 0x104 +#define IMX8MM_CCM_ANALOG_SYS_PLL3_GEN_CTRL 0x114 + +void imx8mm_early_clock_init(void) +{ + void __iomem *ana = IOMEM(MX8M_ANATOP_BASE_ADDR); + void __iomem *ccm = IOMEM(MX8M_CCM_BASE_ADDR); + u32 val; + + imx8m_ccgr_clock_disable(IMX8M_CCM_CCGR_DDR1); + + imx8m_clock_set_target_val(IMX8M_DRAM_ALT_CLK_ROOT, + IMX8M_CCM_TARGET_ROOTn_ENABLE | + IMX8M_CCM_TARGET_ROOTn_MUX(1)); + + /* change the clock source of dram_apb_clk_root: source 4 800MHz /4 = 200MHz */ + imx8m_clock_set_target_val(IMX8M_DRAM_APB_CLK_ROOT, + IMX8M_CCM_TARGET_ROOTn_ENABLE | + IMX8M_CCM_TARGET_ROOTn_MUX(4) | + IMX8M_CCM_TARGET_ROOTn_POST_DIV(4 - 1)); + + imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_DDR1); + + val = readl(ana + IMX8MM_CCM_ANALOG_SYS_PLL1_GEN_CTRL); + val |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | + INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK | + INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK | + INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK | + INTPLL_DIV20_CLKE_MASK; + writel(val, ana + IMX8MM_CCM_ANALOG_SYS_PLL1_GEN_CTRL); + + val = readl(ana + IMX8MM_CCM_ANALOG_SYS_PLL2_GEN_CTRL); + val |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | + INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK | + INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK | + INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK | + INTPLL_DIV20_CLKE_MASK; + writel(val, ana + IMX8MM_CCM_ANALOG_SYS_PLL2_GEN_CTRL); + + /* config GIC to sys_pll2_100m */ + imx8m_ccgr_clock_disable(IMX8M_CCM_CCGR_GIC); + imx8m_clock_set_target_val(IMX8M_GIC_CLK_ROOT, + IMX8M_CCM_TARGET_ROOTn_ENABLE | + IMX8M_CCM_TARGET_ROOTn_MUX(3)); + imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_GIC); + + /* Configure SYS_PLL3 to 750MHz */ + clk_pll1416x_early_set_rate(ana + IMX8MM_CCM_ANALOG_SYS_PLL3_GEN_CTRL, + 750000000UL, 25000000UL); + + clrsetbits_le32(ccm + IMX8M_CCM_TARGET_ROOTn(IMX8M_ARM_A53_CLK_ROOT), + IMX8M_CCM_TARGET_ROOTn_MUX(7), + IMX8M_CCM_TARGET_ROOTn_MUX(2)); + + /* Configure ARM PLL to 1.2GHz */ + clk_pll1416x_early_set_rate(ana + IMX8MM_CCM_ANALOG_ARM_PLL_GEN_CTRL, + 1200000000UL, 25000000UL); + + clrsetbits_le32(ana + IMX8MM_CCM_ANALOG_ARM_PLL_GEN_CTRL, 0, + INTPLL_CLKE_MASK); + + clrsetbits_le32(ccm + IMX8M_CCM_TARGET_ROOTn(IMX8M_ARM_A53_CLK_ROOT), + IMX8M_CCM_TARGET_ROOTn_MUX(7), + IMX8M_CCM_TARGET_ROOTn_MUX(1)); + + /* Configure DIV to 1.2GHz */ + clrsetbits_le32(ccm + IMX8M_CCM_TARGET_ROOTn(IMX8M_ARM_A53_CLK_ROOT), + CCM_TARGET_ROOT0_DIV, + FIELD_PREP(CCM_TARGET_ROOT0_DIV, 0)); } #define KEEP_ALIVE 0x18 diff --git a/arch/arm/mach-imx/include/mach/esdctl.h b/arch/arm/mach-imx/include/mach/esdctl.h index 18c4a28360..41eb9f6729 100644 --- a/arch/arm/mach-imx/include/mach/esdctl.h +++ b/arch/arm/mach-imx/include/mach/esdctl.h @@ -139,6 +139,7 @@ void __noreturn imx53_barebox_entry(void *boarddata); void __noreturn imx6q_barebox_entry(void *boarddata); void __noreturn imx6ul_barebox_entry(void *boarddata); void __noreturn vf610_barebox_entry(void *boarddata); +void __noreturn imx8mm_barebox_entry(void *boarddata); void __noreturn imx8mq_barebox_entry(void *boarddata); void __noreturn imx7d_barebox_entry(void *boarddata); #define imx6sx_barebox_entry(boarddata) imx6ul_barebox_entry(boarddata) diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h index 3666fd4f8b..7742a002ce 100644 --- a/arch/arm/mach-imx/include/mach/generic.h +++ b/arch/arm/mach-imx/include/mach/generic.h @@ -16,6 +16,7 @@ void imx53_boot_save_loc(void); void imx6_boot_save_loc(void); void imx7_boot_save_loc(void); void vf610_boot_save_loc(void); +void imx8mm_boot_save_loc(void); void imx8mq_boot_save_loc(void); void imx25_get_boot_source(enum bootsource *src, int *instance); @@ -26,6 +27,7 @@ void imx53_get_boot_source(enum bootsource *src, int *instance); void imx6_get_boot_source(enum bootsource *src, int *instance); void imx7_get_boot_source(enum bootsource *src, int *instance); void vf610_get_boot_source(enum bootsource *src, int *instance); +void imx8mm_get_boot_source(enum bootsource *src, int *instance); void imx8mq_get_boot_source(enum bootsource *src, int *instance); int imx1_init(void); @@ -40,6 +42,7 @@ int imx53_init(void); int imx6_init(void); int imx7_init(void); int vf610_init(void); +int imx8mm_init(void); int imx8mq_init(void); int imx1_devices_init(void); @@ -59,6 +62,7 @@ void imx6ul_cpu_lowlevel_init(void); void imx7_cpu_lowlevel_init(void); void vf610_cpu_lowlevel_init(void); void imx8mq_cpu_lowlevel_init(void); +void imx8mm_cpu_lowlevel_init(void); /* There's a off-by-one betweem the gpio bank number and the gpiochip */ /* range e.g. GPIO_1_5 is gpio 5 under linux */ @@ -199,6 +203,18 @@ extern unsigned int __imx_cpu_type; # define cpu_is_mx7() (0) #endif +#ifdef CONFIG_ARCH_IMX8MM +# ifdef imx_cpu_type +# undef imx_cpu_type +# define imx_cpu_type __imx_cpu_type +# else +# define imx_cpu_type IMX_CPU_IMX8MM +# endif +# define cpu_is_mx8mm() (imx_cpu_type == IMX_CPU_IMX8MM) +#else +# define cpu_is_mx8mm() (0) +#endif + #ifdef CONFIG_ARCH_IMX8MQ # ifdef imx_cpu_type # undef imx_cpu_type @@ -235,4 +251,6 @@ extern unsigned int __imx_cpu_type; #define cpu_is_mx23() (0) #define cpu_is_mx28() (0) +#define cpu_is_mx8m() (cpu_is_mx8mq() || cpu_is_mx8mm()) + #endif /* __MACH_GENERIC_H */ diff --git a/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h b/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h index 70a7e4af9d..743ed6cda0 100644 --- a/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h +++ b/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h @@ -49,6 +49,7 @@ #define IMX8M_CCM_CCGR_SETTINGn_NEEDED(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b11) void imx8m_early_setup_uart_clock(void); +void imx8mm_early_clock_init(void); void imx8m_clock_set_target_val(int clock_id, u32 val); void imx8m_ccgr_clock_enable(int index); void imx8m_ccgr_clock_disable(int index); diff --git a/arch/arm/mach-imx/include/mach/imx8mq.h b/arch/arm/mach-imx/include/mach/imx8mq.h index c085894ef7..2ef2987188 100644 --- a/arch/arm/mach-imx/include/mach/imx8mq.h +++ b/arch/arm/mach-imx/include/mach/imx8mq.h @@ -4,6 +4,7 @@ #include #include #include +#include #include #include @@ -13,11 +14,21 @@ #define IMX8MQ_OCOTP_VERSION_B1_MAGIC 0xff0055aa #define MX8MQ_ANATOP_DIGPROG 0x6c +#define MX8MM_ANATOP_DIGPROG 0x800 #define DIGPROG_MAJOR GENMASK(23, 8) #define DIGPROG_MINOR GENMASK(7, 0) #define IMX8M_CPUTYPE_IMX8MQ 0x8240 +#define IMX8M_CPUTYPE_IMX8MM 0x8241 + +static inline int imx8mm_cpu_revision(void) +{ + void __iomem *anatop = IOMEM(MX8MM_ANATOP_BASE_ADDR); + uint32_t revision = FIELD_GET(DIGPROG_MINOR, + readl(anatop + MX8MM_ANATOP_DIGPROG)); + return revision; +} static inline int imx8mq_cpu_revision(void) { @@ -49,6 +60,6 @@ static inline int imx8mq_cpu_revision(void) return revision; } -u64 imx8mq_uid(void); +u64 imx8m_uid(void); #endif /* __MACH_IMX8_H */ \ No newline at end of file diff --git a/arch/arm/mach-imx/include/mach/imx_cpu_types.h b/arch/arm/mach-imx/include/mach/imx_cpu_types.h index 754fb9822b..b3fccfadb5 100644 --- a/arch/arm/mach-imx/include/mach/imx_cpu_types.h +++ b/arch/arm/mach-imx/include/mach/imx_cpu_types.h @@ -13,6 +13,7 @@ #define IMX_CPU_IMX6 6 #define IMX_CPU_IMX7 7 #define IMX_CPU_IMX8MQ 8 +#define IMX_CPU_IMX8MM 81 #define IMX_CPU_VF610 610 #endif /* __MACH_IMX_CPU_TYPES_H */ -- cgit v1.2.3