From 764ae1647cafad7c28db7875c49bbaf5af6ed7c0 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 8 Jan 2014 13:04:45 +0100 Subject: ARM: i.MX: Add correct SoC type detection for i.MX6 Using the ANATOP_SI_REV register we can only distinguish between i.MX6q/d and i.MX6dl/s SoCs. Take the number of cores into account to get the exact SoC type. Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/imx6.c | 10 +++++-- arch/arm/mach-imx/include/mach/imx6.h | 49 +++++++++++++++++++++++++++++------ 2 files changed, 49 insertions(+), 10 deletions(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c index ed1edd7adc..13d8bfaf26 100644 --- a/arch/arm/mach-imx/imx6.c +++ b/arch/arm/mach-imx/imx6.c @@ -86,10 +86,16 @@ int imx6_init(void) switch (imx6_cpu_type()) { case IMX6_CPUTYPE_IMX6Q: - cputypestr = "i.MX6 Dual/Quad"; + cputypestr = "i.MX6 Quad"; + break; + case IMX6_CPUTYPE_IMX6D: + cputypestr = "i.MX6 Dual"; break; case IMX6_CPUTYPE_IMX6DL: - cputypestr = "i.MX6 Solo/DualLite"; + cputypestr = "i.MX6 DualLite"; + break; + case IMX6_CPUTYPE_IMX6S: + cputypestr = "i.MX6 Solo"; break; default: cputypestr = "unknown i.MX6"; diff --git a/arch/arm/mach-imx/include/mach/imx6.h b/arch/arm/mach-imx/include/mach/imx6.h index 4b2b1c7a69..1898d8150b 100644 --- a/arch/arm/mach-imx/include/mach/imx6.h +++ b/arch/arm/mach-imx/include/mach/imx6.h @@ -9,24 +9,47 @@ void imx6_init_lowlevel(void); #define IMX6_ANATOP_SI_REV 0x260 -#define IMX6_CPUTYPE_IMX6Q 0x63 -#define IMX6_CPUTYPE_IMX6DL 0x61 +#define IMX6_CPUTYPE_IMX6S 0x161 +#define IMX6_CPUTYPE_IMX6DL 0x261 +#define IMX6_CPUTYPE_IMX6D 0x263 +#define IMX6_CPUTYPE_IMX6Q 0x463 -static inline int imx6_cpu_type(void) +#define SCU_CONFIG 0x04 + +static inline int scu_get_core_count(void) +{ + unsigned long base; + unsigned int ncores; + + asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base)); + + ncores = readl(base + SCU_CONFIG); + return (ncores & 0x03) + 1; +} + +static inline int __imx6_cpu_type(void) { uint32_t val; + val = readl(MX6_ANATOP_BASE_ADDR + IMX6_ANATOP_SI_REV); + val = (val >> 16) & 0xff; + + val |= scu_get_core_count() << 8; + + return val; +} + +static inline int imx6_cpu_type(void) +{ if (!cpu_is_mx6()) return 0; - val = readl(MX6_ANATOP_BASE_ADDR + IMX6_ANATOP_SI_REV); - - return (val >> 16) & 0xff; + return __imx6_cpu_type(); } -static inline int cpu_is_mx6q(void) +static inline int cpu_is_mx6s(void) { - return imx6_cpu_type() == IMX6_CPUTYPE_IMX6Q; + return imx6_cpu_type() == IMX6_CPUTYPE_IMX6S; } static inline int cpu_is_mx6dl(void) @@ -34,4 +57,14 @@ static inline int cpu_is_mx6dl(void) return imx6_cpu_type() == IMX6_CPUTYPE_IMX6DL; } +static inline int cpu_is_mx6d(void) +{ + return imx6_cpu_type() == IMX6_CPUTYPE_IMX6D; +} + +static inline int cpu_is_mx6q(void) +{ + return imx6_cpu_type() == IMX6_CPUTYPE_IMX6Q; +} + #endif /* __MACH_IMX6_H */ -- cgit v1.2.3 From f1f6d76370b379589488b91d39ac284f1466caf3 Mon Sep 17 00:00:00 2001 From: Jesús Guitarte Date: Wed, 18 Dec 2013 13:10:29 +0100 Subject: ARM: i.MX6: correct work flow of PFDs from uboot-sources MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PFDs need to be gate/ungate after PLL lock to reset PFDs to right state. Otherwise PFDs may lose correct state in state-machine, then no output clock. For i.MX6DL and i.MX6SL, ROM have taken care of PFD396 already since the bus clock needs it. This patch is backported from http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/commit/cpu/arm_cortexa8/mx6/generic.c?h=imx_v2009.08_3.0.35_4.1.0&id=b7c5badf94ffbe6cd0845efbb75e16e05e3af404 And resolve issues with booting from MMC/SD cards Signed-off-by: Jesús Guitarte Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/imx6.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c index 13d8bfaf26..304b1c0f2e 100644 --- a/arch/arm/mach-imx/imx6.c +++ b/arch/arm/mach-imx/imx6.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -27,6 +28,7 @@ void imx6_init_lowlevel(void) { void __iomem *aips1 = (void *)MX6_AIPS1_ON_BASE_ADDR; void __iomem *aips2 = (void *)MX6_AIPS2_ON_BASE_ADDR; + int is_imx6q = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6Q; /* * Set all MPROTx to be non-bufferable, trusted for R/W, @@ -56,6 +58,35 @@ void imx6_init_lowlevel(void) writel(0xffffffff, 0x020c4078); writel(0xffffffff, 0x020c407c); writel(0xffffffff, 0x020c4080); + + /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs + * to make sure PFD is working right, otherwise, PFDs may + * not output clock after reset, MX6DL and MX6SL have added 396M pfd + * workaround in ROM code, as bus clock need it + */ + writel(BM_ANADIG_PFD_480_PFD3_CLKGATE | + BM_ANADIG_PFD_480_PFD2_CLKGATE | + BM_ANADIG_PFD_480_PFD1_CLKGATE | + BM_ANADIG_PFD_480_PFD0_CLKGATE, + MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_SET); + writel(BM_ANADIG_PFD_528_PFD3_CLKGATE | + (is_imx6q ? BM_ANADIG_PFD_528_PFD2_CLKGATE : 0) | + BM_ANADIG_PFD_528_PFD1_CLKGATE | + BM_ANADIG_PFD_528_PFD0_CLKGATE, + MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_SET); + + writel(BM_ANADIG_PFD_480_PFD3_CLKGATE | + BM_ANADIG_PFD_480_PFD2_CLKGATE | + BM_ANADIG_PFD_480_PFD1_CLKGATE | + BM_ANADIG_PFD_480_PFD0_CLKGATE, + MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_CLR); + writel(BM_ANADIG_PFD_528_PFD3_CLKGATE | + (is_imx6q ? BM_ANADIG_PFD_528_PFD2_CLKGATE : 0) | + BM_ANADIG_PFD_528_PFD2_CLKGATE | + BM_ANADIG_PFD_528_PFD1_CLKGATE | + BM_ANADIG_PFD_528_PFD0_CLKGATE, + MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_CLR); + } int imx6_init(void) -- cgit v1.2.3 From 3c3e99d6acaaec43b806a51dc68d2cd9c5fa441d Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 13 Jan 2014 01:17:29 +0100 Subject: ARM: imx6: add initial support for Nitrogen6X boards Only the 1GB variant is supported for now, as I don't have anything other to test with. Signed-off-by: Lucas Stach Signed-off-by: Sascha Hauer --- arch/arm/boards/Makefile | 1 + .../arm/boards/boundarydevices-nitrogen6x/Makefile | 3 + arch/arm/boards/boundarydevices-nitrogen6x/board.c | 77 ++++ .../boundarydevices-nitrogen6x/env/config-board | 6 + .../flash-header-nitrogen6x-1g.imxcfg | 106 ++++++ .../boards/boundarydevices-nitrogen6x/lowlevel.c | 30 ++ arch/arm/dts/Makefile | 5 +- arch/arm/dts/imx6dl-nitrogen6x.dts | 21 ++ arch/arm/dts/imx6q-nitrogen6x.dts | 25 ++ arch/arm/dts/imx6qdl-nitrogen6x.dtsi | 412 +++++++++++++++++++++ arch/arm/mach-imx/Kconfig | 4 + images/Makefile.imx | 10 + 12 files changed, 699 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boards/boundarydevices-nitrogen6x/Makefile create mode 100644 arch/arm/boards/boundarydevices-nitrogen6x/board.c create mode 100644 arch/arm/boards/boundarydevices-nitrogen6x/env/config-board create mode 100644 arch/arm/boards/boundarydevices-nitrogen6x/flash-header-nitrogen6x-1g.imxcfg create mode 100644 arch/arm/boards/boundarydevices-nitrogen6x/lowlevel.c create mode 100644 arch/arm/dts/imx6dl-nitrogen6x.dts create mode 100644 arch/arm/dts/imx6q-nitrogen6x.dts create mode 100644 arch/arm/dts/imx6qdl-nitrogen6x.dtsi (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index bb269418ef..7f56359d60 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_MACH_AT91SAM9N12EK) += at91sam9n12ek/ obj-$(CONFIG_MACH_AT91SAM9X5EK) += at91sam9x5ek/ obj-$(CONFIG_MACH_BEAGLE) += beagle/ obj-$(CONFIG_MACH_BEAGLEBONE) += beaglebone/ +obj-$(CONFIG_MACH_NITROGEN6X) += boundarydevices-nitrogen6x/ obj-$(CONFIG_MACH_CCMX51) += ccxmx51/ obj-$(CONFIG_MACH_CFA10036) += crystalfontz-cfa10036/ obj-$(CONFIG_MACH_CHUMBY) += chumby_falconwing/ diff --git a/arch/arm/boards/boundarydevices-nitrogen6x/Makefile b/arch/arm/boards/boundarydevices-nitrogen6x/Makefile new file mode 100644 index 0000000000..177c5d81a5 --- /dev/null +++ b/arch/arm/boards/boundarydevices-nitrogen6x/Makefile @@ -0,0 +1,3 @@ +obj-y += board.o flash-header-nitrogen6x-1g.dcd.o +extra-y += flash-header-nitrogen6x-1g.dcd.S flash-header-nitrogen6x-1g.dcd +lwl-y += lowlevel.o diff --git a/arch/arm/boards/boundarydevices-nitrogen6x/board.c b/arch/arm/boards/boundarydevices-nitrogen6x/board.c new file mode 100644 index 0000000000..1c4b49563f --- /dev/null +++ b/arch/arm/boards/boundarydevices-nitrogen6x/board.c @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2014 Lucas Stach, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +static int nitrogen6x_devices_init(void) +{ + if (!of_machine_is_compatible("fsl,imx6dl-nitrogen6x") && + !of_machine_is_compatible("fsl,imx6q-nitrogen6x")) + return 0; + + imx6_bbu_internal_spi_i2c_register_handler("spiflash", "/dev/m25p0.barebox", + BBU_HANDLER_FLAG_DEFAULT, NULL, 0, 0); + + return 0; +} +device_initcall(nitrogen6x_devices_init); + +static int ksz9021rn_phy_fixup(struct phy_device *dev) +{ + phy_write(dev, 0x09, 0x0f00); + + /* do same as linux kernel */ + /* min rx data delay */ + phy_write(dev, 0x0b, 0x8105); + phy_write(dev, 0x0c, 0x0000); + + /* max rx/tx clock delay, min rx/tx control delay */ + phy_write(dev, 0x0b, 0x8104); + phy_write(dev, 0x0c, 0xf0f0); + phy_write(dev, 0x0b, 0x104); + + return 0; +} + +static int nitrogen6x_coredevices_init(void) +{ + if (!of_machine_is_compatible("fsl,imx6dl-nitrogen6x") && + !of_machine_is_compatible("fsl,imx6q-nitrogen6x")) + return 0; + + phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, + ksz9021rn_phy_fixup); + return 0; +} +coredevice_initcall(nitrogen6x_coredevices_init); + +static int nitrogen6x_postcore_init(void) +{ + if (!of_machine_is_compatible("fsl,imx6dl-nitrogen6x") && + !of_machine_is_compatible("fsl,imx6q-nitrogen6x")) + return 0; + + imx6_init_lowlevel(); + + barebox_set_hostname("nitrogen6x"); + + return 0; +} +postcore_initcall(nitrogen6x_postcore_init); diff --git a/arch/arm/boards/boundarydevices-nitrogen6x/env/config-board b/arch/arm/boards/boundarydevices-nitrogen6x/env/config-board new file mode 100644 index 0000000000..4cabac63dd --- /dev/null +++ b/arch/arm/boards/boundarydevices-nitrogen6x/env/config-board @@ -0,0 +1,6 @@ +#!/bin/sh + +# board defaults, do not change in running system. Change /env/config +# instead + +global.linux.bootargs.base="console=ttymxc1,115200" diff --git a/arch/arm/boards/boundarydevices-nitrogen6x/flash-header-nitrogen6x-1g.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6x/flash-header-nitrogen6x-1g.imxcfg new file mode 100644 index 0000000000..60a39fe870 --- /dev/null +++ b/arch/arm/boards/boundarydevices-nitrogen6x/flash-header-nitrogen6x-1g.imxcfg @@ -0,0 +1,106 @@ +soc imx6 +loadaddr 0x20000000 +dcdofs 0x400 + +wm 32 0x020e05a8 0x00000030 +wm 32 0x020e05b0 0x00000030 +wm 32 0x020e0524 0x00000030 +wm 32 0x020e051c 0x00000030 +wm 32 0x020e0518 0x00000030 +wm 32 0x020e050c 0x00000030 +wm 32 0x020e05b8 0x00000030 +wm 32 0x020e05c0 0x00000030 +wm 32 0x020e05ac 0x00020030 +wm 32 0x020e05b4 0x00020030 +wm 32 0x020e0528 0x00020030 +wm 32 0x020e0520 0x00020030 +wm 32 0x020e0514 0x00020030 +wm 32 0x020e0510 0x00020030 +wm 32 0x020e05bc 0x00020030 +wm 32 0x020e05c4 0x00020030 +wm 32 0x020e056c 0x00020030 +wm 32 0x020e0578 0x00020030 +wm 32 0x020e0588 0x00020030 +wm 32 0x020e0594 0x00020030 +wm 32 0x020e057c 0x00020030 +wm 32 0x020e0590 0x00003000 +wm 32 0x020e0598 0x00003000 +wm 32 0x020e058c 0x00000000 +wm 32 0x020e059c 0x00003030 +wm 32 0x020e05a0 0x00003030 +wm 32 0x020e0784 0x00000030 +wm 32 0x020e0788 0x00000030 +wm 32 0x020e0794 0x00000030 +wm 32 0x020e079c 0x00000030 +wm 32 0x020e07a0 0x00000030 +wm 32 0x020e07a4 0x00000030 +wm 32 0x020e07a8 0x00000030 +wm 32 0x020e0748 0x00000030 +wm 32 0x020e074c 0x00000030 +wm 32 0x020e0750 0x00020000 +wm 32 0x020e0758 0x00000000 +wm 32 0x020e0774 0x00020000 +wm 32 0x020e078c 0x00000030 +wm 32 0x020e0798 0x000c0000 +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 +wm 32 0x021b0018 0x00081740 +wm 32 0x021b001c 0x00008000 +wm 32 0x021b000c 0x555a7975 +wm 32 0x021b0010 0xff538e64 +wm 32 0x021b0014 0x01ff00db +wm 32 0x021b002c 0x000026d2 +wm 32 0x021b0030 0x005b0e21 +wm 32 0x021b0008 0x09444040 +wm 32 0x021b0004 0x00025576 +wm 32 0x021b0040 0x00000027 +wm 32 0x021b0000 0x831a0000 +wm 32 0x021b001c 0x04088032 +wm 32 0x021b001c 0x0408803a +wm 32 0x021b001c 0x00008033 +wm 32 0x021b001c 0x0000803b +wm 32 0x021b001c 0x00428031 +wm 32 0x021b001c 0x00428039 +wm 32 0x021b001c 0x09408030 +wm 32 0x021b001c 0x09408038 +wm 32 0x021b001c 0x04008040 +wm 32 0x021b001c 0x04008048 +wm 32 0x021b0800 0xa1380003 +wm 32 0x021b4800 0xa1380003 +wm 32 0x021b0020 0x00005800 +wm 32 0x021b0818 0x00022227 +wm 32 0x021b4818 0x00022227 +wm 32 0x021b083c 0x434b0350 +wm 32 0x021b0840 0x034c0359 +wm 32 0x021b483c 0x434b0350 +wm 32 0x021b4840 0x03650348 +wm 32 0x021b0848 0x4436383b +wm 32 0x021b4848 0x39393341 +wm 32 0x021b0850 0x35373933 +wm 32 0x021b4850 0x48254A36 +wm 32 0x021b080c 0x001f001f +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x00440044 +wm 32 0x021b4810 0x00440044 +wm 32 0x021b08b8 0x00000800 +wm 32 0x021b48b8 0x00000800 +wm 32 0x021b001c 0x00000000 +wm 32 0x021b0404 0x00011006 +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff +/* enable AXI cache for VDOA/VPU/IPU */ +wm 32 0x020e0010 0xf00000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7 */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f diff --git a/arch/arm/boards/boundarydevices-nitrogen6x/lowlevel.c b/arch/arm/boards/boundarydevices-nitrogen6x/lowlevel.c new file mode 100644 index 0000000000..5b11084670 --- /dev/null +++ b/arch/arm/boards/boundarydevices-nitrogen6x/lowlevel.c @@ -0,0 +1,30 @@ +#include +#include +#include +#include + +extern char __dtb_imx6q_nitrogen6x_start[]; + +ENTRY_FUNCTION(start_imx6q_nitrogen6x_1g, r0, r1, r2) +{ + uint32_t fdt; + + arm_cpu_lowlevel_init(); + + fdt = (uint32_t)__dtb_imx6q_nitrogen6x_start - get_runtime_offset(); + + barebox_arm_entry(0x10000000, SZ_1G, fdt); +} + +extern char __dtb_imx6dl_nitrogen6x_start[]; + +ENTRY_FUNCTION(start_imx6dl_nitrogen6x_1g, r0, r1, r2) +{ + uint32_t fdt; + + arm_cpu_lowlevel_init(); + + fdt = (uint32_t)__dtb_imx6dl_nitrogen6x_start - get_runtime_offset(); + + barebox_arm_entry(0x10000000, SZ_1G, fdt); +} diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 90ac28d220..e89eb2fd7b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -16,7 +16,9 @@ dtb-$(CONFIG_ARCH_IMX6) += imx6q-gk802.dtb \ imx6dl-mba6x.dtb \ imx6q-mba6x.dtb \ imx6q-phytec-pbab01.dtb \ - imx6dl-cubox-i-carrier-1.dtb + imx6dl-cubox-i-carrier-1.dtb \ + imx6q-nitrogen6x.dtb \ + imx6dl-nitrogen6x.dtb dtb-$(CONFIG_ARCH_MVEBU) += dove-cubox.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb @@ -45,6 +47,7 @@ pbl-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o pbl-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o pbl-$(CONFIG_MACH_SOLIDRUN_CARRIER1) += imx6dl-cubox-i-carrier-1.dtb.o pbl-$(CONFIG_MACH_SABRELITE) += imx6q-sabrelite.dtb.o imx6dl-sabrelite.dtb.o +pbl-$(CONFIG_MACH_NITROGEN6X) += imx6q-nitrogen6x.dtb.o imx6dl-nitrogen6x.dtb.o .SECONDARY: $(obj)/$(BUILTIN_DTB).dtb.S .SECONDARY: $(patsubst %,$(obj)/%.S,$(dtb-y)) diff --git a/arch/arm/dts/imx6dl-nitrogen6x.dts b/arch/arm/dts/imx6dl-nitrogen6x.dts new file mode 100644 index 0000000000..5f4d33ccc4 --- /dev/null +++ b/arch/arm/dts/imx6dl-nitrogen6x.dts @@ -0,0 +1,21 @@ +/* + * Copyright 2013 Boundary Devices, Inc. + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-nitrogen6x.dtsi" + +/ { + model = "Freescale i.MX6 DualLite Nitrogen6x Board"; + compatible = "fsl,imx6dl-nitrogen6x", "fsl,imx6dl"; +}; diff --git a/arch/arm/dts/imx6q-nitrogen6x.dts b/arch/arm/dts/imx6q-nitrogen6x.dts new file mode 100644 index 0000000000..a57866b2e9 --- /dev/null +++ b/arch/arm/dts/imx6q-nitrogen6x.dts @@ -0,0 +1,25 @@ +/* + * Copyright 2013 Boundary Devices, Inc. + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-nitrogen6x.dtsi" + +/ { + model = "Freescale i.MX6 Quad Nitrogen6x Board"; + compatible = "fsl,imx6q-nitrogen6x", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/dts/imx6qdl-nitrogen6x.dtsi new file mode 100644 index 0000000000..07452f944b --- /dev/null +++ b/arch/arm/dts/imx6qdl-nitrogen6x.dtsi @@ -0,0 +1,412 @@ +/* + * Copyright 2013 Boundary Devices, Inc. + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +/ { + chosen { + linux,stdout-path = &uart2; + + environment@0 { + compatible = "barebox,environment"; + device-path = &flash, "partname:barebox-environment"; + }; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_2p5v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + power { + label = "Power Button"; + gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + linux,code = ; + gpio-key,wakeup; + }; + + menu { + label = "Menu"; + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + home { + label = "Home"; + gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + back { + label = "Back"; + gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + sound { + compatible = "fsl,imx6q-nitrogen6x-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6q-nitrogen6x-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; + + backlight_lcd { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_3p3v>; + status = "okay"; + }; + + backlight_lvds { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_3p3v>; + status = "okay"; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio3 19 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b", "m25p80"; + spi-max-frequency = <20000000>; + reg = <0>; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x80000>; + }; + + partition@1 { + label = "barebox-environment"; + reg = <0x80000 0x80000>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio1 27 0>; + txen-skew-ps = <0>; + txc-skew-ps = <3000>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks 201>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6q-nitrogen6x { + pinctrl_hog: hoggrp { + fsl,pins = < + /* SGTL5000 sys_mclk */ + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0 + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = ; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_ECSPI1_PINGRP1 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_ENET_PINGRP_RGMII_MD(0x1b0b0, 0x100b0) + /* Phy reset */ + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x000b0 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + /* Power Button */ + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + /* Menu Button */ + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + /* Home Button */ + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 + /* Back Button */ + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + /* Volume Up Button */ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 + /* Volume Down Button */ + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = ; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = ; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = ; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + /* power enable, high active */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_USDHC3_PINGRP_D4 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */ + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_USDHC4_PINGRP_D4 + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */ + >; + }; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&ocotp { + barebox,provide-mac-address = <&fec 0x620>; +}; + +&pcie { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbh1 { + phy_type = "utmi"; + dr_mode = "host"; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + phy_type = "utmi"; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio7 0 0>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + cd-gpios = <&gpio2 6 0>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 3a1089f0ed..7587e15003 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -228,6 +228,10 @@ config MACH_SABRELITE select ARCH_IMX6 select HAVE_DEFAULT_ENVIRONMENT_NEW select HAVE_PBL_MULTI_IMAGES + +config MACH_NITROGEN6X + bool "BoundaryDevices Nitrogen6x" + select ARCH_IMX6 config MACH_SOLIDRUN_CARRIER1 bool "SolidRun CuBox-i Carrier-1" diff --git a/images/Makefile.imx b/images/Makefile.imx index 12007f51cf..b6c9c9ecaf 100644 --- a/images/Makefile.imx +++ b/images/Makefile.imx @@ -93,3 +93,13 @@ pblx-$(CONFIG_MACH_SOLIDRUN_CARRIER1) += start_imx6dl_cubox_i_carrier_1 CFG_start_imx6dl_cubox_i_carrier_1.pblx.imximg = $(board)/solidrun-carrier-1/flash-header-solidrun-carrier-1.imxcfg FILE_barebox-cubox-i-carrier-1.img = start_imx6dl_cubox_i_carrier_1.pblx.imximg image-$(CONFIG_MACH_SOLIDRUN_CARRIER1) += barebox-cubox-i-carrier-1.img + +pblx-$(CONFIG_MACH_NITROGEN6X) += start_imx6q_nitrogen6x_1g +CFG_start_imx6q_nitrogen6x_1g.pblx.imximg = $(board)/boundarydevices-nitrogen6x/flash-header-nitrogen6x-1g.imxcfg +FILE_barebox-boundarydevices-imx6q-nitrogen6x-1g.img = start_imx6q_nitrogen6x_1g.pblx.imximg +image-$(CONFIG_MACH_NITROGEN6X) += barebox-boundarydevices-imx6q-nitrogen6x-1g.img + +pblx-$(CONFIG_MACH_NITROGEN6X) += start_imx6dl_nitrogen6x_1g +CFG_start_imx6dl_nitrogen6x_1g.pblx.imximg = $(board)/boundarydevices-nitrogen6x/flash-header-nitrogen6x-1g.imxcfg +FILE_barebox-boundarydevices-imx6dl-nitrogen6x-1g.img = start_imx6dl_nitrogen6x_1g.pblx.imximg +image-$(CONFIG_MACH_NITROGEN6X) += barebox-boundarydevices-imx6dl-nitrogen6x-1g.img -- cgit v1.2.3 From 67221982b3c327ead2fbe6e527cfa42479caf69f Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 13 Jan 2014 01:17:30 +0100 Subject: ARM: imx6: rename Carrier-1 to Hummingboard Solidrun has renamed the Carrier-1 to Hummingboard. This is also the name that is used in upstream Linux, change barebox to be in line with that. Signed-off-by: Lucas Stach Signed-off-by: Sascha Hauer --- arch/arm/boards/Makefile | 2 +- arch/arm/boards/solidrun-carrier-1/Makefile | 3 - arch/arm/boards/solidrun-carrier-1/board.c | 89 --------------- .../flash-header-solidrun-carrier-1.imxcfg | 79 -------------- arch/arm/boards/solidrun-carrier-1/lowlevel.c | 18 ---- arch/arm/boards/solidrun-hummingboard/Makefile | 3 + arch/arm/boards/solidrun-hummingboard/board.c | 89 +++++++++++++++ .../flash-header-solidrun-hummingboard.imxcfg | 79 ++++++++++++++ arch/arm/boards/solidrun-hummingboard/lowlevel.c | 18 ++++ arch/arm/dts/Makefile | 4 +- arch/arm/dts/imx6dl-cubox-i-carrier-1.dts | 120 --------------------- arch/arm/dts/imx6dl-hummingboard.dts | 120 +++++++++++++++++++++ arch/arm/dts/imx6qdl-microsom.dtsi | 21 ++-- arch/arm/mach-imx/Kconfig | 4 +- images/Makefile.imx | 8 +- 15 files changed, 331 insertions(+), 326 deletions(-) delete mode 100644 arch/arm/boards/solidrun-carrier-1/Makefile delete mode 100644 arch/arm/boards/solidrun-carrier-1/board.c delete mode 100644 arch/arm/boards/solidrun-carrier-1/flash-header-solidrun-carrier-1.imxcfg delete mode 100644 arch/arm/boards/solidrun-carrier-1/lowlevel.c create mode 100644 arch/arm/boards/solidrun-hummingboard/Makefile create mode 100644 arch/arm/boards/solidrun-hummingboard/board.c create mode 100644 arch/arm/boards/solidrun-hummingboard/flash-header-solidrun-hummingboard.imxcfg create mode 100644 arch/arm/boards/solidrun-hummingboard/lowlevel.c delete mode 100644 arch/arm/dts/imx6dl-cubox-i-carrier-1.dts create mode 100644 arch/arm/dts/imx6dl-hummingboard.dts (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index 7f56359d60..a4219d7f77 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -79,7 +79,7 @@ obj-$(CONFIG_MACH_SAMA5D3XEK) += sama5d3xek/ obj-$(CONFIG_MACH_SCB9328) += scb9328/ obj-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += ebv-socrates/ obj-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += terasic-sockit/ -obj-$(CONFIG_MACH_SOLIDRUN_CARRIER1) += solidrun-carrier-1/ +obj-$(CONFIG_MACH_SOLIDRUN_HUMMINGBOARD) += solidrun-hummingboard/ obj-$(CONFIG_MACH_TNY_A9260) += tny-a926x/ obj-$(CONFIG_MACH_TNY_A9263) += tny-a926x/ obj-$(CONFIG_MACH_TNY_A9G20) += tny-a926x/ diff --git a/arch/arm/boards/solidrun-carrier-1/Makefile b/arch/arm/boards/solidrun-carrier-1/Makefile deleted file mode 100644 index d243c8f1a3..0000000000 --- a/arch/arm/boards/solidrun-carrier-1/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -obj-y += board.o flash-header-solidrun-carrier-1.dcd.o -extra-y += flash-header-solidrun-carrier-1.dcd.S flash-header-solidrun-carrier-1.dcd -lwl-y += lowlevel.o diff --git a/arch/arm/boards/solidrun-carrier-1/board.c b/arch/arm/boards/solidrun-carrier-1/board.c deleted file mode 100644 index f520303b73..0000000000 --- a/arch/arm/boards/solidrun-carrier-1/board.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (C) 2013 Lucas Stach - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static int ar8035_phy_fixup(struct phy_device *dev) -{ - u16 val; - - /* Ar803x phy SmartEEE feature cause link status generates glitch, - * which cause ethernet link down/up issue, so disable SmartEEE - */ - phy_write(dev, 0xd, 0x3); - phy_write(dev, 0xe, 0x805d); - phy_write(dev, 0xd, 0x4003); - - val = phy_read(dev, 0xe); - phy_write(dev, 0xe, val & ~(1 << 8)); - - /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ - phy_write(dev, 0xd, 0x7); - phy_write(dev, 0xe, 0x8016); - phy_write(dev, 0xd, 0x4007); - - val = phy_read(dev, 0xe); - val &= 0xffe3; - val |= 0x18; - phy_write(dev, 0xe, val); - - /* introduce tx clock delay */ - phy_write(dev, 0x1d, 0x5); - val = phy_read(dev, 0x1e); - val |= 0x0100; - phy_write(dev, 0x1e, val); - - return 0; -} - -static int carrier1_device_init(void) -{ - if (!of_machine_is_compatible("solidrun,cubox-i-carrier-1")) - return 0; - - phy_register_fixup_for_uid(0x004dd072, 0xffffffef, ar8035_phy_fixup); - - /* enable USB VBUS */ - gpio_direction_output(IMX_GPIO_NR(3, 22), 1); - gpio_direction_output(IMX_GPIO_NR(1, 0), 1); - - return 0; -} -device_initcall(carrier1_device_init); - -static int carrier1_lwl_init(void) -{ - if (!of_machine_is_compatible("solidrun,cubox-i-carrier-1")) - return 0; - - barebox_set_hostname("carrier-1"); - - imx6_init_lowlevel(); - - return 0; -} -postcore_initcall(carrier1_lwl_init); diff --git a/arch/arm/boards/solidrun-carrier-1/flash-header-solidrun-carrier-1.imxcfg b/arch/arm/boards/solidrun-carrier-1/flash-header-solidrun-carrier-1.imxcfg deleted file mode 100644 index b1856b49ce..0000000000 --- a/arch/arm/boards/solidrun-carrier-1/flash-header-solidrun-carrier-1.imxcfg +++ /dev/null @@ -1,79 +0,0 @@ -loadaddr 0x10000000 -soc imx6 -dcdofs 0x400 -wm 32 0x020e0774 0x000c0000 -wm 32 0x020e0754 0x00000000 -wm 32 0x020e04ac 0x00000030 -wm 32 0x020e04b0 0x00000030 -wm 32 0x020e0464 0x00000030 -wm 32 0x020e0490 0x00000030 -wm 32 0x020e074c 0x00000030 -wm 32 0x020e0494 0x00000030 -wm 32 0x020e04a4 0x00003000 -wm 32 0x020e04a8 0x00003000 -wm 32 0x020e04a0 0x00000000 -wm 32 0x020e04b4 0x00003030 -wm 32 0x020e04b8 0x00003030 -wm 32 0x020e076c 0x00000030 -wm 32 0x020e0750 0x00000000 -wm 32 0x020e04bc 0x00000030 -wm 32 0x020e04c0 0x00000030 -wm 32 0x020e04c4 0x00000030 -wm 32 0x020e04c8 0x00000030 -wm 32 0x020e04cc 0x00000000 -wm 32 0x020e04d0 0x00000000 -wm 32 0x020e04d4 0x00000000 -wm 32 0x020e04d8 0x00000000 -wm 32 0x020e0760 0x00000000 -wm 32 0x020e0764 0x00000030 -wm 32 0x020e0770 0x00000030 -wm 32 0x020e0778 0x00000030 -wm 32 0x020e077c 0x00000030 -wm 32 0x020e0780 0x00000000 -wm 32 0x020e0784 0x00000000 -wm 32 0x020e078c 0x00000000 -wm 32 0x020e0748 0x00000000 -wm 32 0x020e0470 0x00000030 -wm 32 0x020e0474 0x00000030 -wm 32 0x020e0478 0x00000030 -wm 32 0x020e047c 0x00000030 -wm 32 0x020e0480 0x00000000 -wm 32 0x020e0484 0x00000000 -wm 32 0x020e0488 0x00000000 -wm 32 0x020e048c 0x00000000 -wm 32 0x021b0800 0xa1390003 -wm 32 0x021b4800 0xa1390003 -wm 32 0x021b080c 0x000F0011 -wm 32 0x021b0810 0x000E000F -wm 32 0x021b083c 0x42240229 -wm 32 0x021b0840 0x021a0219 -wm 32 0x021b0848 0x4e4f5150 -wm 32 0x021b0850 0x35363136 -wm 32 0x021b081c 0x33333333 -wm 32 0x021b0820 0x33333333 -wm 32 0x021b0824 0x33333333 -wm 32 0x021b0828 0x33333333 -wm 32 0x021b08b8 0x00000800 -wm 32 0x021b48b8 0x00000800 -wm 32 0x021b0004 0x0002002d -wm 32 0x021b0008 0x00333030 -wm 32 0x021b000c 0x40445323 -wm 32 0x021b0010 0xb68e8c63 -wm 32 0x021b0014 0x01ff00db -wm 32 0x021b0018 0x00001740 -wm 32 0x021b001c 0x00008000 -wm 32 0x021b002c 0x000026d2 -wm 32 0x021b0030 0x00440e21 -wm 32 0x021b0040 0x00000017 -wm 32 0x021b0400 0x11420000 -wm 32 0x021b0000 0x83190000 -wm 32 0x021b001c 0x04008032 -wm 32 0x021b001c 0x00008033 -wm 32 0x021b001c 0x00428031 -wm 32 0x021b001c 0x07208030 -wm 32 0x021b001c 0x04008040 -wm 32 0x021b0020 0x00005800 -wm 32 0x021b0818 0x00000007 -wm 32 0x021b0004 0x0002556d -wm 32 0x021b0404 0x00011006 -wm 32 0x021b001c 0x00000000 diff --git a/arch/arm/boards/solidrun-carrier-1/lowlevel.c b/arch/arm/boards/solidrun-carrier-1/lowlevel.c deleted file mode 100644 index aa94716496..0000000000 --- a/arch/arm/boards/solidrun-carrier-1/lowlevel.c +++ /dev/null @@ -1,18 +0,0 @@ -#include -#include -#include -#include - -extern char __dtb_imx6dl_cubox_i_carrier_1_start[]; - -ENTRY_FUNCTION(start_imx6dl_cubox_i_carrier_1, r0, r1, r2) -{ - uint32_t fdt; - - __barebox_arm_head(); - - arm_cpu_lowlevel_init(); - - fdt = (uint32_t)__dtb_imx6dl_cubox_i_carrier_1_start - get_runtime_offset(); - barebox_arm_entry(0x10000000, SZ_512M, fdt); -} diff --git a/arch/arm/boards/solidrun-hummingboard/Makefile b/arch/arm/boards/solidrun-hummingboard/Makefile new file mode 100644 index 0000000000..8b4754e1c1 --- /dev/null +++ b/arch/arm/boards/solidrun-hummingboard/Makefile @@ -0,0 +1,3 @@ +obj-y += board.o flash-header-solidrun-hummingboard.dcd.o +extra-y += flash-header-solidrun-hummingboard.dcd.S flash-header-solidrun-hummingboard.dcd +lwl-y += lowlevel.o diff --git a/arch/arm/boards/solidrun-hummingboard/board.c b/arch/arm/boards/solidrun-hummingboard/board.c new file mode 100644 index 0000000000..afc5c867b2 --- /dev/null +++ b/arch/arm/boards/solidrun-hummingboard/board.c @@ -0,0 +1,89 @@ +/* + * Copyright (C) 2013 Lucas Stach + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int ar8035_phy_fixup(struct phy_device *dev) +{ + u16 val; + + /* Ar803x phy SmartEEE feature cause link status generates glitch, + * which cause ethernet link down/up issue, so disable SmartEEE + */ + phy_write(dev, 0xd, 0x3); + phy_write(dev, 0xe, 0x805d); + phy_write(dev, 0xd, 0x4003); + + val = phy_read(dev, 0xe); + phy_write(dev, 0xe, val & ~(1 << 8)); + + /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ + phy_write(dev, 0xd, 0x7); + phy_write(dev, 0xe, 0x8016); + phy_write(dev, 0xd, 0x4007); + + val = phy_read(dev, 0xe); + val &= 0xffe3; + val |= 0x18; + phy_write(dev, 0xe, val); + + /* introduce tx clock delay */ + phy_write(dev, 0x1d, 0x5); + val = phy_read(dev, 0x1e); + val |= 0x0100; + phy_write(dev, 0x1e, val); + + return 0; +} + +static int hummingboard_device_init(void) +{ + if (!of_machine_is_compatible("solidrun,hummingboard")) + return 0; + + phy_register_fixup_for_uid(0x004dd072, 0xffffffef, ar8035_phy_fixup); + + /* enable USB VBUS */ + gpio_direction_output(IMX_GPIO_NR(3, 22), 1); + gpio_direction_output(IMX_GPIO_NR(1, 0), 1); + + return 0; +} +device_initcall(hummingboard_device_init); + +static int hummingboard_lwl_init(void) +{ + if (!of_machine_is_compatible("solidrun,hummingboard")) + return 0; + + barebox_set_hostname("hummingboard"); + + imx6_init_lowlevel(); + + return 0; +} +postcore_initcall(hummingboard_lwl_init); diff --git a/arch/arm/boards/solidrun-hummingboard/flash-header-solidrun-hummingboard.imxcfg b/arch/arm/boards/solidrun-hummingboard/flash-header-solidrun-hummingboard.imxcfg new file mode 100644 index 0000000000..b1856b49ce --- /dev/null +++ b/arch/arm/boards/solidrun-hummingboard/flash-header-solidrun-hummingboard.imxcfg @@ -0,0 +1,79 @@ +loadaddr 0x10000000 +soc imx6 +dcdofs 0x400 +wm 32 0x020e0774 0x000c0000 +wm 32 0x020e0754 0x00000000 +wm 32 0x020e04ac 0x00000030 +wm 32 0x020e04b0 0x00000030 +wm 32 0x020e0464 0x00000030 +wm 32 0x020e0490 0x00000030 +wm 32 0x020e074c 0x00000030 +wm 32 0x020e0494 0x00000030 +wm 32 0x020e04a4 0x00003000 +wm 32 0x020e04a8 0x00003000 +wm 32 0x020e04a0 0x00000000 +wm 32 0x020e04b4 0x00003030 +wm 32 0x020e04b8 0x00003030 +wm 32 0x020e076c 0x00000030 +wm 32 0x020e0750 0x00000000 +wm 32 0x020e04bc 0x00000030 +wm 32 0x020e04c0 0x00000030 +wm 32 0x020e04c4 0x00000030 +wm 32 0x020e04c8 0x00000030 +wm 32 0x020e04cc 0x00000000 +wm 32 0x020e04d0 0x00000000 +wm 32 0x020e04d4 0x00000000 +wm 32 0x020e04d8 0x00000000 +wm 32 0x020e0760 0x00000000 +wm 32 0x020e0764 0x00000030 +wm 32 0x020e0770 0x00000030 +wm 32 0x020e0778 0x00000030 +wm 32 0x020e077c 0x00000030 +wm 32 0x020e0780 0x00000000 +wm 32 0x020e0784 0x00000000 +wm 32 0x020e078c 0x00000000 +wm 32 0x020e0748 0x00000000 +wm 32 0x020e0470 0x00000030 +wm 32 0x020e0474 0x00000030 +wm 32 0x020e0478 0x00000030 +wm 32 0x020e047c 0x00000030 +wm 32 0x020e0480 0x00000000 +wm 32 0x020e0484 0x00000000 +wm 32 0x020e0488 0x00000000 +wm 32 0x020e048c 0x00000000 +wm 32 0x021b0800 0xa1390003 +wm 32 0x021b4800 0xa1390003 +wm 32 0x021b080c 0x000F0011 +wm 32 0x021b0810 0x000E000F +wm 32 0x021b083c 0x42240229 +wm 32 0x021b0840 0x021a0219 +wm 32 0x021b0848 0x4e4f5150 +wm 32 0x021b0850 0x35363136 +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b08b8 0x00000800 +wm 32 0x021b48b8 0x00000800 +wm 32 0x021b0004 0x0002002d +wm 32 0x021b0008 0x00333030 +wm 32 0x021b000c 0x40445323 +wm 32 0x021b0010 0xb68e8c63 +wm 32 0x021b0014 0x01ff00db +wm 32 0x021b0018 0x00001740 +wm 32 0x021b001c 0x00008000 +wm 32 0x021b002c 0x000026d2 +wm 32 0x021b0030 0x00440e21 +wm 32 0x021b0040 0x00000017 +wm 32 0x021b0400 0x11420000 +wm 32 0x021b0000 0x83190000 +wm 32 0x021b001c 0x04008032 +wm 32 0x021b001c 0x00008033 +wm 32 0x021b001c 0x00428031 +wm 32 0x021b001c 0x07208030 +wm 32 0x021b001c 0x04008040 +wm 32 0x021b0020 0x00005800 +wm 32 0x021b0818 0x00000007 +wm 32 0x021b0004 0x0002556d +wm 32 0x021b0404 0x00011006 +wm 32 0x021b001c 0x00000000 diff --git a/arch/arm/boards/solidrun-hummingboard/lowlevel.c b/arch/arm/boards/solidrun-hummingboard/lowlevel.c new file mode 100644 index 0000000000..c101f06fed --- /dev/null +++ b/arch/arm/boards/solidrun-hummingboard/lowlevel.c @@ -0,0 +1,18 @@ +#include +#include +#include +#include + +extern char __dtb_imx6dl_hummingboard_start[]; + +ENTRY_FUNCTION(start_imx6dl_hummingboard, r0, r1, r2) +{ + uint32_t fdt; + + __barebox_arm_head(); + + arm_cpu_lowlevel_init(); + + fdt = (uint32_t)__dtb_imx6dl_hummingboard_start - get_runtime_offset(); + barebox_arm_entry(0x10000000, SZ_512M, fdt); +} diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e89eb2fd7b..add4dc07ea 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -16,7 +16,7 @@ dtb-$(CONFIG_ARCH_IMX6) += imx6q-gk802.dtb \ imx6dl-mba6x.dtb \ imx6q-mba6x.dtb \ imx6q-phytec-pbab01.dtb \ - imx6dl-cubox-i-carrier-1.dtb \ + imx6dl-hummingboard.dtb \ imx6q-nitrogen6x.dtb \ imx6dl-nitrogen6x.dtb dtb-$(CONFIG_ARCH_MVEBU) += dove-cubox.dtb @@ -45,7 +45,7 @@ pbl-$(CONFIG_MACH_TOSHIBA_AC100) += tegra20-paz00.dtb.o pbl-$(CONFIG_MACH_TQMA6X) += imx6dl-mba6x.dtb.o imx6q-mba6x.dtb.o pbl-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o pbl-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o -pbl-$(CONFIG_MACH_SOLIDRUN_CARRIER1) += imx6dl-cubox-i-carrier-1.dtb.o +pbl-$(CONFIG_MACH_SOLIDRUN_HUMMINGBOARD) += imx6dl-hummingboard.dtb.o pbl-$(CONFIG_MACH_SABRELITE) += imx6q-sabrelite.dtb.o imx6dl-sabrelite.dtb.o pbl-$(CONFIG_MACH_NITROGEN6X) += imx6q-nitrogen6x.dtb.o imx6dl-nitrogen6x.dtb.o diff --git a/arch/arm/dts/imx6dl-cubox-i-carrier-1.dts b/arch/arm/dts/imx6dl-cubox-i-carrier-1.dts deleted file mode 100644 index 1f13f03140..0000000000 --- a/arch/arm/dts/imx6dl-cubox-i-carrier-1.dts +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (C) 2013 Russell King - * - * The code contained herein is licensed under the GNU General Public - * License version 2. - */ -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-microsom.dtsi" -#include "imx6qdl-microsom-ar8035.dtsi" - -/ { - model = "SolidRun Cubox-i DL/Solo Carrier-1 Board"; - compatible = "solidrun,cubox-i-carrier-1", "fsl,imx6dl"; - - chosen { - linux,stdout-path = &uart1; - - environment@0 { - compatible = "barebox,environment"; - device-path = &usdhc2, "partname:barebox-environment"; - }; - }; - - memory { - reg = <0x10000000 0x20000000>; - }; - - ir_recv: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio1 2 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_carrier1_gpio1_2>; - }; - - codec: spdif-transmitter { - compatible = "linux,spdif-dit"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_carrier1_spdif>; - }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "imx-spdif"; - /* IMX6 doesn't implement this yet */ - spdif-controller = <&spdif>; - spdif-out; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - - /* - * Not fitted on Carrier-1 board... yet - status = "okay"; - - rtc: pcf8523@68 { - compatible = "nxp,pcf8523"; - reg = <0x68>; - }; - */ -}; - -&iomuxc { - carrier1 { - pinctrl_carrier1_gpio1_2: carrier1-gpio1_2 { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 - >; - }; - - pinctrl_carrier1_spdif: carrier1-spdif { - fsl,pins = ; - }; - - pinctrl_carrier1_usdhc2: carrier1-usdhc2 { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 - MX6QDL_PAD_GPIO_4__SD2_CD_B 0x1f071 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = ; - }; - }; -}; - -&spdif { - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_carrier1_usdhc2>; - vmmc-supply = <®_3p3v>; - fsl,cd-controller; - status = "okay"; - - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "barebox"; - reg = <0x0 0x80000>; - }; - - partition@1 { - label = "barebox-environment"; - reg = <0x80000 0x80000>; - }; -}; diff --git a/arch/arm/dts/imx6dl-hummingboard.dts b/arch/arm/dts/imx6dl-hummingboard.dts new file mode 100644 index 0000000000..e964682524 --- /dev/null +++ b/arch/arm/dts/imx6dl-hummingboard.dts @@ -0,0 +1,120 @@ +/* + * Copyright (C) 2013 Russell King + * + * The code contained herein is licensed under the GNU General Public + * License version 2. + */ +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-microsom.dtsi" +#include "imx6qdl-microsom-ar8035.dtsi" + +/ { + model = "SolidRun HummingBoard DL/Solo"; + compatible = "solidrun,hummingboard", "fsl,imx6dl"; + + chosen { + linux,stdout-path = &uart1; + + environment@0 { + compatible = "barebox,environment"; + device-path = &usdhc2, "partname:barebox-environment"; + }; + }; + + memory { + reg = <0x10000000 0x20000000>; + }; + + ir_recv: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio1 2 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_gpio1_2>; + }; + + codec: spdif-transmitter { + compatible = "linux,spdif-dit"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_spdif>; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + /* IMX6 doesn't implement this yet */ + spdif-controller = <&spdif>; + spdif-out; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_i2c1>; + + /* + * Not fitted on Carrier-1 board... yet + status = "okay"; + + rtc: pcf8523@68 { + compatible = "nxp,pcf8523"; + reg = <0x68>; + }; + */ +}; + +&iomuxc { + hummingboard { + pinctrl_hummingboard_gpio1_2: hummingboard-gpio1_2 { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 + >; + }; + + pinctrl_hummingboard_i2c1: hummingboard-i2c1 { + fsl,pins = ; + }; + + pinctrl_hummingboard_spdif: hummingboard-spdif { + fsl,pins = ; + }; + + pinctrl_hummingboard_usdhc2: hummingboard-usdhc2 { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 + MX6QDL_PAD_GPIO_4__SD2_CD_B 0x1f071 + >; + }; + }; +}; + +&spdif { + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_usdhc2>; + vmmc-supply = <®_3p3v>; + fsl,cd-controller; + status = "okay"; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x80000>; + }; + + partition@1 { + label = "barebox-environment"; + reg = <0x80000 0x80000>; + }; +}; diff --git a/arch/arm/dts/imx6qdl-microsom.dtsi b/arch/arm/dts/imx6qdl-microsom.dtsi index 85e43bfd00..a8cfbb4a3b 100644 --- a/arch/arm/dts/imx6qdl-microsom.dtsi +++ b/arch/arm/dts/imx6qdl-microsom.dtsi @@ -7,17 +7,21 @@ / { regulators { compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; - reg_3p3v: 3p3v { + reg_3p3v: regulator@0 { compatible = "regulator-fixed"; + reg = <0>; regulator-name = "3P3V"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; - reg_usb_h1_vbus: usb_h1_vbus { + reg_usb_h1_vbus: regulator@1 { compatible = "regulator-fixed"; + reg = <1>; regulator-name = "usb_h1_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -25,8 +29,9 @@ enable-active-high; }; - reg_usb_otg_vbus: usb_otg_vbus { + reg_usb_otg_vbus: regulator@2 { compatible = "regulator-fixed"; + reg = <2>; regulator-name = "usb_otg_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -51,6 +56,10 @@ >; }; + pinctrl_microsom_uart1: microsom-uart1 { + fsl,pins = ; + }; + pinctrl_microsom_usbotg: microsom-usbotg { /* * Similar to pinctrl_usbotg_2, but we want it @@ -58,16 +67,12 @@ */ fsl,pins = ; }; - - pinctrl_uart1: uart1grp { - fsl,pins = ; - }; }; }; &uart1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; + pinctrl-0 = <&pinctrl_microsom_uart1>; status = "okay"; }; diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 7587e15003..de0b9ace1a 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -233,8 +233,8 @@ config MACH_NITROGEN6X bool "BoundaryDevices Nitrogen6x" select ARCH_IMX6 -config MACH_SOLIDRUN_CARRIER1 - bool "SolidRun CuBox-i Carrier-1" +config MACH_SOLIDRUN_HUMMINGBOARD + bool "SolidRun Hummingboard" select ARCH_IMX6 endif diff --git a/images/Makefile.imx b/images/Makefile.imx index b6c9c9ecaf..4c572cf0a5 100644 --- a/images/Makefile.imx +++ b/images/Makefile.imx @@ -89,10 +89,10 @@ CFG_start_imx6dl_sabrelite.pblx.imximg = $(board)/freescale-mx6-sabrelite/flash- FILE_barebox-freescale-imx6dl-sabrelite.img = start_imx6dl_sabrelite.pblx.imximg image-$(CONFIG_MACH_SABRELITE) += barebox-freescale-imx6dl-sabrelite.img -pblx-$(CONFIG_MACH_SOLIDRUN_CARRIER1) += start_imx6dl_cubox_i_carrier_1 -CFG_start_imx6dl_cubox_i_carrier_1.pblx.imximg = $(board)/solidrun-carrier-1/flash-header-solidrun-carrier-1.imxcfg -FILE_barebox-cubox-i-carrier-1.img = start_imx6dl_cubox_i_carrier_1.pblx.imximg -image-$(CONFIG_MACH_SOLIDRUN_CARRIER1) += barebox-cubox-i-carrier-1.img +pblx-$(CONFIG_MACH_SOLIDRUN_HUMMINGBOARD) += start_imx6dl_hummingboard +CFG_start_imx6dl_hummingboard.pblx.imximg = $(board)/solidrun-hummingboard/flash-header-solidrun-hummingboard.imxcfg +FILE_barebox-solidrun-imx6dl-hummingboard.img = start_imx6dl_hummingboard.pblx.imximg +image-$(CONFIG_MACH_SOLIDRUN_HUMMINGBOARD) += barebox-solidrun-imx6dl-hummingboard.img pblx-$(CONFIG_MACH_NITROGEN6X) += start_imx6q_nitrogen6x_1g CFG_start_imx6q_nitrogen6x_1g.pblx.imximg = $(board)/boundarydevices-nitrogen6x/flash-header-nitrogen6x-1g.imxcfg -- cgit v1.2.3 From 00bd28647740ddae5291468a73ee2695a4b2c848 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 17 Jan 2014 08:50:41 +0100 Subject: ARM: phyCARD-i.MX27: switch to new environment Signed-off-by: Sascha Hauer --- arch/arm/boards/phycard-i.MX27/env/config | 48 ---------------------- .../boards/phycard-i.MX27/env/init/mtdparts-nand | 11 +++++ arch/arm/mach-imx/Kconfig | 1 + 3 files changed, 12 insertions(+), 48 deletions(-) delete mode 100644 arch/arm/boards/phycard-i.MX27/env/config create mode 100644 arch/arm/boards/phycard-i.MX27/env/init/mtdparts-nand (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/boards/phycard-i.MX27/env/config b/arch/arm/boards/phycard-i.MX27/env/config deleted file mode 100644 index 160cbe7c2d..0000000000 --- a/arch/arm/boards/phycard-i.MX27/env/config +++ /dev/null @@ -1,48 +0,0 @@ -#!/bin/sh - -eth0.serverip= -user= - -# use 'dhcp' to do dhcp in barebox and in kernel -# use 'none' if you want to skip kernel ip autoconfiguration -ip=dhcp - -# or set your networking parameters here -#eth0.ipaddr=a.b.c.d -#eth0.netmask=a.b.c.d -#eth0.gateway=a.b.c.d -#eth0.serverip=a.b.c.d - -# can be either 'nfs', 'tftp', 'nor' or 'nand' -kernel_loc=tftp -# can be either 'net', 'nor', 'nand' or 'initrd' -rootfs_loc=net - -# can be either 'jffs2' or 'ubifs' -rootfs_type=ubifs -rootfsimage=root-${global.hostname}.$rootfs_type - -kernelimage=zImage-${global.hostname} -#kernelimage=uImage-${global.hostname} -#kernelimage=Image-${global.hostname} -#kernelimage=Image-${global.hostname}.lzo - -if [ -n $user ]; then - kernelimage="$user"-"$kernelimage" - nfsroot="$eth0.serverip:/home/$user/nfsroot/${global.hostname}" - rootfsimage="$user"-"$rootfsimage" -else - nfsroot="$eth0.serverip:/path/to/nfs/root" -fi - -autoboot_timeout=3 - -bootargs="console=ttymxc0,115200" - -nand_parts="512k(barebox)ro,512k(bareboxenv),4M(kernel),-(root)" -rootfs_mtdblock_nand=7 - -# set a fancy prompt (if support is compiled in) -PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " - - diff --git a/arch/arm/boards/phycard-i.MX27/env/init/mtdparts-nand b/arch/arm/boards/phycard-i.MX27/env/init/mtdparts-nand new file mode 100644 index 0000000000..e2dcfab49a --- /dev/null +++ b/arch/arm/boards/phycard-i.MX27/env/init/mtdparts-nand @@ -0,0 +1,11 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "NAND partitions" + exit +fi + +mtdparts="512k(nand0.barebox),512k(nand0.bareboxenv),4M(nand0.kernel),-(nand0.root)" +kernelname="mxc_nand" + +mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index de0b9ace1a..81ce3084c5 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -314,6 +314,7 @@ config MACH_IMX27ADS config MACH_PCA100 bool "phyCard-i.MX27" select ARCH_IMX27 + select HAVE_DEFAULT_ENVIRONMENT_NEW help Say Y here if you are using Phytec's phyCard-i.MX27 (pca100) equipped with a Freescale i.MX27 Processor -- cgit v1.2.3 From 084a99446604a612fd69f9500a46a716bd9b8042 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 17 Jan 2014 09:57:16 +0100 Subject: ARM: i.MX27: Add missing MPLL clock sources The MPLL can be driven from the low frequency reference clock. This is the reset default. Currently the clock code assumes this has been changed from the lowlevel code. If that didn't happen we get wrong clock rates. This adds the missing clocks so that we get correct clock rates. Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/clk-imx27.c | 44 ++++++++++++++++++++++++++++++++++++++----- 1 file changed, 39 insertions(+), 5 deletions(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c index 6fd3cd6fc8..c7922612e2 100644 --- a/arch/arm/mach-imx/clk-imx27.c +++ b/arch/arm/mach-imx/clk-imx27.c @@ -92,8 +92,23 @@ enum mx27_clks { dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div, - per2_div, per3_div, per4_div, usb_div, cpu_sel, clko_sel, cpu_div, clko_div, - clko_en, lcdc_per_gate, lcdc_ahb_gate, lcdc_ipg_gate, clk_max + per2_div, per3_div, per4_div, vpu_sel, vpu_div, usb_div, cpu_sel, + clko_sel, cpu_div, clko_div, ssi1_sel, ssi2_sel, ssi1_div, ssi2_div, + clko_en, ssi2_ipg_gate, ssi1_ipg_gate, slcdc_ipg_gate, sdhc3_ipg_gate, + sdhc2_ipg_gate, sdhc1_ipg_gate, scc_ipg_gate, sahara_ipg_gate, + rtc_ipg_gate, pwm_ipg_gate, owire_ipg_gate, lcdc_ipg_gate, + kpp_ipg_gate, iim_ipg_gate, i2c2_ipg_gate, i2c1_ipg_gate, + gpt6_ipg_gate, gpt5_ipg_gate, gpt4_ipg_gate, gpt3_ipg_gate, + gpt2_ipg_gate, gpt1_ipg_gate, gpio_ipg_gate, fec_ipg_gate, + emma_ipg_gate, dma_ipg_gate, cspi3_ipg_gate, cspi2_ipg_gate, + cspi1_ipg_gate, nfc_baud_gate, ssi2_baud_gate, ssi1_baud_gate, + vpu_baud_gate, per4_gate, per3_gate, per2_gate, per1_gate, + usb_ahb_gate, slcdc_ahb_gate, sahara_ahb_gate, lcdc_ahb_gate, + vpu_ahb_gate, fec_ahb_gate, emma_ahb_gate, emi_ahb_gate, dma_ahb_gate, + csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate, + uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate, + uart2_ipg_gate, uart1_ipg_gate, ckih_div1p5, fpm, mpll_osc_sel, + mpll_sel, spll_gate, clk_max }; static struct clk *clks[clk_max]; @@ -103,6 +118,16 @@ static const char *cpu_sel_clks[] = { "mpll", }; +static const char *mpll_sel_clks[] = { + "fpm", + "mpll_osc_sel", +}; + +static const char *mpll_osc_sel_clks[] = { + "ckih", + "ckih_div1p5", +}; + static const char *clko_sel_clks[] = { "ckil", NULL, @@ -152,7 +177,16 @@ static int imx27_ccm_probe(struct device_d *dev) clks[dummy] = clk_fixed("dummy", 0); clks[ckih] = clk_fixed("ckih", 26000000); clks[ckil] = clk_fixed("ckil", 32768); - clks[mpll] = imx_clk_pllv1("mpll", "ckih", base + CCM_MPCTL0); + clks[fpm] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1); + clks[ckih_div1p5] = imx_clk_fixed_factor("ckih_div1p5", "ckih", 2, 3); + + clks[mpll_osc_sel] = imx_clk_mux("mpll_osc_sel", base + CCM_CSCR, 4, 1, + mpll_osc_sel_clks, + ARRAY_SIZE(mpll_osc_sel_clks)); + clks[mpll_sel] = imx_clk_mux("mpll_sel", base + CCM_CSCR, 16, 1, mpll_sel_clks, + ARRAY_SIZE(mpll_sel_clks)); + + clks[mpll] = imx_clk_pllv1("mpll", "mpll_sel", base + CCM_MPCTL0); clks[spll] = imx_clk_pllv1("spll", "ckih", base + CCM_SPCTL0); clks[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3); @@ -179,7 +213,7 @@ static int imx27_ccm_probe(struct device_d *dev) else clks[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", base + CCM_CSCR, 13, 3); clks[clko_div] = imx_clk_divider("clko_div", "clko_sel", base + CCM_PCDR0, 22, 3); - clks[lcdc_per_gate] = imx_clk_gate("lcdc_per_gate", "per3_div", base + CCM_PCCR1, 8); + clks[per3_gate] = imx_clk_gate("per3_gate", "per3_div", base + CCM_PCCR1, 8); clks[lcdc_ahb_gate] = imx_clk_gate("lcdc_ahb_gate", "ahb", base + CCM_PCCR1, 15); clks[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", base + CCM_PCCR0, 14); @@ -203,7 +237,7 @@ static int imx27_ccm_probe(struct device_d *dev) clkdev_add_physbase(clks[per2_div], MX27_SDHC1_BASE_ADDR, NULL); clkdev_add_physbase(clks[per2_div], MX27_SDHC2_BASE_ADDR, NULL); clkdev_add_physbase(clks[per2_div], MX27_SDHC3_BASE_ADDR, NULL); - clkdev_add_physbase(clks[lcdc_per_gate], MX27_LCDC_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per3_gate], MX27_LCDC_BASE_ADDR, NULL); clkdev_add_physbase(clks[lcdc_ahb_gate], MX27_LCDC_BASE_ADDR, "ahb"); clkdev_add_physbase(clks[lcdc_ipg_gate], MX27_LCDC_BASE_ADDR, "ipg"); clkdev_add_physbase(clks[ipg], MX27_FEC_BASE_ADDR, NULL); -- cgit v1.2.3 From f1d83fad0677264f06026fd3d6873285573c9ec4 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 17 Jan 2014 11:17:45 +0100 Subject: ARM: i.MX: external NAND boot: factor out a 2k pagesize detection function Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/external-nand-boot.c | 65 +++++++++++++++++++++++----------- 1 file changed, 45 insertions(+), 20 deletions(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/external-nand-boot.c b/arch/arm/mach-imx/external-nand-boot.c index 1af46b78ea..a1221c834e 100644 --- a/arch/arm/mach-imx/external-nand-boot.c +++ b/arch/arm/mach-imx/external-nand-boot.c @@ -279,6 +279,46 @@ int __bare_init imx_barebox_boot_nand_external(unsigned long nfc_base) return 1; } +static inline int imx21_pagesize_2k(void) +{ + if (readl(MX21_SYSCTRL_BASE_ADDR + 0x14) & (1 << 5)) + return 1; + else + return 0; +} + +static inline int imx25_pagesize_2k(void) +{ + if (readl(MX25_CCM_BASE_ADDR + MX25_CCM_RCSR) & (1 << 8)) + return 1; + else + return 0; +} + +static inline int imx27_pagesize_2k(void) +{ + if (readl(MX27_SYSCTRL_BASE_ADDR + 0x14) & (1 << 5)) + return 1; + else + return 0; +} + +static inline int imx31_pagesize_2k(void) +{ + if (readl(MX31_CCM_BASE_ADDR + MX31_CCM_RCSR) & MX31_RCSR_NFMS) + return 1; + else + return 0; +} + +static inline int imx35_pagesize_2k(void) +{ + if (readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR) & (1 << 8)) + return 1; + else + return 0; +} + #define BARE_INIT_FUNCTION(name) \ void __noreturn __section(.text_bare_init_##name) \ name @@ -298,10 +338,7 @@ BARE_INIT_FUNCTION(imx21_barebox_boot_nand_external)(void) if (imx_barebox_boot_nand_external(nfc_base)) { jump_sdram(nfc_base - ld_var(_text)); - if (readl(MX21_SYSCTRL_BASE_ADDR + 0x14) & (1 << 5)) - pagesize_2k = 1; - else - pagesize_2k = 0; + pagesize_2k = imx21_pagesize_2k(); imx_nand_load_image((void *)ld_var(_text), ld_var(barebox_image_size), @@ -321,10 +358,7 @@ BARE_INIT_FUNCTION(imx25_barebox_boot_nand_external)(void) if (imx_barebox_boot_nand_external(nfc_base)) { jump_sdram(nfc_base - ld_var(_text)); - if (readl(MX25_CCM_BASE_ADDR + MX25_CCM_RCSR) & (1 << 8)) - pagesize_2k = 1; - else - pagesize_2k = 0; + pagesize_2k = imx25_pagesize_2k(); imx_nand_load_image((void *)ld_var(_text), ld_var(_barebox_image_size), @@ -342,10 +376,7 @@ BARE_INIT_FUNCTION(imx27_barebox_boot_nand_external)(void) if (imx_barebox_boot_nand_external(nfc_base)) { jump_sdram(nfc_base - ld_var(_text)); - if (readl(MX27_SYSCTRL_BASE_ADDR + 0x14) & (1 << 5)) - pagesize_2k = 1; - else - pagesize_2k = 0; + pagesize_2k = imx27_pagesize_2k(); imx_nand_load_image((void *)ld_var(_text), ld_var(_barebox_image_size), @@ -363,10 +394,7 @@ BARE_INIT_FUNCTION(imx31_barebox_boot_nand_external)(void) if (imx_barebox_boot_nand_external(nfc_base)) { jump_sdram(nfc_base - ld_var(_text)); - if (readl(MX31_CCM_BASE_ADDR + MX31_CCM_RCSR) & MX31_RCSR_NFMS) - pagesize_2k = 1; - else - pagesize_2k = 0; + pagesize_2k = imx31_pagesize_2k(); imx_nand_load_image((void *)ld_var(_text), ld_var(_barebox_image_size), @@ -384,10 +412,7 @@ BARE_INIT_FUNCTION(imx35_barebox_boot_nand_external)(void) if (imx_barebox_boot_nand_external(nfc_base)) { jump_sdram(nfc_base - ld_var(_text)); - if (readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR) & (1 << 8)) - pagesize_2k = 1; - else - pagesize_2k = 0; + pagesize_2k = imx35_pagesize_2k(); imx_nand_load_image((void *)ld_var(_text), ld_var(_barebox_image_size), -- cgit v1.2.3 From 9399c7444d8f04e449a0c7d54c99aa437a13ca22 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 17 Jan 2014 11:22:06 +0100 Subject: ARM: i.MX: external NAND boot: create function macro for different SoCs Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/external-nand-boot.c | 112 +++++++-------------------------- 1 file changed, 23 insertions(+), 89 deletions(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/external-nand-boot.c b/arch/arm/mach-imx/external-nand-boot.c index a1221c834e..4d86ab9d48 100644 --- a/arch/arm/mach-imx/external-nand-boot.c +++ b/arch/arm/mach-imx/external-nand-boot.c @@ -329,95 +329,29 @@ static inline int imx35_pagesize_2k(void) * NAND. In this case the booting is continued without loading an image from * NAND. This function needs a stack to be set up. */ -#ifdef BROKEN -BARE_INIT_FUNCTION(imx21_barebox_boot_nand_external)(void) -{ - unsigned long nfc_base = MX21_NFC_BASE_ADDR; - int pagesize_2k; - - if (imx_barebox_boot_nand_external(nfc_base)) { - jump_sdram(nfc_base - ld_var(_text)); - - pagesize_2k = imx21_pagesize_2k(); - - imx_nand_load_image((void *)ld_var(_text), - ld_var(barebox_image_size), - (void *)nfc_base, pagesize_2k); - } - - /* This function doesn't exist yet */ - imx21_barebox_entry(0); -} -#endif - -BARE_INIT_FUNCTION(imx25_barebox_boot_nand_external)(void) -{ - unsigned long nfc_base = MX25_NFC_BASE_ADDR; - int pagesize_2k; - - if (imx_barebox_boot_nand_external(nfc_base)) { - jump_sdram(nfc_base - ld_var(_text)); - - pagesize_2k = imx25_pagesize_2k(); - - imx_nand_load_image((void *)ld_var(_text), - ld_var(_barebox_image_size), - (void *)nfc_base, pagesize_2k); - } - - imx25_barebox_entry(0); -} - -BARE_INIT_FUNCTION(imx27_barebox_boot_nand_external)(void) -{ - unsigned long nfc_base = MX27_NFC_BASE_ADDR; - int pagesize_2k; - - if (imx_barebox_boot_nand_external(nfc_base)) { - jump_sdram(nfc_base - ld_var(_text)); - pagesize_2k = imx27_pagesize_2k(); - - imx_nand_load_image((void *)ld_var(_text), - ld_var(_barebox_image_size), - (void *)nfc_base, pagesize_2k); - } - - imx27_barebox_entry(0); -} - -BARE_INIT_FUNCTION(imx31_barebox_boot_nand_external)(void) -{ - unsigned long nfc_base = MX31_NFC_BASE_ADDR; - int pagesize_2k; - - if (imx_barebox_boot_nand_external(nfc_base)) { - jump_sdram(nfc_base - ld_var(_text)); - - pagesize_2k = imx31_pagesize_2k(); - - imx_nand_load_image((void *)ld_var(_text), - ld_var(_barebox_image_size), - (void *)nfc_base, pagesize_2k); - } - - imx31_barebox_entry(0); +#define DEFINE_EXTERNAL_NAND_ENTRY(soc) \ + \ +BARE_INIT_FUNCTION(imx##soc##_barebox_boot_nand_external)(void) \ +{ \ + unsigned long nfc_base = MX##soc##_NFC_BASE_ADDR; \ + \ + if (imx_barebox_boot_nand_external(nfc_base)) { \ + jump_sdram(nfc_base - ld_var(_text)); \ + \ + imx_nand_load_image((void *)ld_var(_text), \ + ld_var(_barebox_image_size), \ + (void *)nfc_base, \ + imx##soc##_pagesize_2k()); \ + } \ + \ + imx##soc##_barebox_entry(0); \ } -BARE_INIT_FUNCTION(imx35_barebox_boot_nand_external)(void) -{ - unsigned long nfc_base = MX35_NFC_BASE_ADDR; - int pagesize_2k; - - if (imx_barebox_boot_nand_external(nfc_base)) { - jump_sdram(nfc_base - ld_var(_text)); - - pagesize_2k = imx35_pagesize_2k(); - - imx_nand_load_image((void *)ld_var(_text), - ld_var(_barebox_image_size), - (void *)nfc_base, pagesize_2k); - } - - imx35_barebox_entry(0); -} +#ifdef BROKEN +DEFINE_EXTERNAL_NAND_ENTRY(21) +#endif +DEFINE_EXTERNAL_NAND_ENTRY(25) +DEFINE_EXTERNAL_NAND_ENTRY(27) +DEFINE_EXTERNAL_NAND_ENTRY(31) +DEFINE_EXTERNAL_NAND_ENTRY(35) -- cgit v1.2.3 From f77e5b938564b3d1193b55bbab42d79449699397 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 17 Jan 2014 12:01:52 +0100 Subject: ARM: i.MX: external NAND boot: make it work with relocatable PBL We used to copy the initial binary portion from NFC SRAM to TEXT_BASE and jumped there. With relocatable PBL TEXT_BASE becomes 0, so this doesn't work. This is changed to copy the initial binary portion to the beginning of SDRAM instead. Tested on Phytec phyCARD-i.MX27 and Karo TX25 with and without relocatable pbl. Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/external-nand-boot.c | 107 +++++++++++++++------------------ 1 file changed, 50 insertions(+), 57 deletions(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/external-nand-boot.c b/arch/arm/mach-imx/external-nand-boot.c index 4d86ab9d48..8c88e4bb23 100644 --- a/arch/arm/mach-imx/external-nand-boot.c +++ b/arch/arm/mach-imx/external-nand-boot.c @@ -28,6 +28,10 @@ #include #include +#define BARE_INIT_FUNCTION(name) \ + __section(.text_bare_init_##name) \ + name + static void __bare_init noinline imx_nandboot_wait_op_done(void *regs) { u32 r; @@ -235,50 +239,6 @@ void __bare_init imx_nand_load_image(void *dest, int size, void __iomem *base, } } -/* - * This function assumes the currently running binary has been - * copied from its current position to an offset. It returns - * to the calling function - offset. - * NOTE: The calling function may not return itself since it still - * works on the old content of the lr register. Only call this - * from a __noreturn function. - */ -static __bare_init __naked void jump_sdram(unsigned long offset) -{ - flush_icache(); - - __asm__ __volatile__ ( - "sub lr, lr, %0;" - "mov pc, lr;" : : "r"(offset) - ); -} - -/* - * Load and start barebox from NAND. This function also checks if we are really - * running inside the NFC address space. If not, barebox is started from the - * currently running address without loading anything from NAND. - */ -int __bare_init imx_barebox_boot_nand_external(unsigned long nfc_base) -{ - u32 r; - u32 *src, *trg; - int i; - - /* skip NAND boot if not running from NFC space */ - r = get_pc(); - if (r < nfc_base || r > nfc_base + 0x800) - return 0; - - src = (unsigned int *)nfc_base; - trg = (unsigned int *)ld_var(_text); - - /* Move ourselves out of NFC SRAM */ - for (i = 0; i < 0x800 / sizeof(int); i++) - *trg++ = *src++; - - return 1; -} - static inline int imx21_pagesize_2k(void) { if (readl(MX21_SYSCTRL_BASE_ADDR + 0x14) & (1 << 5)) @@ -319,10 +279,6 @@ static inline int imx35_pagesize_2k(void) return 0; } -#define BARE_INIT_FUNCTION(name) \ - void __noreturn __section(.text_bare_init_##name) \ - name - /* * SoC specific entries for booting in external NAND mode. To be called from * the board specific entry code. This is safe to call even if not booting from @@ -332,20 +288,57 @@ static inline int imx35_pagesize_2k(void) #define DEFINE_EXTERNAL_NAND_ENTRY(soc) \ \ -BARE_INIT_FUNCTION(imx##soc##_barebox_boot_nand_external)(void) \ +void __noreturn BARE_INIT_FUNCTION(imx##soc##_boot_nand_external_cont)(void) \ { \ unsigned long nfc_base = MX##soc##_NFC_BASE_ADDR; \ + unsigned long sdram = MX##soc##_CSD0_BASE_ADDR; \ + \ + imx_nand_load_image((void *)sdram, \ + ld_var(_barebox_image_size), \ + (void *)nfc_base, \ + imx##soc##_pagesize_2k()); \ + \ + imx##soc##_barebox_entry(0); \ +} \ + \ +void __noreturn BARE_INIT_FUNCTION(imx##soc##_barebox_boot_nand_external)(void) \ +{ \ + unsigned long nfc_base = MX##soc##_NFC_BASE_ADDR; \ + unsigned long sdram = MX##soc##_CSD0_BASE_ADDR; \ + unsigned long __fn; \ + u32 r; \ + u32 *src, *trg; \ + int i; \ + void __noreturn (*fn)(void); \ + \ + /* skip NAND boot if not running from NFC space */ \ + r = get_pc(); \ + if (r < nfc_base || r > nfc_base + 0x800) \ + imx##soc##_barebox_entry(0); \ + \ + src = (unsigned int *)nfc_base; \ + trg = (unsigned int *)sdram; \ + \ + /* \ + * Copy initial binary portion from NFC SRAM to beginning of \ + * SDRAM \ + */ \ + for (i = 0; i < 0x800 / sizeof(int); i++) \ + *trg++ = *src++; \ \ - if (imx_barebox_boot_nand_external(nfc_base)) { \ - jump_sdram(nfc_base - ld_var(_text)); \ + /* The next function we jump to */ \ + __fn = (unsigned long)imx##soc##_boot_nand_external_cont; \ + /* mask out TEXT_BASE */ \ + __fn &= 0x7ff; \ + /* \ + * and add sdram base instead where we copied the initial \ + * binary above \ + */ \ + __fn += sdram; \ \ - imx_nand_load_image((void *)ld_var(_text), \ - ld_var(_barebox_image_size), \ - (void *)nfc_base, \ - imx##soc##_pagesize_2k()); \ - } \ + fn = (void *)__fn; \ \ - imx##soc##_barebox_entry(0); \ + fn(); \ } #ifdef BROKEN -- cgit v1.2.3 From 35ae916ecfcf44125394acb37778ebb90e876e78 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 28 Jan 2014 08:54:18 +0100 Subject: ARM: i.MX: external NAND boot: do not depend on cpu_is_* With multiboard support the cpu_is_* macros are no longer compile time generated and do not work in early code, so pass a v1 variable around. Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/external-nand-boot.c | 58 ++++++++++++++++++++++++++-------- 1 file changed, 44 insertions(+), 14 deletions(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/external-nand-boot.c b/arch/arm/mach-imx/external-nand-boot.c index 8c88e4bb23..7760d8d175 100644 --- a/arch/arm/mach-imx/external-nand-boot.c +++ b/arch/arm/mach-imx/external-nand-boot.c @@ -95,12 +95,12 @@ static void __bare_init imx_nandboot_nfc_addr(void *regs, u32 offs, int pagesize } } -static void __bare_init imx_nandboot_send_page(void *regs, +static void __bare_init imx_nandboot_send_page(void *regs, int v1, unsigned int ops, int pagesize_2k) { int bufs, i; - if (nfc_is_v1() && pagesize_2k) + if (v1 && pagesize_2k) bufs = 4; else bufs = 1; @@ -126,15 +126,15 @@ static void __bare_init __memcpy32(void *trg, const void *src, int size) *t++ = *s++; } -static noinline void __bare_init imx_nandboot_get_page(void *regs, +static noinline void __bare_init imx_nandboot_get_page(void *regs, int v1, u32 offs, int pagesize_2k) { imx_nandboot_send_cmd(regs, NAND_CMD_READ0); imx_nandboot_nfc_addr(regs, offs, pagesize_2k); - imx_nandboot_send_page(regs, NFC_OUTPUT, pagesize_2k); + imx_nandboot_send_page(regs, v1, NFC_OUTPUT, pagesize_2k); } -void __bare_init imx_nand_load_image(void *dest, int size, void __iomem *base, +void __bare_init imx_nand_load_image(void *dest, int v1, int size, void __iomem *base, int pagesize_2k) { u32 tmp, page, block, blocksize, pagesize, badblocks; @@ -149,12 +149,12 @@ void __bare_init imx_nand_load_image(void *dest, int size, void __iomem *base, blocksize = 16 * 1024; } - if (nfc_is_v21()) { - regs = base + 0x1e00; - spare0 = base + 0x1000; - } else if (nfc_is_v1()) { + if (v1) { regs = base + 0xe00; spare0 = base + 0x800; + } else { + regs = base + 0x1e00; + spare0 = base + 0x1000; } imx_nandboot_send_cmd(regs, NAND_CMD_RESET); @@ -168,13 +168,13 @@ void __bare_init imx_nand_load_image(void *dest, int size, void __iomem *base, tmp = readw(regs + NFC_V1_V2_CONFIG1); tmp |= NFC_V1_V2_CONFIG1_ECC_EN; - if (nfc_is_v21()) + if (!v1) /* currently no support for 218 byte OOB with stronger ECC */ tmp |= NFC_V2_CONFIG1_ECC_MODE_4; tmp &= ~(NFC_V1_V2_CONFIG1_SP_EN | NFC_V1_V2_CONFIG1_INT_MSK); writew(tmp, regs + NFC_V1_V2_CONFIG1); - if (nfc_is_v21()) { + if (!v1) { if (pagesize_2k) writew(NFC_V2_SPAS_SPARESIZE(64), regs + NFC_V2_SPAS); else @@ -196,7 +196,7 @@ void __bare_init imx_nand_load_image(void *dest, int size, void __iomem *base, while (1) { page = 0; - imx_nandboot_get_page(regs, block * blocksize + + imx_nandboot_get_page(regs, v1, block * blocksize + page * pagesize, pagesize_2k); if (bbt) { @@ -223,7 +223,7 @@ void __bare_init imx_nand_load_image(void *dest, int size, void __iomem *base, block * blocksize + page * pagesize); if (page) - imx_nandboot_get_page(regs, block * blocksize + + imx_nandboot_get_page(regs, v1, block * blocksize + page * pagesize, pagesize_2k); page++; @@ -239,6 +239,36 @@ void __bare_init imx_nand_load_image(void *dest, int size, void __iomem *base, } } +void BARE_INIT_FUNCTION(imx21_nand_load_image)(void *dest, int size, + void __iomem *base, int pagesize_2k) +{ + imx_nand_load_image(dest, 1, size, base, pagesize_2k); +} + +void BARE_INIT_FUNCTION(imx25_nand_load_image)(void *dest, int size, + void __iomem *base, int pagesize_2k) +{ + imx_nand_load_image(dest, 0, size, base, pagesize_2k); +} + +void BARE_INIT_FUNCTION(imx27_nand_load_image)(void *dest, int size, + void __iomem *base, int pagesize_2k) +{ + imx_nand_load_image(dest, 1, size, base, pagesize_2k); +} + +void BARE_INIT_FUNCTION(imx31_nand_load_image)(void *dest, int size, + void __iomem *base, int pagesize_2k) +{ + imx_nand_load_image(dest, 1, size, base, pagesize_2k); +} + +void BARE_INIT_FUNCTION(imx35_nand_load_image)(void *dest, int size, + void __iomem *base, int pagesize_2k) +{ + imx_nand_load_image(dest, 0, size, base, pagesize_2k); +} + static inline int imx21_pagesize_2k(void) { if (readl(MX21_SYSCTRL_BASE_ADDR + 0x14) & (1 << 5)) @@ -293,7 +323,7 @@ void __noreturn BARE_INIT_FUNCTION(imx##soc##_boot_nand_external_cont)(void) unsigned long nfc_base = MX##soc##_NFC_BASE_ADDR; \ unsigned long sdram = MX##soc##_CSD0_BASE_ADDR; \ \ - imx_nand_load_image((void *)sdram, \ + imx##soc##_nand_load_image((void *)sdram, \ ld_var(_barebox_image_size), \ (void *)nfc_base, \ imx##soc##_pagesize_2k()); \ -- cgit v1.2.3 From c5b79860899c50e04b21c9fee1b319dbdf10d398 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 17 Jan 2014 12:41:21 +0100 Subject: ARM: i.MX: external NAND boot: pass boarddata Signed-off-by: Sascha Hauer --- arch/arm/boards/eukrea_cpuimx25/lowlevel.c | 2 +- arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S | 1 + arch/arm/boards/eukrea_cpuimx35/lowlevel.c | 2 +- arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S | 1 + arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S | 1 + arch/arm/boards/guf-cupid/lowlevel.c | 2 +- arch/arm/boards/guf-neso/lowlevel.c | 2 +- arch/arm/boards/karo-tx25/lowlevel.c | 2 +- arch/arm/boards/pcm037/lowlevel.c | 2 +- arch/arm/boards/pcm038/lowlevel.c | 2 +- arch/arm/boards/pcm043/lowlevel.c | 2 +- arch/arm/boards/phycard-i.MX27/lowlevel.c | 2 +- arch/arm/mach-imx/external-nand-boot.c | 14 ++++++++------ arch/arm/mach-imx/include/mach/imx-nand.h | 10 +++++----- 14 files changed, 25 insertions(+), 20 deletions(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c index 11d990dfd9..07659f53fc 100644 --- a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c +++ b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c @@ -131,7 +131,7 @@ void __bare_init __naked barebox_arm_reset_vector(void) /* setup a stack to be able to call imx25_barebox_boot_nand_external() */ arm_setup_stack(STACK_BASE + STACK_SIZE - 12); - imx25_barebox_boot_nand_external(); + imx25_barebox_boot_nand_external(0); #endif out: imx25_barebox_entry(0); diff --git a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S index a85b00d910..ae1391c283 100644 --- a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S +++ b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S @@ -127,6 +127,7 @@ barebox_arm_reset_vector: /* Setup a temporary stack in SDRAM */ ldr sp, =MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 4; + mov r0, #0 b imx27_barebox_boot_nand_external #endif /* CONFIG_NAND_IMX_BOOT */ diff --git a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c index a667e4c5eb..d03e1109d9 100644 --- a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c +++ b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c @@ -140,7 +140,7 @@ void __bare_init __naked barebox_arm_reset_vector(void) /* setup a stack to be able to call imx35_barebox_boot_nand_external() */ arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8); - imx35_barebox_boot_nand_external(); + imx35_barebox_boot_nand_external(0); #endif out: imx35_barebox_entry(0); diff --git a/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S b/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S index 174262d193..8446c6f1db 100644 --- a/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S +++ b/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S @@ -101,6 +101,7 @@ barebox_arm_reset_vector: /* Setup a temporary stack in SRAM */ ldr sp, =MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 4 + mov r0, #0 b imx25_barebox_boot_nand_external #endif /* CONFIG_NAND_IMX_BOOT */ diff --git a/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S b/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S index 2844465f39..cb9ed0ab6e 100644 --- a/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S +++ b/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S @@ -158,6 +158,7 @@ barebox_arm_reset_vector: /* Setup a temporary stack in internal SRAM */ ldr sp, =MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 4 + mov r0, #0 b imx35_barebox_boot_nand_external #endif /* CONFIG_NAND_IMX_BOOT */ diff --git a/arch/arm/boards/guf-cupid/lowlevel.c b/arch/arm/boards/guf-cupid/lowlevel.c index d5298c1836..d5dce16507 100644 --- a/arch/arm/boards/guf-cupid/lowlevel.c +++ b/arch/arm/boards/guf-cupid/lowlevel.c @@ -316,7 +316,7 @@ void __bare_init __naked barebox_arm_reset_vector(void) /* setup a stack to be able to call imx35_barebox_boot_nand_external() */ arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8); - imx35_barebox_boot_nand_external(); + imx35_barebox_boot_nand_external(0); #endif out: imx35_barebox_entry(0); diff --git a/arch/arm/boards/guf-neso/lowlevel.c b/arch/arm/boards/guf-neso/lowlevel.c index 386751d5ef..c3323ee1ea 100644 --- a/arch/arm/boards/guf-neso/lowlevel.c +++ b/arch/arm/boards/guf-neso/lowlevel.c @@ -90,7 +90,7 @@ void __bare_init __naked barebox_arm_reset_vector(void) /* setup a stack to be able to call imx27_barebox_boot_nand_external() */ arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 8); - imx27_barebox_boot_nand_external(); + imx27_barebox_boot_nand_external(0); #endif out: imx27_barebox_entry(0); diff --git a/arch/arm/boards/karo-tx25/lowlevel.c b/arch/arm/boards/karo-tx25/lowlevel.c index 742100d0ab..11f4138d2f 100644 --- a/arch/arm/boards/karo-tx25/lowlevel.c +++ b/arch/arm/boards/karo-tx25/lowlevel.c @@ -161,7 +161,7 @@ void __bare_init __naked barebox_arm_reset_vector(void) /* setup a stack to be able to call imx25_barebox_boot_nand_external() */ arm_setup_stack(MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 8); - imx25_barebox_boot_nand_external(); + imx25_barebox_boot_nand_external(0); #endif out: imx25_barebox_entry(0); diff --git a/arch/arm/boards/pcm037/lowlevel.c b/arch/arm/boards/pcm037/lowlevel.c index b81a24f0cd..ae2d8c0375 100644 --- a/arch/arm/boards/pcm037/lowlevel.c +++ b/arch/arm/boards/pcm037/lowlevel.c @@ -129,7 +129,7 @@ void __bare_init __naked barebox_arm_reset_vector(void) /* setup a stack to be able to call imx31_barebox_boot_nand_external() */ arm_setup_stack(MX31_IRAM_BASE_ADDR + MX31_IRAM_SIZE - 12); - imx31_barebox_boot_nand_external(); + imx31_barebox_boot_nand_external(0); #else imx31_barebox_entry(0); #endif diff --git a/arch/arm/boards/pcm038/lowlevel.c b/arch/arm/boards/pcm038/lowlevel.c index 0ea293981b..bb948f1c14 100644 --- a/arch/arm/boards/pcm038/lowlevel.c +++ b/arch/arm/boards/pcm038/lowlevel.c @@ -97,7 +97,7 @@ void __bare_init __naked barebox_arm_reset_vector(void) /* setup a stack to be able to call mx27_barebox_boot_nand_external() */ arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 8); - imx27_barebox_boot_nand_external(); + imx27_barebox_boot_nand_external(0); #endif out: imx27_barebox_entry(0); diff --git a/arch/arm/boards/pcm043/lowlevel.c b/arch/arm/boards/pcm043/lowlevel.c index ebd6b29543..64b03823f6 100644 --- a/arch/arm/boards/pcm043/lowlevel.c +++ b/arch/arm/boards/pcm043/lowlevel.c @@ -192,7 +192,7 @@ void __bare_init __naked barebox_arm_reset_vector(void) /* setup a stack to be able to call imx35_barebox_boot_nand_external() */ arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8); - imx35_barebox_boot_nand_external(); + imx35_barebox_boot_nand_external(0); #endif out: imx35_barebox_entry(0); diff --git a/arch/arm/boards/phycard-i.MX27/lowlevel.c b/arch/arm/boards/phycard-i.MX27/lowlevel.c index 9f5dfff16e..33de1c0423 100644 --- a/arch/arm/boards/phycard-i.MX27/lowlevel.c +++ b/arch/arm/boards/phycard-i.MX27/lowlevel.c @@ -100,7 +100,7 @@ void __bare_init __naked barebox_arm_reset_vector(void) sdram_init(); #ifdef CONFIG_NAND_IMX_BOOT - imx27_barebox_boot_nand_external(); + imx27_barebox_boot_nand_external(0); #else imx27_barebox_entry(0); #endif diff --git a/arch/arm/mach-imx/external-nand-boot.c b/arch/arm/mach-imx/external-nand-boot.c index 7760d8d175..fab37bf77a 100644 --- a/arch/arm/mach-imx/external-nand-boot.c +++ b/arch/arm/mach-imx/external-nand-boot.c @@ -318,7 +318,8 @@ static inline int imx35_pagesize_2k(void) #define DEFINE_EXTERNAL_NAND_ENTRY(soc) \ \ -void __noreturn BARE_INIT_FUNCTION(imx##soc##_boot_nand_external_cont)(void) \ +void __noreturn BARE_INIT_FUNCTION(imx##soc##_boot_nand_external_cont) \ + (uint32_t boarddata) \ { \ unsigned long nfc_base = MX##soc##_NFC_BASE_ADDR; \ unsigned long sdram = MX##soc##_CSD0_BASE_ADDR; \ @@ -328,10 +329,11 @@ void __noreturn BARE_INIT_FUNCTION(imx##soc##_boot_nand_external_cont)(void) (void *)nfc_base, \ imx##soc##_pagesize_2k()); \ \ - imx##soc##_barebox_entry(0); \ + imx##soc##_barebox_entry(boarddata); \ } \ \ -void __noreturn BARE_INIT_FUNCTION(imx##soc##_barebox_boot_nand_external)(void) \ +void __noreturn BARE_INIT_FUNCTION(imx##soc##_barebox_boot_nand_external) \ + (uint32_t boarddata) \ { \ unsigned long nfc_base = MX##soc##_NFC_BASE_ADDR; \ unsigned long sdram = MX##soc##_CSD0_BASE_ADDR; \ @@ -339,12 +341,12 @@ void __noreturn BARE_INIT_FUNCTION(imx##soc##_barebox_boot_nand_external)(void) u32 r; \ u32 *src, *trg; \ int i; \ - void __noreturn (*fn)(void); \ + void __noreturn (*fn)(uint32_t); \ \ /* skip NAND boot if not running from NFC space */ \ r = get_pc(); \ if (r < nfc_base || r > nfc_base + 0x800) \ - imx##soc##_barebox_entry(0); \ + imx##soc##_barebox_entry(boarddata); \ \ src = (unsigned int *)nfc_base; \ trg = (unsigned int *)sdram; \ @@ -368,7 +370,7 @@ void __noreturn BARE_INIT_FUNCTION(imx##soc##_barebox_boot_nand_external)(void) \ fn = (void *)__fn; \ \ - fn(); \ + fn(boarddata); \ } #ifdef BROKEN diff --git a/arch/arm/mach-imx/include/mach/imx-nand.h b/arch/arm/mach-imx/include/mach/imx-nand.h index 9e6416e4d4..972a0da5d7 100644 --- a/arch/arm/mach-imx/include/mach/imx-nand.h +++ b/arch/arm/mach-imx/include/mach/imx-nand.h @@ -3,11 +3,11 @@ #include -void imx21_barebox_boot_nand_external(void); -void imx25_barebox_boot_nand_external(void); -void imx27_barebox_boot_nand_external(void); -void imx31_barebox_boot_nand_external(void); -void imx35_barebox_boot_nand_external(void); +void imx21_barebox_boot_nand_external(uint32_t boarddata); +void imx25_barebox_boot_nand_external(uint32_t boarddata); +void imx27_barebox_boot_nand_external(uint32_t boarddata); +void imx31_barebox_boot_nand_external(uint32_t boarddata); +void imx35_barebox_boot_nand_external(uint32_t boarddata); void imx_nand_set_layout(int writesize, int datawidth); struct imx_nand_platform_data { -- cgit v1.2.3 From 14bb8cc21baacfed7f60f1a37737641af3827efb Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 17 Jan 2014 14:32:21 +0100 Subject: ARM: i.MX clocksource: return successful for multiple instances With multiple instances we returned -EBUSY which will provoke a log message. Return successful instead since the i.MX27 has multiple GPTs in the devicetree. Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/clocksource.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/clocksource.c b/arch/arm/mach-imx/clocksource.c index dc29d200c0..9f5ca568fd 100644 --- a/arch/arm/mach-imx/clocksource.c +++ b/arch/arm/mach-imx/clocksource.c @@ -97,7 +97,7 @@ static int imx_gpt_probe(struct device_d *dev) /* one timer is enough */ if (timer_base) - return -EBUSY; + return 0; ret = dev_get_drvdata(dev, (unsigned long *)®s); if (ret) -- cgit v1.2.3 From 2af8bdd36908658a33838008200856b30734543b Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 20 Jan 2014 12:39:40 +0100 Subject: ARM: i.MX53: tqma53: Switch to devicetree and multiboard support Signed-off-by: Sascha Hauer --- arch/arm/boards/tqma53/Makefile | 1 - arch/arm/boards/tqma53/board.c | 245 ++------------------- .../tqma53/flash-header-tq-tqma53-1gib.imxcfg | 5 + .../tqma53/flash-header-tq-tqma53-512mib.imxcfg | 5 + arch/arm/boards/tqma53/flash-header-tq-tqma53.h | 61 +++++ arch/arm/boards/tqma53/flash_header.c | 113 ---------- arch/arm/boards/tqma53/lowlevel.c | 58 ++++- arch/arm/configs/tqma53_defconfig | 19 +- arch/arm/dts/Makefile | 1 + arch/arm/mach-imx/Kconfig | 19 +- images/Makefile.imx | 10 + 11 files changed, 169 insertions(+), 368 deletions(-) create mode 100644 arch/arm/boards/tqma53/flash-header-tq-tqma53-1gib.imxcfg create mode 100644 arch/arm/boards/tqma53/flash-header-tq-tqma53-512mib.imxcfg create mode 100644 arch/arm/boards/tqma53/flash-header-tq-tqma53.h delete mode 100644 arch/arm/boards/tqma53/flash_header.c (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/boards/tqma53/Makefile b/arch/arm/boards/tqma53/Makefile index d44f697718..01c7a259e9 100644 --- a/arch/arm/boards/tqma53/Makefile +++ b/arch/arm/boards/tqma53/Makefile @@ -1,3 +1,2 @@ obj-y += board.o -lwl-y += flash_header.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/tqma53/board.c b/arch/arm/boards/tqma53/board.c index 9069f7c1cd..958e5ad1f0 100644 --- a/arch/arm/boards/tqma53/board.c +++ b/arch/arm/boards/tqma53/board.c @@ -13,251 +13,32 @@ * */ -#include #include -#include -#include -#include +#include +#include #include -#include -#include -#include -#include -#include -#include -#include #include -#include #include -#include -#include -#include -#include -#include -#include -#include - -static struct fec_platform_data fec_info = { - .xcv_type = PHY_INTERFACE_MODE_RMII, -}; - -static iomux_v3_cfg_t tqma53_pads[] = { - MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD, - MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC, - MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD, - MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS, - MX53_PAD_KEY_ROW2__CAN1_RXCAN, - MX53_PAD_KEY_COL2__CAN1_TXCAN, - MX53_PAD_KEY_ROW4__CAN2_RXCAN, - MX53_PAD_KEY_COL4__CAN2_TXCAN, - MX53_PAD_GPIO_19__CCM_CLKO, - MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK, - MX53_PAD_SD1_DATA0__CSPI_MISO, - MX53_PAD_SD1_CMD__CSPI_MOSI, - MX53_PAD_SD1_CLK__CSPI_SCLK, - MX53_PAD_SD1_DATA1__CSPI_SS0, - MX53_PAD_SD1_DATA2__CSPI_SS1, - MX53_PAD_SD1_DATA3__CSPI_SS2, - MX53_PAD_EIM_D17__ECSPI1_MISO, - MX53_PAD_EIM_D18__ECSPI1_MOSI, - MX53_PAD_EIM_D16__ECSPI1_SCLK, - MX53_PAD_EIM_EB2__ECSPI1_SS0, - MX53_PAD_EIM_D19__ECSPI1_SS1, - MX53_PAD_EIM_D24__ECSPI1_SS2, - MX53_PAD_EIM_D25__ECSPI1_SS3, - MX53_PAD_GPIO_4__ESDHC2_CD, - MX53_PAD_SD2_CLK__ESDHC2_CLK, - MX53_PAD_SD2_CMD__ESDHC2_CMD, - MX53_PAD_SD2_DATA0__ESDHC2_DAT0, - MX53_PAD_SD2_DATA1__ESDHC2_DAT1, - MX53_PAD_SD2_DATA2__ESDHC2_DAT2, - MX53_PAD_SD2_DATA3__ESDHC2_DAT3, - MX53_PAD_GPIO_2__ESDHC2_WP, - MX53_PAD_PATA_IORDY__ESDHC3_CLK, - MX53_PAD_PATA_RESET_B__ESDHC3_CMD, - MX53_PAD_PATA_DATA8__ESDHC3_DAT0, - MX53_PAD_PATA_DATA9__ESDHC3_DAT1, - MX53_PAD_PATA_DATA10__ESDHC3_DAT2, - MX53_PAD_PATA_DATA11__ESDHC3_DAT3, - MX53_PAD_PATA_DATA0__ESDHC3_DAT4, - MX53_PAD_PATA_DATA1__ESDHC3_DAT5, - MX53_PAD_PATA_DATA2__ESDHC3_DAT6, - MX53_PAD_PATA_DATA3__ESDHC3_DAT7, - MX53_PAD_FEC_MDC__FEC_MDC, - MX53_PAD_FEC_MDIO__FEC_MDIO, - MX53_PAD_FEC_RXD0__FEC_RDATA_0, - MX53_PAD_FEC_RXD1__FEC_RDATA_1, - MX53_PAD_FEC_CRS_DV__FEC_RX_DV, - MX53_PAD_FEC_RX_ER__FEC_RX_ER, - MX53_PAD_FEC_TXD0__FEC_TDATA_0, - MX53_PAD_FEC_TXD1__FEC_TDATA_1, - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, - MX53_PAD_FEC_TX_EN__FEC_TX_EN, - MX53_PAD_GPIO_7__FIRI_RXD, - MX53_PAD_GPIO_8__FIRI_TXD, - MX53_PAD_GPIO_0__GPIO1_0, - MX53_PAD_GPIO_3__GPIO1_3, - MX53_PAD_PATA_DATA14__GPIO2_14, - MX53_PAD_PATA_DATA15__GPIO2_15, - MX53_PAD_EIM_CS0__GPIO2_23, - MX53_PAD_EIM_OE__GPIO2_25, - MX53_PAD_EIM_RW__GPIO2_26, - MX53_PAD_EIM_LBA__GPIO2_27, - MX53_PAD_PATA_DATA5__GPIO2_5, - MX53_PAD_PATA_DATA6__GPIO2_6, - MX53_PAD_PATA_DATA7__GPIO2_7, - MX53_PAD_EIM_DA11__GPIO3_11, - MX53_PAD_EIM_DA12__GPIO3_12, - MX53_PAD_EIM_DA13__GPIO3_13, - MX53_PAD_EIM_DA14__GPIO3_14, - MX53_PAD_EIM_D20__GPIO3_20, - MX53_PAD_EIM_D21__GPIO3_21, - MX53_PAD_EIM_D22__GPIO3_22, - MX53_PAD_EIM_D28__GPIO3_28, - MX53_PAD_EIM_D29__GPIO3_29, - MX53_PAD_EIM_WAIT__GPIO5_0, - MX53_PAD_PATA_DA_1__GPIO7_7, - MX53_PAD_PATA_DA_2__GPIO7_8, - MX53_PAD_KEY_COL3__I2C2_SCL, - MX53_PAD_KEY_ROW3__I2C2_SDA, - MX53_PAD_GPIO_5__I2C3_SCL, - MX53_PAD_GPIO_6__I2C3_SDA, - MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10, - MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11, - MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12, - MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13, - MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14, - MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15, - MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16, - MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17, - MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18, - MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19, - MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4, - MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5, - MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6, - MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7, - MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8, - MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9, - MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN, - MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC, - MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK, - MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC, - MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK, - MX53_PAD_EIM_DA10__IPU_DI1_PIN15, - MX53_PAD_EIM_D23__IPU_DI1_PIN2, - MX53_PAD_EIM_EB3__IPU_DI1_PIN3, - MX53_PAD_EIM_DA15__IPU_DI1_PIN4, - MX53_PAD_EIM_CS1__IPU_DI1_PIN6, - MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0, - MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1, - MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10, - MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11, - MX53_PAD_EIM_A17__IPU_DISP1_DAT_12, - MX53_PAD_EIM_A18__IPU_DISP1_DAT_13, - MX53_PAD_EIM_A19__IPU_DISP1_DAT_14, - MX53_PAD_EIM_A20__IPU_DISP1_DAT_15, - MX53_PAD_EIM_A21__IPU_DISP1_DAT_16, - MX53_PAD_EIM_A22__IPU_DISP1_DAT_17, - MX53_PAD_EIM_A23__IPU_DISP1_DAT_18, - MX53_PAD_EIM_A24__IPU_DISP1_DAT_19, - MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2, - MX53_PAD_EIM_D31__IPU_DISP1_DAT_20, - MX53_PAD_EIM_D30__IPU_DISP1_DAT_21, - MX53_PAD_EIM_D26__IPU_DISP1_DAT_22, - MX53_PAD_EIM_D27__IPU_DISP1_DAT_23, - MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3, - MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4, - MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5, - MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6, - MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7, - MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8, - MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9, - MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK, - MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0, - MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1, - MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2, - MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3, - MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK, - MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0, - MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1, - MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2, - MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3, - MX53_PAD_GPIO_18__OWIRE_LINE, - MX53_PAD_GPIO_1__PWM2_PWMO, - MX53_PAD_GPIO_16__SPDIF_IN1, - MX53_PAD_GPIO_17__SPDIF_OUT1, - MX53_PAD_PATA_DMACK__UART1_RXD_MUX, - MX53_PAD_PATA_DIOW__UART1_TXD_MUX, - MX53_PAD_PATA_INTRQ__UART2_CTS, - MX53_PAD_PATA_DIOR__UART2_RTS, - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX, - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX, - MX53_PAD_PATA_CS_1__UART3_RXD_MUX, - MX53_PAD_PATA_CS_0__UART3_TXD_MUX, - - /* SD2 card detect */ - MX53_PAD_GPIO_4__GPIO1_4, - /* SD2 write protect */ - MX53_PAD_GPIO_2__GPIO1_2, - /* phy reset */ - MX53_PAD_PATA_DA_0__GPIO7_6, -}; - -#define GPIO_FEC_NRESET IMX_GPIO_NR(7, 6) - -#define GPIO_SD2_CD IMX_GPIO_NR(1, 4) -#define GPIO_SD2_WP IMX_GPIO_NR(1, 2) - -static struct esdhc_platform_data tqma53_sd2_data = { - .cd_gpio = GPIO_SD2_CD, - .wp_gpio = GPIO_SD2_WP, - .cd_type = ESDHC_CD_GPIO, - .wp_type = ESDHC_WP_GPIO, -}; - -static struct esdhc_platform_data tqma53_sd3_data = { - .cd_type = ESDHC_CD_PERMANENT, - .wp_type = ESDHC_WP_NONE, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, -}; - static int tqma53_devices_init(void) { - gpio_direction_output(GPIO_FEC_NRESET, 0); - mdelay(1); - gpio_set_value(GPIO_FEC_NRESET, 1); + char *of_env_path = "/chosen/environment-emmc"; - imx53_iim_register_fec_ethaddr(); - imx53_add_fec(&fec_info); - imx53_add_mmc1(&tqma53_sd2_data); - imx53_add_mmc2(&tqma53_sd3_data); - - armlinux_set_architecture(MACH_TYPE_TQMA53); - - return 0; -} -device_initcall(tqma53_devices_init); - -static int tqma53_part_init(void) -{ - devfs_add_partition("disk0", 0x00000, SZ_1M, DEVFS_PARTITION_FIXED, "self0"); - devfs_add_partition("disk0", SZ_1M, SZ_1M, DEVFS_PARTITION_FIXED, "env0"); - - return 0; -} -late_initcall(tqma53_part_init); - -static int tqma53_console_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(tqma53_pads, ARRAY_SIZE(tqma53_pads)); + if (!of_machine_is_compatible("tq,tqma53")) + return 0; barebox_set_model("TQ tqma53"); barebox_set_hostname("tqma53"); - imx53_add_uart1(); + if (bootsource_get() == BOOTSOURCE_MMC && + bootsource_get_instance() == 1) + of_env_path = "/chosen/environment-sd"; + + of_device_enable_path(of_env_path); + + armlinux_set_architecture(MACH_TYPE_TQMA53); return 0; } -console_initcall(tqma53_console_init); +device_initcall(tqma53_devices_init); diff --git a/arch/arm/boards/tqma53/flash-header-tq-tqma53-1gib.imxcfg b/arch/arm/boards/tqma53/flash-header-tq-tqma53-1gib.imxcfg new file mode 100644 index 0000000000..50a8f27dc5 --- /dev/null +++ b/arch/arm/boards/tqma53/flash-header-tq-tqma53-1gib.imxcfg @@ -0,0 +1,5 @@ +#define SETUP_512MIB_1GIB \ + wm 32 0x63fd9018 0x00011740; \ + wm 32 0x63fd9000 0xc3190000 + +#include "flash-header-tq-tqma53.h" diff --git a/arch/arm/boards/tqma53/flash-header-tq-tqma53-512mib.imxcfg b/arch/arm/boards/tqma53/flash-header-tq-tqma53-512mib.imxcfg new file mode 100644 index 0000000000..4c8eed40d2 --- /dev/null +++ b/arch/arm/boards/tqma53/flash-header-tq-tqma53-512mib.imxcfg @@ -0,0 +1,5 @@ +#define SETUP_512MIB_1GIB \ + wm 32 0x63fd9018 0x00101740; \ + wm 32 0x63fd9000 0x83190000 + +#include "flash-header-tq-tqma53.h" diff --git a/arch/arm/boards/tqma53/flash-header-tq-tqma53.h b/arch/arm/boards/tqma53/flash-header-tq-tqma53.h new file mode 100644 index 0000000000..4d16b0667a --- /dev/null +++ b/arch/arm/boards/tqma53/flash-header-tq-tqma53.h @@ -0,0 +1,61 @@ +soc imx53 +loadaddr 0x70000000 +dcdofs 0x400 + +/* IOMUX */ +wm 32 0x53fa8554 0x00300000 +wm 32 0x53fa8558 0x00300040 +wm 32 0x53fa8560 0x00300000 +wm 32 0x53fa8564 0x00300040 +wm 32 0x53fa8568 0x00300040 +wm 32 0x53fa8570 0x00300000 +wm 32 0x53fa8574 0x00300000 +wm 32 0x53fa8578 0x00300000 +wm 32 0x53fa857c 0x00300040 +wm 32 0x53fa8580 0x00300040 +wm 32 0x53fa8584 0x00300000 +wm 32 0x53fa8588 0x00300000 +wm 32 0x53fa8590 0x00300040 +wm 32 0x53fa8594 0x00300000 +wm 32 0x53fa86f0 0x00300000 +wm 32 0x53fa86f4 0x00000000 +wm 32 0x53fa86fc 0x00000000 +wm 32 0x53fa8714 0x00000000 +wm 32 0x53fa8718 0x00300000 +wm 32 0x53fa871c 0x00300000 +wm 32 0x53fa8720 0x00300000 +wm 32 0x53fa8724 0x04000000 +wm 32 0x53fa8728 0x00300000 +wm 32 0x53fa872c 0x00300000 +/* ESDCTL */ +wm 32 0x63fd9088 0x35343535 +wm 32 0x63fd9090 0x4d444c44 +wm 32 0x63fd907c 0x01370138 +wm 32 0x63fd9080 0x013b013c +wm 32 0x63fd90f8 0x00000800 + +SETUP_512MIB_1GIB + +wm 32 0x63fd900c 0x9f5152e3 +wm 32 0x63fd9010 0xb68e8a63 +wm 32 0x63fd9014 0x01ff00db +wm 32 0x63fd902c 0x000026d2 +/* Engcm12377 / errata sheet 03/2013 */ +wm 32 0x63fd9030 0x009f0e23 +wm 32 0x63fd9008 0x12273030 +wm 32 0x63fd9004 0x0002002d +wm 32 0x63fd901c 0x00008032 +wm 32 0x63fd901c 0x00008033 +wm 32 0x63fd901c 0x00028031 +wm 32 0x63fd901c 0x052080b0 +wm 32 0x63fd901c 0x04008040 +wm 32 0x63fd901c 0x0000803a +wm 32 0x63fd901c 0x0000803b +wm 32 0x63fd901c 0x00028039 +wm 32 0x63fd901c 0x05208138 +wm 32 0x63fd901c 0x04008048 +wm 32 0x63fd9020 0x00005800 +/* prevent reserved value, use default TZQ_CS */ +wm 32 0x63fd9040 0x05380003 +wm 32 0x63fd9058 0x00022227 +wm 32 0x63fd901C 0x00000000 diff --git a/arch/arm/boards/tqma53/flash_header.c b/arch/arm/boards/tqma53/flash_header.c deleted file mode 100644 index ea649af394..0000000000 --- a/arch/arm/boards/tqma53/flash_header.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (C) 2011 Marc Kleine-Budde - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include - -void __naked __flash_header_start go(void) -{ - barebox_arm_head(); -} - -struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = { - /* IOMUX */ - { .addr = cpu_to_be32(0x53fa8554), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa8558), .val = cpu_to_be32(0x00300040), }, - { .addr = cpu_to_be32(0x53fa8560), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa8564), .val = cpu_to_be32(0x00300040), }, - { .addr = cpu_to_be32(0x53fa8568), .val = cpu_to_be32(0x00300040), }, - { .addr = cpu_to_be32(0x53fa8570), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa8574), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa8578), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa857c), .val = cpu_to_be32(0x00300040), }, - { .addr = cpu_to_be32(0x53fa8580), .val = cpu_to_be32(0x00300040), }, - { .addr = cpu_to_be32(0x53fa8584), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa8588), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa8590), .val = cpu_to_be32(0x00300040), }, - { .addr = cpu_to_be32(0x53fa8594), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa86f0), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa86f4), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa86fc), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa8714), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa8718), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa871c), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa8720), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa8724), .val = cpu_to_be32(0x04000000), }, - { .addr = cpu_to_be32(0x53fa8728), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa872c), .val = cpu_to_be32(0x00300000), }, - /* ESDCTL */ - { .addr = cpu_to_be32(0x63fd9088), .val = cpu_to_be32(0x35343535), }, - { .addr = cpu_to_be32(0x63fd9090), .val = cpu_to_be32(0x4d444c44), }, - { .addr = cpu_to_be32(0x63fd907c), .val = cpu_to_be32(0x01370138), }, - { .addr = cpu_to_be32(0x63fd9080), .val = cpu_to_be32(0x013b013c), }, - { .addr = cpu_to_be32(0x63fd90f8), .val = cpu_to_be32(0x00000800), }, -#ifdef CONFIG_MACH_TQMA53_1GB_RAM - /* sync with u-boot: add WALAT for 4 chip variant */ - { .addr = cpu_to_be32(0x63fd9018), .val = cpu_to_be32(0x00011740), }, - { .addr = cpu_to_be32(0x63fd9000), .val = cpu_to_be32(0xc3190000), }, -#else - { .addr = cpu_to_be32(0x63fd9018), .val = cpu_to_be32(0x00101740), }, - { .addr = cpu_to_be32(0x63fd9000), .val = cpu_to_be32(0x83190000), }, -#endif - { .addr = cpu_to_be32(0x63fd900c), .val = cpu_to_be32(0x9f5152e3), }, - { .addr = cpu_to_be32(0x63fd9010), .val = cpu_to_be32(0xb68e8a63), }, - { .addr = cpu_to_be32(0x63fd9014), .val = cpu_to_be32(0x01ff00db), }, - { .addr = cpu_to_be32(0x63fd902c), .val = cpu_to_be32(0x000026d2), }, - /* Engcm12377 / errata sheet 03/2013 */ - { .addr = cpu_to_be32(0x63fd9030), .val = cpu_to_be32(0x009f0e23), }, - { .addr = cpu_to_be32(0x63fd9008), .val = cpu_to_be32(0x12273030), }, - { .addr = cpu_to_be32(0x63fd9004), .val = cpu_to_be32(0x0002002d), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008032), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008033), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00028031), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x052080b0), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008040), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0000803a), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0000803b), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00028039), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x05208138), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008048), }, - { .addr = cpu_to_be32(0x63fd9020), .val = cpu_to_be32(0x00005800), }, - /* prevent reserved value, use default TZQ_CS */ - { .addr = cpu_to_be32(0x63fd9040), .val = cpu_to_be32(0x05380003), }, - { .addr = cpu_to_be32(0x63fd9058), .val = cpu_to_be32(0x00022227), }, - { .addr = cpu_to_be32(0x63fd901C), .val = cpu_to_be32(0x00000000), }, -}; - -#define APP_DEST 0x70000000 - -struct imx_flash_header_v2 __flash_header_section flash_header = { - .header.tag = IVT_HEADER_TAG, - .header.length = cpu_to_be16(32), - .header.version = IVT_VERSION, - - .entry = APP_DEST + 0x1000, - .dcd_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header_v2, dcd), - .boot_data_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header_v2, boot_data), - .self = APP_DEST + 0x400, - - .boot_data.start = APP_DEST, - .boot_data.size = DCD_BAREBOX_SIZE, - - .dcd.header.tag = DCD_HEADER_TAG, - .dcd.header.length = cpu_to_be16(sizeof(struct imx_dcd) + sizeof(dcd_entry)), - .dcd.header.version = DCD_VERSION, - - .dcd.command.tag = DCD_COMMAND_WRITE_TAG, - .dcd.command.length = cpu_to_be16(sizeof(struct imx_dcd_command) + sizeof(dcd_entry)), - .dcd.command.param = DCD_COMMAND_WRITE_PARAM, -}; diff --git a/arch/arm/boards/tqma53/lowlevel.c b/arch/arm/boards/tqma53/lowlevel.c index a6eaa46dd2..320a03e7b9 100644 --- a/arch/arm/boards/tqma53/lowlevel.c +++ b/arch/arm/boards/tqma53/lowlevel.c @@ -1,11 +1,65 @@ #include +#include +#include #include #include +#include #include -void __naked barebox_arm_reset_vector(void) +extern char __dtb_imx53_mba53_start[]; + +static inline void setup_uart(void __iomem *base) +{ + /* Enable UART for lowlevel debugging purposes */ + writel(0x00000000, base + 0x80); + writel(0x00004027, base + 0x84); + writel(0x00000704, base + 0x88); + writel(0x00000a81, base + 0x90); + writel(0x0000002b, base + 0x9c); + writel(0x0001046a, base + 0xb0); + writel(0x0000047f, base + 0xa4); + writel(0x0000a2c1, base + 0xa8); + writel(0x00000001, base + 0x80); +} + +static void __noreturn start_imx53_tqma53_common(uint32_t fdt) +{ + if (IS_ENABLED(CONFIG_DEBUG_LL)) { + writel(0x3, MX53_IOMUXC_BASE_ADDR + 0x278); + writel(0x3, MX53_IOMUXC_BASE_ADDR + 0x27c); + setup_uart((void *)MX53_UART2_BASE_ADDR); + putc_ll('>'); + } + + imx53_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx53_mba53_512mib, r0, r1, r2) { + uint32_t fdt; + arm_cpu_lowlevel_init(); + + arm_setup_stack(0xf8020000 - 8); + imx53_init_lowlevel_early(800); - imx53_barebox_entry(0); + + fdt = (uint32_t)__dtb_imx53_mba53_start - get_runtime_offset(); + + start_imx53_tqma53_common(fdt); +} + +ENTRY_FUNCTION(start_imx53_mba53_1gib, r0, r1, r2) +{ + uint32_t fdt; + + arm_cpu_lowlevel_init(); + + arm_setup_stack(0xf8020000 - 8); + + imx53_init_lowlevel_early(800); + + fdt = (uint32_t)__dtb_imx53_mba53_start - get_runtime_offset(); + + start_imx53_tqma53_common(fdt); } diff --git a/arch/arm/configs/tqma53_defconfig b/arch/arm/configs/tqma53_defconfig index fedd36821d..26e6b288bc 100644 --- a/arch/arm/configs/tqma53_defconfig +++ b/arch/arm/configs/tqma53_defconfig @@ -1,5 +1,5 @@ CONFIG_ARCH_IMX=y -CONFIG_ARCH_IMX53=y +CONFIG_IMX_MULTI_BOARDS=y CONFIG_MACH_TQMA53=y CONFIG_IMX_IIM=y CONFIG_IMX_IIM_FUSE_BLOW=y @@ -7,13 +7,17 @@ CONFIG_AEABI=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y CONFIG_ARM_UNWIND=y CONFIG_MMU=y -CONFIG_MALLOC_SIZE=0x2000000 +CONFIG_TEXT_BASE=0x0 +CONFIG_MALLOC_SIZE=0x0 CONFIG_MALLOC_TLSF=y CONFIG_KALLSYMS=y +CONFIG_RELOCATABLE=y CONFIG_LONGHELP=y CONFIG_HUSH_FANCY_PROMPT=y CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y +CONFIG_BLSPEC=y +CONFIG_CONSOLE_ACTIVATE_NONE=y CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/tqma53/env/" CONFIG_DEBUG_INFO=y @@ -25,8 +29,6 @@ CONFIG_CMD_EXPORT=y CONFIG_CMD_PRINTENV=y CONFIG_CMD_READLINE=y CONFIG_CMD_TIME=y -CONFIG_CMD_BASENAME=y -CONFIG_CMD_DIRNAME=y CONFIG_CMD_ECHO_E=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_IOMEM=y @@ -38,20 +40,27 @@ CONFIG_CMD_BOOTM_INITRD=y CONFIG_CMD_BOOTM_OFTREE=y CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y CONFIG_CMD_UIMAGE=y -# CONFIG_CMD_BOOTZ is not set # CONFIG_CMD_BOOTU is not set CONFIG_CMD_RESET=y CONFIG_CMD_GO=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OF_NODE=y CONFIG_CMD_TIMEOUT=y CONFIG_CMD_PARTITION=y CONFIG_CMD_MAGICVAR=y CONFIG_CMD_MAGICVAR_HELP=y CONFIG_CMD_GPIO=y CONFIG_CMD_UNCOMPRESS=y +CONFIG_CMD_MIITOOL=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DETECT=y CONFIG_NET=y CONFIG_NET_DHCP=y CONFIG_NET_PING=y CONFIG_NET_NETCONSOLE=y +CONFIG_OFDEVICE=y +CONFIG_OF_BAREBOX_DRIVERS=y CONFIG_DRIVER_NET_FEC_IMX=y # CONFIG_SPI is not set CONFIG_MCI=y diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 189394b9aa..1718bde66a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -46,6 +46,7 @@ pbl-$(CONFIG_MACH_SOLIDRUN_CUBOX) += dove-cubox.dtb.o pbl-$(CONFIG_MACH_GK802) += imx6q-gk802.dtb.o pbl-$(CONFIG_MACH_TORADEX_COLIBRI_T20_IRIS) += tegra20-colibri-iris.dtb.o pbl-$(CONFIG_MACH_TOSHIBA_AC100) += tegra20-paz00.dtb.o +pbl-$(CONFIG_MACH_TQMA53) += imx53-mba53.dtb.o pbl-$(CONFIG_MACH_TQMA6X) += imx6dl-mba6x.dtb.o imx6q-mba6x.dtb.o pbl-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o pbl-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 81ce3084c5..359f06c63f 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -196,6 +196,10 @@ config MACH_FREESCALE_MX53_LOCO bool "Freescale i.MX53 LOCO" select ARCH_IMX53 +config MACH_TQMA53 + bool "TQ i.MX53 TQMa53" + select ARCH_IMX53 + config MACH_FREESCALE_MX53_VMX53 bool "Voipac i.MX53" select ARCH_IMX53 @@ -444,11 +448,6 @@ config MACH_FREESCALE_MX53_SMD bool "Freescale i.MX53 SMD" select ARCH_IMX53 -config MACH_TQMA53 - bool "TQ i.MX53 TQMa53" - select ARCH_IMX53 - select HAVE_DEFAULT_ENVIRONMENT_NEW - config MACH_TX53 bool "Ka-Ro TX53" select ARCH_IMX53 @@ -544,16 +543,6 @@ endchoice endif -if MACH_TQMA53 - -config MACH_TQMA53_1GB_RAM - bool "Use 1GiB of SDRAM" - depends on MACH_TQMA53 - help - use 1GiB of SDRAM (512MiB otherwise) - -endif - if MACH_TX53 choice diff --git a/images/Makefile.imx b/images/Makefile.imx index 901d8cdcdc..3318fcf09c 100644 --- a/images/Makefile.imx +++ b/images/Makefile.imx @@ -36,6 +36,16 @@ CFG_start_imx53_vmx53.pblx.imximg = $(board)/freescale-mx53-vmx53/flash-header-i FILE_barebox-freescale-imx53-vmx53.img = start_imx53_vmx53.pblx.imximg image-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += barebox-freescale-imx53-vmx53.img +pblx-$(CONFIG_MACH_TQMA53) += start_imx53_mba53_512mib +CFG_start_imx53_mba53_512mib.pblx.imximg = $(board)/tqma53/flash-header-tq-tqma53-512mib.imxcfg +FILE_barebox-tq-mba53-512mib.img = start_imx53_mba53_512mib.pblx.imximg +image-$(CONFIG_MACH_TQMA53) += barebox-tq-mba53-512mib.img + +pblx-$(CONFIG_MACH_TQMA53) += start_imx53_mba53_1gib +CFG_start_imx53_mba53_1gib.pblx.imximg = $(board)/tqma53/flash-header-tq-tqma53-1gib.imxcfg +FILE_barebox-tq-mba53-1gib.img = start_imx53_mba53_1gib.pblx.imximg +image-$(CONFIG_MACH_TQMA53) += barebox-tq-mba53-1gib.img + # ----------------------- i.MX6 based boards --------------------------- pblx-$(CONFIG_MACH_REALQ7) += start_imx6_realq7 CFG_start_imx6_realq7.pblx.imximg = $(board)/dmo-mx6-realq7/flash-header.imxcfg -- cgit v1.2.3 From 3711a1d8e7022925b6e4e83836bd957691f52ae0 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 28 Jan 2014 10:39:45 +0100 Subject: ARM: i.MX: external NAND boot: use image size from image header When compiling with multiimage support ld_var(_barebox_image_size) only contains the length of the PBL image, but not including the appended compressed data. With this patch the image size is read from the barebox header instead which contains the correct size, either from the linker or from the fix_size tool. This makes the external_nand_boot compatible with multiimage support. Tested on Phytec phyCARD-i.MX27 with and without PBL. Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/external-nand-boot.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/external-nand-boot.c b/arch/arm/mach-imx/external-nand-boot.c index fab37bf77a..c08806cee3 100644 --- a/arch/arm/mach-imx/external-nand-boot.c +++ b/arch/arm/mach-imx/external-nand-boot.c @@ -322,10 +322,13 @@ void __noreturn BARE_INIT_FUNCTION(imx##soc##_boot_nand_external_cont) \ (uint32_t boarddata) \ { \ unsigned long nfc_base = MX##soc##_NFC_BASE_ADDR; \ - unsigned long sdram = MX##soc##_CSD0_BASE_ADDR; \ + void *sdram = (void *)MX##soc##_CSD0_BASE_ADDR; \ + uint32_t image_size; \ + \ + image_size = *(uint32_t *)(sdram + 0x2c); \ \ - imx##soc##_nand_load_image((void *)sdram, \ - ld_var(_barebox_image_size), \ + imx##soc##_nand_load_image(sdram, \ + image_size, \ (void *)nfc_base, \ imx##soc##_pagesize_2k()); \ \ -- cgit v1.2.3 From 7ebb5fbb58b6b9e496e3441f1be6bdc5b993964d Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 27 Jan 2014 16:15:00 +0100 Subject: ARM: i.MX: external NAND boot: make dtb boarddata work If we are running from NFC SRAM and we are passed boarddata containing a devicetree pointer then it point to an address relative to the NFC SRAM start. First thing we do is to copy the initial binary to SDRAM and jump there. The devicetree pointer has to be adjusted by this offset. Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/external-nand-boot.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/external-nand-boot.c b/arch/arm/mach-imx/external-nand-boot.c index c08806cee3..fe933aa3a9 100644 --- a/arch/arm/mach-imx/external-nand-boot.c +++ b/arch/arm/mach-imx/external-nand-boot.c @@ -373,6 +373,11 @@ void __noreturn BARE_INIT_FUNCTION(imx##soc##_barebox_boot_nand_external) \ \ fn = (void *)__fn; \ \ + if (boarddata > nfc_base && boarddata < nfc_base + SZ_512K) { \ + boarddata &= SZ_512K - 1; \ + boarddata += sdram; \ + } \ + \ fn(boarddata); \ } -- cgit v1.2.3 From 45c5110587deb65c820ed2da6602dc16dea9e8d9 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 27 Jan 2014 16:24:10 +0100 Subject: ARM: i.MX25: Add missing GPT clock lookups Only one GPT will be used, but with devicetree support we can't predict which one it is, so we need the clock lookup for all GPTs to ensure that the timer gets its clock. Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/clk-imx25.c | 3 +++ arch/arm/mach-imx/include/mach/imx25-regs.h | 3 +++ 2 files changed, 6 insertions(+) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c index 9817990667..4d8631cb01 100644 --- a/arch/arm/mach-imx/clk-imx25.c +++ b/arch/arm/mach-imx/clk-imx25.c @@ -140,6 +140,9 @@ static int imx25_ccm_probe(struct device_d *dev) clkdev_add_physbase(clks[per15], MX25_UART4_BASE_ADDR, NULL); clkdev_add_physbase(clks[per15], MX25_UART5_BASE_ADDR, NULL); clkdev_add_physbase(clks[per5], MX25_GPT1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per5], MX25_GPT2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per5], MX25_GPT3_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per5], MX25_GPT4_BASE_ADDR, NULL); clkdev_add_physbase(clks[ipg], MX25_FEC_BASE_ADDR, NULL); clkdev_add_physbase(clks[ipg], MX25_I2C1_BASE_ADDR, NULL); clkdev_add_physbase(clks[ipg], MX25_I2C2_BASE_ADDR, NULL); diff --git a/arch/arm/mach-imx/include/mach/imx25-regs.h b/arch/arm/mach-imx/include/mach/imx25-regs.h index 9ab0fb3eee..71812764c9 100644 --- a/arch/arm/mach-imx/include/mach/imx25-regs.h +++ b/arch/arm/mach-imx/include/mach/imx25-regs.h @@ -35,6 +35,9 @@ #define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000) #define MX25_CCM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) +#define MX25_GPT4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x84000) +#define MX25_GPT3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x88000) +#define MX25_GPT2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x8c000) #define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000) #define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000) #define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000) -- cgit v1.2.3 From 0e80f5b4cc0d2b6b5fdeed99785ba88fe1753337 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 28 Jan 2014 09:28:25 +0100 Subject: ARM: i.MX: cleanup bootmode selection Which bootmode is selected has no longer to be chosen by Kconfig. The boards can decide themselves which bootmode they want to support. This makes it unnecesary to ask the user which bootmode shall be supported, so the "Select boot mode" becomes invisible and both support will be compiled in as needed by the boards. NAND_IMX_BOOT goes away and the already existing ARCH_IMX_EXTERNAL_BOOT_NAND can now be used for the boards to depend on external nand boot. Signed-off-by: Sascha Hauer --- arch/arm/boards/eukrea_cpuimx25/lowlevel.c | 10 ++++----- arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S | 4 ++-- arch/arm/boards/eukrea_cpuimx35/lowlevel.c | 25 +++++++++++---------- .../boards/freescale-mx25-3-stack/lowlevel_init.S | 5 +++-- .../boards/freescale-mx35-3-stack/lowlevel_init.S | 4 ++-- arch/arm/boards/guf-cupid/lowlevel.c | 21 ++++++++--------- arch/arm/boards/guf-neso/lowlevel.c | 11 ++++----- arch/arm/boards/imx21ads/lowlevel_init.S | 5 +++-- arch/arm/boards/pcm037/lowlevel.c | 14 ++++++------ arch/arm/boards/pcm038/lowlevel.c | 10 ++++----- arch/arm/boards/pcm043/lowlevel.c | 25 +++++++++++---------- arch/arm/boards/phycard-i.MX27/lowlevel.c | 4 ---- arch/arm/mach-imx/Kconfig | 26 +++++----------------- 13 files changed, 76 insertions(+), 88 deletions(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c index 07659f53fc..f0bf2c7fd5 100644 --- a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c +++ b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c @@ -127,12 +127,12 @@ void __bare_init __naked barebox_arm_reset_vector(void) writeb(0xda, MX25_CSD0_BASE_ADDR + 0x1000000); writel(0x82216080, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0); -#ifdef CONFIG_NAND_IMX_BOOT - /* setup a stack to be able to call imx25_barebox_boot_nand_external() */ - arm_setup_stack(STACK_BASE + STACK_SIZE - 12); + if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) { + /* setup a stack to be able to call imx25_barebox_boot_nand_external() */ + arm_setup_stack(MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 12); - imx25_barebox_boot_nand_external(0); -#endif + imx25_barebox_boot_nand_external(0); + } out: imx25_barebox_entry(0); } diff --git a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S index ae1391c283..f8e3c23540 100644 --- a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S +++ b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S @@ -123,13 +123,13 @@ barebox_arm_reset_vector: 1: sdram_init -#ifdef CONFIG_NAND_IMX_BOOT +#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND /* Setup a temporary stack in SDRAM */ ldr sp, =MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 4; mov r0, #0 b imx27_barebox_boot_nand_external -#endif /* CONFIG_NAND_IMX_BOOT */ +#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */ ret: b imx27_barebox_entry diff --git a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c index d03e1109d9..b8ba3c8716 100644 --- a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c +++ b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c @@ -130,18 +130,19 @@ void __bare_init __naked barebox_arm_reset_vector(void) writeb(0xda, MX35_CSD0_BASE_ADDR + 0x2000000); writel(0x82228080, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); -#ifdef CONFIG_NAND_IMX_BOOT - /* Speed up NAND controller by adjusting the NFC divider */ - r = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); - r &= ~(0xf << 28); - r |= 0x1 << 28; - writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); - - /* setup a stack to be able to call imx35_barebox_boot_nand_external() */ - arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8); - - imx35_barebox_boot_nand_external(0); -#endif + if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) { + /* Speed up NAND controller by adjusting the NFC divider */ + r = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); + r &= ~(0xf << 28); + r |= 0x1 << 28; + writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); + + /* setup a stack to be able to call imx35_barebox_boot_nand_external() */ + arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8); + + imx35_barebox_boot_nand_external(0); + } + out: imx35_barebox_entry(0); } diff --git a/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S b/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S index 8446c6f1db..4ca4c82d32 100644 --- a/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S +++ b/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S @@ -97,13 +97,14 @@ barebox_arm_reset_vector: ldr r3, ESDCTL_DELAY5 str r3, [r0, #0x30] -#ifdef CONFIG_NAND_IMX_BOOT +#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND + /* Setup a temporary stack in SRAM */ ldr sp, =MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 4 mov r0, #0 b imx25_barebox_boot_nand_external -#endif /* CONFIG_NAND_IMX_BOOT */ +#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */ ret: b imx25_barebox_entry diff --git a/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S b/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S index cb9ed0ab6e..6d37f35a2e 100644 --- a/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S +++ b/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S @@ -154,13 +154,13 @@ barebox_arm_reset_vector: ldr r3, =ESDCTL_DELAY_LINE5 str r3, [r0, #0x30] -#ifdef CONFIG_NAND_IMX_BOOT +#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND /* Setup a temporary stack in internal SRAM */ ldr sp, =MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 4 mov r0, #0 b imx35_barebox_boot_nand_external -#endif /* CONFIG_NAND_IMX_BOOT */ +#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */ b imx35_barebox_entry diff --git a/arch/arm/boards/guf-cupid/lowlevel.c b/arch/arm/boards/guf-cupid/lowlevel.c index d5dce16507..4c0de9caed 100644 --- a/arch/arm/boards/guf-cupid/lowlevel.c +++ b/arch/arm/boards/guf-cupid/lowlevel.c @@ -306,18 +306,19 @@ void __bare_init __naked barebox_arm_reset_vector(void) r0 = ESDCTL0_SDE | ESDCTL0_ROW14 | ESDCTL0_COL10 | ESDCTL0_DSIZ_31_0; /* 1024 MBit DDR-SDRAM */ setup_sdram(r0, ESDMISC_MDDR_EN, 0x80000f00); -#ifdef CONFIG_NAND_IMX_BOOT - /* Speed up NAND controller by adjusting the NFC divider */ - r0 = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); - r0 &= ~(0xf << 28); - r0 |= 0x1 << 28; - writel(r0, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); + if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) { + /* Speed up NAND controller by adjusting the NFC divider */ + r0 = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); + r0 &= ~(0xf << 28); + r0 |= 0x1 << 28; + writel(r0, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); - /* setup a stack to be able to call imx35_barebox_boot_nand_external() */ - arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8); + /* setup a stack to be able to call imx35_barebox_boot_nand_external() */ + arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8); + + imx35_barebox_boot_nand_external(0); + } - imx35_barebox_boot_nand_external(0); -#endif out: imx35_barebox_entry(0); } diff --git a/arch/arm/boards/guf-neso/lowlevel.c b/arch/arm/boards/guf-neso/lowlevel.c index c3323ee1ea..d26ee73ef1 100644 --- a/arch/arm/boards/guf-neso/lowlevel.c +++ b/arch/arm/boards/guf-neso/lowlevel.c @@ -86,12 +86,13 @@ void __bare_init __naked barebox_arm_reset_vector(void) ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); -#ifdef CONFIG_NAND_IMX_BOOT - /* setup a stack to be able to call imx27_barebox_boot_nand_external() */ - arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 8); + if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) { + /* setup a stack to be able to call imx27_barebox_boot_nand_external() */ + arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 8); + + imx27_barebox_boot_nand_external(0); + } - imx27_barebox_boot_nand_external(0); -#endif out: imx27_barebox_entry(0); } diff --git a/arch/arm/boards/imx21ads/lowlevel_init.S b/arch/arm/boards/imx21ads/lowlevel_init.S index 09ca4a477e..471390f328 100644 --- a/arch/arm/boards/imx21ads/lowlevel_init.S +++ b/arch/arm/boards/imx21ads/lowlevel_init.S @@ -118,12 +118,13 @@ barebox_arm_reset_vector: ldr r1, =0x6419a007 str r1, [r0] -#ifdef CONFIG_NAND_IMX_BOOT +#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND { + /* Setup a temporary stack in SRAM */ ldr sp, =MX21_IRAM_BASE_ADDR + MX21_IRAM_SIZE - 4 b imx21_barebox_boot_nand_external -#endif /* CONFIG_NAND_IMX_BOOT */ +#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */ ret: mov r0, #0xc0000000 diff --git a/arch/arm/boards/pcm037/lowlevel.c b/arch/arm/boards/pcm037/lowlevel.c index ae2d8c0375..cd894c25ce 100644 --- a/arch/arm/boards/pcm037/lowlevel.c +++ b/arch/arm/boards/pcm037/lowlevel.c @@ -125,12 +125,12 @@ void __bare_init __naked barebox_arm_reset_vector(void) writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC); #endif -#ifdef CONFIG_NAND_IMX_BOOT - /* setup a stack to be able to call imx31_barebox_boot_nand_external() */ - arm_setup_stack(MX31_IRAM_BASE_ADDR + MX31_IRAM_SIZE - 12); + if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) { + /* setup a stack to be able to call imx31_barebox_boot_nand_external() */ + arm_setup_stack(MX31_IRAM_BASE_ADDR + MX31_IRAM_SIZE - 12); - imx31_barebox_boot_nand_external(0); -#else - imx31_barebox_entry(0); -#endif + imx31_barebox_boot_nand_external(0); + } else { + imx31_barebox_entry(0); + } } diff --git a/arch/arm/boards/pcm038/lowlevel.c b/arch/arm/boards/pcm038/lowlevel.c index bb948f1c14..4f55af8264 100644 --- a/arch/arm/boards/pcm038/lowlevel.c +++ b/arch/arm/boards/pcm038/lowlevel.c @@ -93,12 +93,12 @@ void __bare_init __naked barebox_arm_reset_vector(void) ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); -#ifdef CONFIG_NAND_IMX_BOOT - /* setup a stack to be able to call mx27_barebox_boot_nand_external() */ - arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 8); + if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) { + /* setup a stack to be able to call mx27_barebox_boot_nand_external() */ + arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 8); - imx27_barebox_boot_nand_external(0); -#endif + imx27_barebox_boot_nand_external(0); + } out: imx27_barebox_entry(0); } diff --git a/arch/arm/boards/pcm043/lowlevel.c b/arch/arm/boards/pcm043/lowlevel.c index 64b03823f6..8376bb4f00 100644 --- a/arch/arm/boards/pcm043/lowlevel.c +++ b/arch/arm/boards/pcm043/lowlevel.c @@ -182,18 +182,19 @@ void __bare_init __naked barebox_arm_reset_vector(void) /* enable Auto-Refresh */ writel(0x00002000, esdctl_base + IMX_ESDCTL1); -#ifdef CONFIG_NAND_IMX_BOOT - /* Speed up NAND controller by adjusting the NFC divider */ - r = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); - r &= ~(0xf << 28); - r |= 0x1 << 28; - writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); - - /* setup a stack to be able to call imx35_barebox_boot_nand_external() */ - arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8); - - imx35_barebox_boot_nand_external(0); -#endif + if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) { + /* Speed up NAND controller by adjusting the NFC divider */ + r = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); + r &= ~(0xf << 28); + r |= 0x1 << 28; + writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); + + /* setup a stack to be able to call imx35_barebox_boot_nand_external() */ + arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8); + + imx35_barebox_boot_nand_external(0); + } + out: imx35_barebox_entry(0); } diff --git a/arch/arm/boards/phycard-i.MX27/lowlevel.c b/arch/arm/boards/phycard-i.MX27/lowlevel.c index 33de1c0423..5b3bdafa71 100644 --- a/arch/arm/boards/phycard-i.MX27/lowlevel.c +++ b/arch/arm/boards/phycard-i.MX27/lowlevel.c @@ -99,9 +99,5 @@ void __bare_init __naked barebox_arm_reset_vector(void) sdram_init(); -#ifdef CONFIG_NAND_IMX_BOOT imx27_barebox_boot_nand_external(0); -#else - imx27_barebox_entry(0); -#endif } diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 359f06c63f..55038e81c9 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -38,8 +38,9 @@ config ARCH_TEXT_BASE default 0x4fc00000 if MACH_PHYTEC_PFLA02 default 0x4fc00000 if MACH_DFI_FS700_M60 -choice - prompt "Select boot mode" +config ARCH_IMX_INTERNAL_BOOT + bool "support internal boot mode" + depends on ARCH_IMX25 || ARCH_IMX35 || ARCH_IMX51 || ARCH_IMX53 || ARCH_IMX6 depends on !HAVE_PBL_MULTI_IMAGES help i.MX processors support two different boot modes. With the internal @@ -58,16 +59,6 @@ choice The external boot mode is supported on older i.MX processors (i.MX1, i.MX21, i.MX25, i.MX27, i.MX31, i.MX35). -config ARCH_IMX_INTERNAL_BOOT - bool "support internal boot mode" - depends on ARCH_IMX25 || ARCH_IMX35 || ARCH_IMX51 || ARCH_IMX53 || ARCH_IMX6 - -config ARCH_IMX_EXTERNAL_BOOT - bool "support external boot mode" - depends on ARCH_IMX1 || ARCH_IMX21 || ARCH_IMX25 || ARCH_IMX27 || ARCH_IMX31 || ARCH_IMX35 - -endchoice - config ARCH_IMX_IMXIMAGE bool default y @@ -105,16 +96,10 @@ config ARCH_IMX_INTERNAL_BOOT_SERIAL endchoice -config NAND_IMX_BOOT - bool - depends on ARCH_IMX_EXTERNAL_BOOT_NAND - default y - config ARCH_IMX_EXTERNAL_BOOT_NAND bool - depends on !ARCH_IMX1 - prompt "Support Starting barebox from NAND" - depends on ARCH_IMX_EXTERNAL_BOOT + depends on ARCH_IMX25 || ARCH_IMX27 || ARCH_IMX31 || ARCH_IMX35 + prompt "Support Starting barebox from NAND in external bootmode" config BAREBOX_UPDATE_IMX_EXTERNAL_NAND bool @@ -319,6 +304,7 @@ config MACH_PCA100 bool "phyCard-i.MX27" select ARCH_IMX27 select HAVE_DEFAULT_ENVIRONMENT_NEW + select ARCH_IMX_EXTERNAL_BOOT_NAND help Say Y here if you are using Phytec's phyCard-i.MX27 (pca100) equipped with a Freescale i.MX27 Processor -- cgit v1.2.3 From 021890a39eb6aca30e25f21c629547c9223a4c27 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 28 Jan 2014 10:40:34 +0100 Subject: ARM: i.MX: Karo TX25: Switch to multiboard support Signed-off-by: Sascha Hauer --- arch/arm/boards/karo-tx25/board.c | 2 +- arch/arm/boards/karo-tx25/lowlevel.c | 26 +++++++++++++++----------- arch/arm/configs/tx25stk5_defconfig | 8 ++------ arch/arm/mach-imx/Kconfig | 14 +++++++------- images/Makefile.imx | 5 +++++ 5 files changed, 30 insertions(+), 25 deletions(-) (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/boards/karo-tx25/board.c b/arch/arm/boards/karo-tx25/board.c index b4d553ec96..59c81b2faa 100644 --- a/arch/arm/boards/karo-tx25/board.c +++ b/arch/arm/boards/karo-tx25/board.c @@ -89,7 +89,7 @@ static int tx25_init(void) armlinux_set_architecture(MACH_TYPE_TX25); armlinux_set_serial(imx_uid()); - imx_bbu_external_nand_register_handler("nand", "/dev/nand0.barebox", + imx_bbu_external_nand_register_handler("nand", "/dev/nand0.boot", BBU_HANDLER_FLAG_DEFAULT); return 0; diff --git a/arch/arm/boards/karo-tx25/lowlevel.c b/arch/arm/boards/karo-tx25/lowlevel.c index a3a778469b..be27bc7bd3 100644 --- a/arch/arm/boards/karo-tx25/lowlevel.c +++ b/arch/arm/boards/karo-tx25/lowlevel.c @@ -75,12 +75,9 @@ static inline void __bare_init setup_sdram(uint32_t base, uint32_t esdctl, writel(esdctl, esdctlreg); } -extern char __dtb_imx25_karo_tx25_start[]; - -void __bare_init __naked barebox_arm_reset_vector(void) +static void __bare_init karo_tx25_common_init(uint32_t fdt) { uint32_t r; - uint32_t fdt; arm_cpu_lowlevel_init(); @@ -139,8 +136,6 @@ void __bare_init __naked barebox_arm_reset_vector(void) setup_uart(); - fdt = (uint32_t)__dtb_imx25_karo_tx25_start - get_runtime_offset(); - /* Skip SDRAM initialization if we run from RAM */ r = get_pc(); if (r > 0x80000000 && r < 0xa0000000) @@ -162,12 +157,21 @@ void __bare_init __naked barebox_arm_reset_vector(void) setup_sdram(0x80000000, ESDCTLVAL, ESDCFGVAL); setup_sdram(0x90000000, ESDCTLVAL, ESDCFGVAL); -#ifdef CONFIG_NAND_IMX_BOOT - /* setup a stack to be able to call imx25_barebox_boot_nand_external() */ - arm_setup_stack(MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 8); - imx25_barebox_boot_nand_external(fdt); -#endif + out: imx25_barebox_entry(fdt); } + +extern char __dtb_imx25_karo_tx25_start[]; + +ENTRY_FUNCTION(start_imx25_karo_tx25, r0, r1, r2) +{ + uint32_t fdt; + + arm_setup_stack(MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 8); + + fdt = (uint32_t)__dtb_imx25_karo_tx25_start - get_runtime_offset(); + + karo_tx25_common_init(fdt); +} diff --git a/arch/arm/configs/tx25stk5_defconfig b/arch/arm/configs/tx25stk5_defconfig index 32a618390f..b499b5d071 100644 --- a/arch/arm/configs/tx25stk5_defconfig +++ b/arch/arm/configs/tx25stk5_defconfig @@ -1,14 +1,10 @@ -CONFIG_BUILTIN_DTB=y -CONFIG_BUILTIN_DTB_NAME="imx25-karo-tx25" CONFIG_ARCH_IMX=y -CONFIG_ARCH_IMX_EXTERNAL_BOOT=y -CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND=y +CONFIG_IMX_MULTI_BOARDS=y CONFIG_MACH_TX25=y CONFIG_IMX_IIM=y CONFIG_AEABI=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y CONFIG_ARM_UNWIND=y -CONFIG_PBL_IMAGE=y CONFIG_MMU=y CONFIG_TEXT_BASE=0x91d00000 CONFIG_MALLOC_SIZE=0x1000000 @@ -77,9 +73,9 @@ CONFIG_NAND=y CONFIG_NAND_IMX=y CONFIG_VIDEO=y CONFIG_DRIVER_VIDEO_IMX=y +CONFIG_IMXFB_DRIVER_VIDEO_IMX_OVERLAY=y CONFIG_MCI=y CONFIG_MCI_IMX_ESDHC=y -CONFIG_SRAM=y CONFIG_WATCHDOG=y CONFIG_WATCHDOG_IMX=y CONFIG_FS_TFTP=y diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 55038e81c9..f60ef2c2a5 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -167,6 +167,13 @@ config IMX_MULTI_BOARDS if IMX_MULTI_BOARDS +config MACH_TX25 + bool "Ka-Ro TX25" + select ARCH_IMX25 + select ARCH_IMX_EXTERNAL_BOOT_NAND + help + Say Y here if you are using the Ka-Ro tx25 board + config MACH_EFIKA_MX_SMARTBOOK bool "Efika MX smartbook" select ARCH_IMX51 @@ -275,13 +282,6 @@ config MACH_FREESCALE_MX25_3STACK Say Y here if you are using the Freescale MX25 3stack board equipped with a Freescale i.MX25 Processor -config MACH_TX25 - bool "Ka-Ro TX25" - select ARCH_IMX25 - select HAVE_DEFAULT_ENVIRONMENT_NEW - help - Say Y here if you are using the Ka-Ro tx25 board - # ---------------------------------------------------------- comment "i.MX27 Boards" diff --git a/images/Makefile.imx b/images/Makefile.imx index 3318fcf09c..dd12242b99 100644 --- a/images/Makefile.imx +++ b/images/Makefile.imx @@ -9,6 +9,11 @@ $(obj)/%.imximg: $(obj)/% FORCE board = $(srctree)/arch/$(ARCH)/boards +# ----------------------- i.MX25 based boards --------------------------- +pblx-$(CONFIG_MACH_TX25) += start_imx25_karo_tx25 +FILE_barebox-karo-tx25.img = start_imx25_karo_tx25.pblx +image-$(CONFIG_MACH_TX25) += barebox-karo-tx25.img + # ----------------------- i.MX51 based boards --------------------------- pblx-$(CONFIG_MACH_FREESCALE_MX51_PDK) += start_imx51_babbage CFG_start_imx51_babbage.pblx.imximg = $(board)/freescale-mx51-pdk/flash-header-imx51-babbage.imxcfg -- cgit v1.2.3 From cc66cf109b1d2ca40c180a87fd76c2099dff2d92 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 31 Jan 2014 13:56:35 +0100 Subject: ARM: i.MX: Add lowlevel gpio functions Some boards need gpio functions very early and also sometimes is useful to toggle gpios during early code debug. This adds a header file for setting i.MX gpios early. Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/include/mach/imx-gpio.h | 48 +++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 arch/arm/mach-imx/include/mach/imx-gpio.h (limited to 'arch/arm/mach-imx') diff --git a/arch/arm/mach-imx/include/mach/imx-gpio.h b/arch/arm/mach-imx/include/mach/imx-gpio.h new file mode 100644 index 0000000000..5e673beef9 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/imx-gpio.h @@ -0,0 +1,48 @@ +#ifndef __MACH_IMX_GPIO_H +#define __MACH_IMX_GPIO_H + +#include + +/* + * i.MX lowlevel gpio functions. Only for use with lowlevel code. Use + * regular gpio functions outside of lowlevel code! + */ + +static inline void imx_gpio_direction_output(void __iomem *gdir, void __iomem *dr, + int gpio, int value) +{ + uint32_t val; + + val = readl(gdir); + val |= 1 << gpio; + writel(val, gdir); + + val = readl(dr); + if (value) + val |= 1 << gpio; + else + val &= ~(1 << gpio); + + writel(val, dr); +} + +static inline void imx1_gpio_direction_output(void *base, int gpio, int value) +{ + imx_gpio_direction_output(base + 0x0, base + 0x1c, gpio, value); +} + +#define imx21_gpio_direction_output(base, gpio, value) imx1_gpio_direction_output(base, gpio,value) +#define imx27_gpio_direction_output(base, gpio, value) imx1_gpio_direction_output(base, gpio,value) + +static inline void imx31_gpio_direction_output(void *base, int gpio, int value) +{ + imx_gpio_direction_output(base + 0x4, base + 0x0, gpio, value); +} + +#define imx25_gpio_direction_output(base, gpio, value) imx31_gpio_direction_output(base, gpio,value) +#define imx35_gpio_direction_output(base, gpio, value) imx31_gpio_direction_output(base, gpio,value) +#define imx51_gpio_direction_output(base, gpio, value) imx31_gpio_direction_output(base, gpio,value) +#define imx53_gpio_direction_output(base, gpio, value) imx31_gpio_direction_output(base, gpio,value) +#define imx6_gpio_direction_output(base, gpio, value) imx31_gpio_direction_output(base, gpio,value) + +#endif /* __MACH_IMX_GPIO_H */ -- cgit v1.2.3