From 7351b6b5c59c7a280787998006f39a5cd3a2f18b Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 13 Jun 2017 00:37:49 +0200 Subject: ARM: mvebu: fix size mask for RAM window MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The size field in the window control register occupies bits 31:16. So adapt ARMADA_370_XP_DDR_SIZE_MASK accordingly. This fixes detection of RAM chips smaller than 32 MiB and so probably doesn't affect any supported machine. Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/mach-mvebu/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-mvebu') diff --git a/arch/arm/mach-mvebu/common.c b/arch/arm/mach-mvebu/common.c index 06bfb72615..fa971da11e 100644 --- a/arch/arm/mach-mvebu/common.c +++ b/arch/arm/mach-mvebu/common.c @@ -47,7 +47,7 @@ #define ARMADA_370_XP_SDRAM_BASE (IOMEM(MVEBU_REMAP_INT_REG_BASE) + 0x20000) #define ARMADA_370_XP_DDR_SIZE_CSn(n) (0x184 + ((n) * 0x8)) #define ARMADA_370_XP_DDR_SIZE_ENABLED BIT(0) -#define ARMADA_370_XP_DDR_SIZE_MASK 0xff000000 +#define ARMADA_370_XP_DDR_SIZE_MASK 0xffff0000 /* * Marvell MVEBU SoC id and revision can be read from any PCIe -- cgit v1.2.3