From 0fe976103ee5b6e6c1e9f8f782e429f442450126 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Sun, 13 Apr 2014 15:27:34 +0200 Subject: tegra: source MSELECT clock from CLK_M We need to reprogram PLL_P at a later time, so we have to make sure MSELECT is able to operate correctly when we stop PLL_P. Signed-off-by: Lucas Stach Signed-off-by: Sascha Hauer --- arch/arm/mach-tegra/tegra_avp_init.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-tegra/tegra_avp_init.c') diff --git a/arch/arm/mach-tegra/tegra_avp_init.c b/arch/arm/mach-tegra/tegra_avp_init.c index 3314db4572..1afea445ac 100644 --- a/arch/arm/mach-tegra/tegra_avp_init.c +++ b/arch/arm/mach-tegra/tegra_avp_init.c @@ -164,8 +164,8 @@ static void start_cpu0_clocks(void) /* init MSELECT */ writel(CRC_RST_DEV_V_MSELECT, TEGRA_CLK_RESET_BASE + CRC_RST_DEV_V_SET); - writel((CRC_CLK_SOURCE_MSEL_SRC_PLLP << - CRC_CLK_SOURCE_MSEL_SRC_SHIFT) | 2, + writel((CRC_CLK_SOURCE_MSEL_SRC_CLKM << + CRC_CLK_SOURCE_MSEL_SRC_SHIFT), TEGRA_CLK_RESET_BASE + CRC_CLK_SOURCE_MSEL); writel(CRC_CLK_OUT_ENB_V_MSELECT, TEGRA_CLK_RESET_BASE + CRC_CLK_OUT_ENB_V); -- cgit v1.2.3