From 22920598a5e150ecdab8bda69d6220975dbee996 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Tue, 3 Jun 2014 22:35:05 +0200 Subject: tegra: setup L2 cache on Tegra124 Set SRAM latency to 3 clock cycles. Signed-off-by: Lucas Stach Signed-off-by: Sascha Hauer --- arch/arm/mach-tegra/tegra_maincomplex_init.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-tegra') diff --git a/arch/arm/mach-tegra/tegra_maincomplex_init.c b/arch/arm/mach-tegra/tegra_maincomplex_init.c index 83ad33d933..17490a425a 100644 --- a/arch/arm/mach-tegra/tegra_maincomplex_init.c +++ b/arch/arm/mach-tegra/tegra_maincomplex_init.c @@ -25,6 +25,8 @@ void tegra_maincomplex_entry(void) { uint32_t rambase, ramsize; + enum tegra_chiptype chiptype; + u32 reg = 0; arm_cpu_lowlevel_init(); @@ -36,7 +38,16 @@ void tegra_maincomplex_entry(void) TEGRA_CLK_RESET_BASE + CRC_CCLK_BURST_POLICY); writel(CRC_SUPER_CDIV_ENB, TEGRA_CLK_RESET_BASE + CRC_SUPER_CCLK_DIV); - switch (tegra_get_chiptype()) { + chiptype = tegra_get_chiptype(); + + if (chiptype >= TEGRA114) { + asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg)); + reg &= ~7; + reg |= 2; + asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg)); + } + + switch (chiptype) { case TEGRA20: rambase = 0x0; ramsize = tegra20_get_ramsize(); -- cgit v1.2.3