From 45d810e2b723997ae516264bd5b026f6a2ca13c4 Mon Sep 17 00:00:00 2001 From: Andrey Panov Date: Wed, 4 Mar 2015 23:11:41 +0300 Subject: ARM: Rockchip: Update Kconfig Signed-off-by: Andrey Panov Signed-off-by: Sascha Hauer --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9b6c626dfb..b92352fc67 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -159,6 +159,7 @@ config ARCH_ROCKCHIP select PINCTRL select PINCTRL_ROCKCHIP select HAVE_PBL_MULTI_IMAGES + select ARCH_HAS_L2X0 config ARCH_SOCFPGA bool "Altera SOCFPGA cyclone5" -- cgit v1.2.3 From a0790f987599a189f2f4a2eecdd09da7d1486f0e Mon Sep 17 00:00:00 2001 From: Andrey Panov Date: Wed, 4 Mar 2015 23:11:43 +0300 Subject: ARM: Rockchip: Use newer DTS for Radxa Rock board Signed-off-by: Andrey Panov Signed-off-by: Sascha Hauer --- arch/arm/dts/rk3188-clocks.dtsi | 289 ----------------------------------- arch/arm/dts/rk3188-radxarock.dts | 32 ++-- arch/arm/dts/rk3188.dtsi | 306 -------------------------------------- arch/arm/dts/rk3xxx.dtsi | 139 ----------------- 4 files changed, 20 insertions(+), 746 deletions(-) delete mode 100644 arch/arm/dts/rk3188-clocks.dtsi delete mode 100644 arch/arm/dts/rk3188.dtsi delete mode 100644 arch/arm/dts/rk3xxx.dtsi (limited to 'arch/arm') diff --git a/arch/arm/dts/rk3188-clocks.dtsi b/arch/arm/dts/rk3188-clocks.dtsi deleted file mode 100644 index b1b92dc245..0000000000 --- a/arch/arm/dts/rk3188-clocks.dtsi +++ /dev/null @@ -1,289 +0,0 @@ -/* - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/ { - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * This is a dummy clock, to be used as placeholder on - * other mux clocks when a specific parent clock is not - * yet implemented. It should be dropped when the driver - * is complete. - */ - dummy: dummy { - compatible = "fixed-clock"; - clock-frequency = <0>; - #clock-cells = <0>; - }; - - xin24m: xin24m { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - - dummy48m: dummy48m { - compatible = "fixed-clock"; - clock-frequency = <48000000>; - #clock-cells = <0>; - }; - - dummy150m: dummy150m { - compatible = "fixed-clock"; - clock-frequency = <150000000>; - #clock-cells = <0>; - }; - - clk_gates0: gate-clk@200000d0 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000d0 0x4>; - clocks = <&dummy150m>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_core_periph", "gate_cpu_gpll", - "gate_ddrphy", "gate_aclk_cpu", - "gate_hclk_cpu", "gate_pclk_cpu", - "gate_atclk_cpu", "gate_aclk_core", - "reserved", "gate_i2s0", - "gate_i2s0_frac", "reserved", - "reserved", "gate_spdif", - "gate_spdif_frac", "gate_testclk"; - - #clock-cells = <1>; - }; - - clk_gates1: gate-clk@200000d4 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000d4 0x4>; - clocks = <&xin24m>, <&xin24m>, - <&xin24m>, <&dummy>, - <&dummy>, <&xin24m>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>; - - clock-output-names = - "gate_timer0", "gate_timer1", - "gate_timer3", "gate_jtag", - "gate_aclk_lcdc1_src", "gate_otgphy0", - "gate_otgphy1", "gate_ddr_gpll", - "gate_uart0", "gate_frac_uart0", - "gate_uart1", "gate_frac_uart1", - "gate_uart2", "gate_frac_uart2", - "gate_uart3", "gate_frac_uart3"; - - #clock-cells = <1>; - }; - - clk_gates2: gate-clk@200000d8 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000d8 0x4>; - clocks = <&clk_gates2 1>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&clk_gates2 3>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy48m>, - <&dummy>, <&dummy48m>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_periph_src", "gate_aclk_periph", - "gate_hclk_periph", "gate_pclk_periph", - "gate_smc", "gate_mac", - "gate_hsadc", "gate_hsadc_frac", - "gate_saradc", "gate_spi0", - "gate_spi1", "gate_mmc0", - "gate_mac_lbtest", "gate_mmc1", - "gate_emmc", "reserved"; - - #clock-cells = <1>; - }; - - clk_gates3: gate-clk@200000dc { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000dc 0x4>; - clocks = <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&xin24m>, <&xin24m>, - <&dummy>, <&dummy>, - <&xin24m>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&xin24m>, <&dummy>; - - clock-output-names = - "gate_aclk_lcdc0_src", "gate_dclk_lcdc0", - "gate_dclk_lcdc1", "gate_pclkin_cif0", - "gate_timer2", "gate_timer4", - "gate_hsicphy", "gate_cif0_out", - "gate_timer5", "gate_aclk_vepu", - "gate_hclk_vepu", "gate_aclk_vdpu", - "gate_hclk_vdpu", "reserved", - "gate_timer6", "gate_aclk_gpu_src"; - - #clock-cells = <1>; - }; - - clk_gates4: gate-clk@200000e0 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000e0 0x4>; - clocks = <&clk_gates2 2>, <&clk_gates2 3>, - <&clk_gates2 1>, <&clk_gates2 1>, - <&clk_gates2 1>, <&clk_gates2 2>, - <&clk_gates2 2>, <&clk_gates2 2>, - <&clk_gates0 4>, <&clk_gates0 4>, - <&clk_gates0 3>, <&dummy>, - <&clk_gates0 3>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_hclk_peri_axi_matrix", "gate_pclk_peri_axi_matrix", - "gate_aclk_cpu_peri", "gate_aclk_peri_axi_matrix", - "gate_aclk_pei_niu", "gate_hclk_usb_peri", - "gate_hclk_peri_ahb_arbi", "gate_hclk_emem_peri", - "gate_hclk_cpubus", "gate_hclk_ahb2apb", - "gate_aclk_strc_sys", "reserved", - "gate_aclk_intmem", "reserved", - "gate_hclk_imem1", "gate_hclk_imem0"; - - #clock-cells = <1>; - }; - - clk_gates5: gate-clk@200000e4 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000e4 0x4>; - clocks = <&clk_gates0 3>, <&clk_gates2 1>, - <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates0 4>, <&clk_gates0 5>, - <&clk_gates2 1>, <&clk_gates2 2>, - <&clk_gates2 2>, <&clk_gates2 2>, - <&clk_gates2 2>, <&clk_gates4 5>; - - clock-output-names = - "gate_aclk_dmac1", "gate_aclk_dmac2", - "gate_pclk_efuse", "gate_pclk_tzpc", - "gate_pclk_grf", "gate_pclk_pmu", - "gate_hclk_rom", "gate_pclk_ddrupctl", - "gate_aclk_smc", "gate_hclk_nandc", - "gate_hclk_mmc0", "gate_hclk_mmc1", - "gate_hclk_emmc", "gate_hclk_otg0"; - - #clock-cells = <1>; - }; - - clk_gates6: gate-clk@200000e8 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000e8 0x4>; - clocks = <&clk_gates3 0>, <&clk_gates0 4>, - <&clk_gates0 4>, <&clk_gates1 4>, - <&clk_gates0 4>, <&clk_gates3 0>, - <&dummy>, <&dummy>, - <&clk_gates3 0>, <&clk_gates0 4>, - <&clk_gates0 4>, <&clk_gates1 4>, - <&clk_gates0 4>, <&clk_gates3 0>; - - clock-output-names = - "gate_aclk_lcdc0", "gate_hclk_lcdc0", - "gate_hclk_lcdc1", "gate_aclk_lcdc1", - "gate_hclk_cif0", "gate_aclk_cif0", - "reserved", "reserved", - "gate_aclk_ipp", "gate_hclk_ipp", - "gate_hclk_rga", "gate_aclk_rga", - "gate_hclk_vio_bus", "gate_aclk_vio0"; - - #clock-cells = <1>; - }; - - clk_gates7: gate-clk@200000ec { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000ec 0x4>; - clocks = <&clk_gates2 2>, <&clk_gates0 4>, - <&clk_gates0 4>, <&dummy>, - <&dummy>, <&clk_gates2 2>, - <&clk_gates2 2>, <&clk_gates0 5>, - <&dummy>, <&clk_gates0 5>, - <&clk_gates0 5>, <&clk_gates2 3>, - <&clk_gates2 3>, <&clk_gates2 3>, - <&clk_gates2 3>, <&clk_gates2 3>; - - clock-output-names = - "gate_hclk_emac", "gate_hclk_spdif", - "gate_hclk_i2s0_2ch", "gate_hclk_otg1", - "gate_hclk_hsic", "gate_hclk_hsadc", - "gate_hclk_pidf", "gate_pclk_timer0", - "reserved", "gate_pclk_timer2", - "gate_pclk_pwm01", "gate_pclk_pwm23", - "gate_pclk_spi0", "gate_pclk_spi1", - "gate_pclk_saradc", "gate_pclk_wdt"; - - #clock-cells = <1>; - }; - - clk_gates8: gate-clk@200000f0 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000f0 0x4>; - clocks = <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates2 3>, <&clk_gates2 3>, - <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates2 3>, <&clk_gates2 3>, - <&clk_gates2 3>, <&clk_gates0 5>, - <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates2 3>, <&dummy>; - - clock-output-names = - "gate_pclk_uart0", "gate_pclk_uart1", - "gate_pclk_uart2", "gate_pclk_uart3", - "gate_pclk_i2c0", "gate_pclk_i2c1", - "gate_pclk_i2c2", "gate_pclk_i2c3", - "gate_pclk_i2c4", "gate_pclk_gpio0", - "gate_pclk_gpio1", "gate_pclk_gpio2", - "gate_pclk_gpio3", "gate_aclk_gps"; - - #clock-cells = <1>; - }; - - clk_gates9: gate-clk@200000f4 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000f4 0x4>; - clocks = <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_clk_core_dbg", "gate_pclk_dbg", - "gate_clk_trace", "gate_atclk", - "gate_clk_l2c", "gate_aclk_vio1", - "gate_pclk_publ", "gate_aclk_gpu"; - - #clock-cells = <1>; - }; - }; - -}; diff --git a/arch/arm/dts/rk3188-radxarock.dts b/arch/arm/dts/rk3188-radxarock.dts index 2d49d6981c..47b2487dd9 100644 --- a/arch/arm/dts/rk3188-radxarock.dts +++ b/arch/arm/dts/rk3188-radxarock.dts @@ -12,22 +12,30 @@ * GNU General Public License for more details. */ -/dts-v1/; -#include "rk3188.dtsi" +#include / { - model = "Radxa Rock"; - compatible = "radxa,rock", "rockchip,rk3188"; + chosen { + linux,stdout-path = &uart2; - memory { - reg = <0x60000000 0x80000000>; - }; - - soc { - uart2: serial@20064000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; + environment { + compatible = "barebox,environment"; + device-path = &mmc0, "partname:barebox-environment"; status = "okay"; }; }; }; + +&mmc0 { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x80000>; + }; + partition@1 { + label = "barebox-environment"; + reg = <0x80000 0x80000>; + }; +}; diff --git a/arch/arm/dts/rk3188.dtsi b/arch/arm/dts/rk3188.dtsi deleted file mode 100644 index 277a915096..0000000000 --- a/arch/arm/dts/rk3188.dtsi +++ /dev/null @@ -1,306 +0,0 @@ -/* - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include "rk3xxx.dtsi" -#include "rk3188-clocks.dtsi" - -/* barebox additions */ -/ { - soc { - ethernet@10204000 { - compatible = "snps,arc-emac"; - reg = <0x10204000 0x100>; - interrupts = ; - clock-frequency = <50000000>; - max-speed = <100>; - phy = <&phy0>; - pinctrl-names = "default"; - pinctrl-0 = <&emac0_pins>; - - #address-cells = <1>; - #size-cells = <0>; - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; - - pinctrl@20008000 { - emac0 { - emac0_pins: emac0-pins { - rockchip,pins = , - , - , - , - , - , - , - , - , - ; - }; - }; - }; - }; -}; - -/* original rk3188.dtsi from Linux 3.16 */ -/ { - compatible = "rockchip,rk3188"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "rockchip,rk3066-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x1>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x2>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x3>; - }; - }; - - soc { - global-timer@1013c200 { - interrupts = ; - }; - - local-timer@1013c600 { - interrupts = ; - }; - - sram: sram@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x8000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10080000 0x8000>; - - smp-sram@0 { - compatible = "rockchip,rk3066-smp-sram"; - reg = <0x0 0x50>; - }; - }; - - pinctrl@20008000 { - compatible = "rockchip,rk3188-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmu>; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@0x2000a000 { - compatible = "rockchip,rk3188-gpio-bank0"; - reg = <0x2000a000 0x100>; - interrupts = ; - clocks = <&clk_gates8 9>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@0x2003c000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003c000 0x100>; - interrupts = ; - clocks = <&clk_gates8 10>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@2003e000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003e000 0x100>; - interrupts = ; - clocks = <&clk_gates8 11>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio3@20080000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20080000 0x100>; - interrupts = ; - clocks = <&clk_gates8 12>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg_pull_up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg_pull_down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg_pull_none { - bias-disable; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = , - ; - }; - - uart0_cts: uart0-cts { - rockchip,pins = ; - }; - - uart0_rts: uart0-rts { - rockchip,pins = ; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = , - ; - }; - - uart1_cts: uart1-cts { - rockchip,pins = ; - }; - - uart1_rts: uart1-rts { - rockchip,pins = ; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = , - ; - }; - /* no rts / cts for uart2 */ - }; - - uart3 { - uart3_xfer: uart3-xfer { - rockchip,pins = , - ; - }; - - uart3_cts: uart3-cts { - rockchip,pins = ; - }; - - uart3_rts: uart3-rts { - rockchip,pins = ; - }; - }; - - sd0 { - sd0_clk: sd0-clk { - rockchip,pins = ; - }; - - sd0_cmd: sd0-cmd { - rockchip,pins = ; - }; - - sd0_cd: sd0-cd { - rockchip,pins = ; - }; - - sd0_wp: sd0-wp { - rockchip,pins = ; - }; - - sd0_pwr: sd0-pwr { - rockchip,pins = ; - }; - - sd0_bus1: sd0-bus-width1 { - rockchip,pins = ; - }; - - sd0_bus4: sd0-bus-width4 { - rockchip,pins = , - , - , - ; - }; - }; - - sd1 { - sd1_clk: sd1-clk { - rockchip,pins = ; - }; - - sd1_cmd: sd1-cmd { - rockchip,pins = ; - }; - - sd1_cd: sd1-cd { - rockchip,pins = ; - }; - - sd1_wp: sd1-wp { - rockchip,pins = ; - }; - - sd1_bus1: sd1-bus-width1 { - rockchip,pins = ; - }; - - sd1_bus4: sd1-bus-width4 { - rockchip,pins = , - , - , - ; - }; - }; - }; - }; -}; diff --git a/arch/arm/dts/rk3xxx.dtsi b/arch/arm/dts/rk3xxx.dtsi deleted file mode 100644 index 2adf1cc9e8..0000000000 --- a/arch/arm/dts/rk3xxx.dtsi +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include "skeleton.dtsi" - -/ { - interrupt-parent = <&gic>; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - scu@1013c000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x1013c000 0x100>; - }; - - pmu: pmu@20004000 { - compatible = "rockchip,rk3066-pmu", "syscon"; - reg = <0x20004000 0x100>; - }; - - grf: grf@20008000 { - compatible = "syscon"; - reg = <0x20008000 0x200>; - }; - - gic: interrupt-controller@1013d000 { - compatible = "arm,cortex-a9-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x1013d000 0x1000>, - <0x1013c100 0x0100>; - }; - - L2: l2-cache-controller@10138000 { - compatible = "arm,pl310-cache"; - reg = <0x10138000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - global-timer@1013c200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x1013c200 0x20>; - interrupts = ; - clocks = <&dummy150m>; - }; - - local-timer@1013c600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x1013c600 0x20>; - interrupts = ; - clocks = <&dummy150m>; - }; - - uart0: serial@10124000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10124000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&clk_gates1 8>; - status = "disabled"; - }; - - uart1: serial@10126000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10126000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&clk_gates1 10>; - status = "disabled"; - }; - - uart2: serial@20064000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20064000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&clk_gates1 12>; - status = "disabled"; - }; - - uart3: serial@20068000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20068000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&clk_gates1 14>; - status = "disabled"; - }; - - dwmmc@10214000 { - compatible = "rockchip,rk2928-dw-mshc"; - reg = <0x10214000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - clocks = <&clk_gates5 10>, <&clk_gates2 11>; - clock-names = "biu", "ciu"; - - status = "disabled"; - }; - - dwmmc@10218000 { - compatible = "rockchip,rk2928-dw-mshc"; - reg = <0x10218000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - clocks = <&clk_gates5 11>, <&clk_gates2 13>; - clock-names = "biu", "ciu"; - - status = "disabled"; - }; - }; -}; -- cgit v1.2.3 From 290161a2f07044db0908cd003accf03a6c0d4924 Mon Sep 17 00:00:00 2001 From: Andrey Panov Date: Wed, 4 Mar 2015 23:11:44 +0300 Subject: ARM: Rockchip: Update Radxa Rock board Signed-off-by: Andrey Panov Signed-off-by: Sascha Hauer --- arch/arm/boards/radxa-rock/board.c | 35 ++++++-------------------- arch/arm/boards/radxa-rock/env/boot/mshc1 | 9 +++++++ arch/arm/boards/radxa-rock/env/boot/mshc1-old | 8 ++++++ arch/arm/boards/radxa-rock/env/init/bootsource | 7 ++++++ arch/arm/boards/radxa-rock/env/nv/hostname | 1 + 5 files changed, 32 insertions(+), 28 deletions(-) create mode 100644 arch/arm/boards/radxa-rock/env/boot/mshc1 create mode 100644 arch/arm/boards/radxa-rock/env/boot/mshc1-old create mode 100644 arch/arm/boards/radxa-rock/env/init/bootsource create mode 100644 arch/arm/boards/radxa-rock/env/nv/hostname (limited to 'arch/arm') diff --git a/arch/arm/boards/radxa-rock/board.c b/arch/arm/boards/radxa-rock/board.c index 3d9b5be344..ec053f9123 100644 --- a/arch/arm/boards/radxa-rock/board.c +++ b/arch/arm/boards/radxa-rock/board.c @@ -16,8 +16,9 @@ #include #include #include -#include +#include #include +#include static struct i2c_board_info radxa_rock_i2c_devices[] = { { @@ -43,20 +44,6 @@ static void radxa_rock_pmic_init(void) act8846_set_bits(pmic, ACT8846_LDO9_CTRL, BIT(7), BIT(7)); } -static int setup_plls(void) -{ - if (!of_machine_is_compatible("radxa,rock")) - return 0; - - /* Codec PLL frequency: 594 MHz */ - rk3188_pll_set_parameters(RK3188_CPLL, 2, 198, 4); - /* General PLL frequency: 300 MHz */ - rk3188_pll_set_parameters(RK3188_GPLL, 1, 50, 4); - - return 0; -} -coredevice_initcall(setup_plls); - static int devices_init(void) { if (!of_machine_is_compatible("radxa,rock")) @@ -68,20 +55,12 @@ static int devices_init(void) radxa_rock_pmic_init(); - /* Set mac_pll divisor to 6 (50MHz output) */ - writel((5 << 8) | (0x1f << 24), 0x20000098); + armlinux_set_architecture(3066); - return 0; -} -device_initcall(devices_init); - -static int hostname_init(void) -{ - if (!of_machine_is_compatible("radxa,rock")) - return 0; - - barebox_set_hostname("radxa-rock"); + /* Map SRAM to address 0, kernel relies on this */ + writel((RK_SOC_CON0_REMAP << 16) | RK_SOC_CON0_REMAP, + RK_GRF_BASE + RK_GRF_SOC_CON0); return 0; } -postcore_initcall(hostname_init); +device_initcall(devices_init); diff --git a/arch/arm/boards/radxa-rock/env/boot/mshc1 b/arch/arm/boards/radxa-rock/env/boot/mshc1 new file mode 100644 index 0000000000..964b6cc3eb --- /dev/null +++ b/arch/arm/boards/radxa-rock/env/boot/mshc1 @@ -0,0 +1,9 @@ +#!/bin/sh + +mount /dev/mshc1.0 + +oftree -f +oftree -l /mnt/mshc1.0/rk3188-radxarock.dtb + +global.bootm.image=/mnt/mshc1.0/zImage +global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootwait" diff --git a/arch/arm/boards/radxa-rock/env/boot/mshc1-old b/arch/arm/boards/radxa-rock/env/boot/mshc1-old new file mode 100644 index 0000000000..1e1b57751d --- /dev/null +++ b/arch/arm/boards/radxa-rock/env/boot/mshc1-old @@ -0,0 +1,8 @@ +#!/bin/sh + +mount /dev/mshc1.0 + +oftree -f + +global.bootm.image=/mnt/mshc1.0/zImage-old +global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootwait" diff --git a/arch/arm/boards/radxa-rock/env/init/bootsource b/arch/arm/boards/radxa-rock/env/init/bootsource new file mode 100644 index 0000000000..4e8299b8dd --- /dev/null +++ b/arch/arm/boards/radxa-rock/env/init/bootsource @@ -0,0 +1,7 @@ +#!/bin/sh + +if [ -n "$nv.boot.default" ]; then + exit +fi + +global.boot.default=mshc1 diff --git a/arch/arm/boards/radxa-rock/env/nv/hostname b/arch/arm/boards/radxa-rock/env/nv/hostname new file mode 100644 index 0000000000..16523aca12 --- /dev/null +++ b/arch/arm/boards/radxa-rock/env/nv/hostname @@ -0,0 +1 @@ +radxa-rock -- cgit v1.2.3 From 9a9a7891e750367b477f5d6d0a9a524df74e43e0 Mon Sep 17 00:00:00 2001 From: Andrey Panov Date: Wed, 4 Mar 2015 23:11:40 +0300 Subject: ARM: Rockchip: Remove unused files from mach-rockchip Signed-off-by: Andrey Panov Signed-off-by: Sascha Hauer --- arch/arm/mach-rockchip/Makefile | 1 - arch/arm/mach-rockchip/include/mach/rockchip-pll.h | 26 ------ arch/arm/mach-rockchip/pll.c | 102 --------------------- 3 files changed, 129 deletions(-) delete mode 100644 arch/arm/mach-rockchip/include/mach/rockchip-pll.h delete mode 100644 arch/arm/mach-rockchip/pll.c (limited to 'arch/arm') diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 6f4ec169e3..820eb10ac2 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -1,2 +1 @@ obj-y += core.o -obj-y += pll.o \ No newline at end of file diff --git a/arch/arm/mach-rockchip/include/mach/rockchip-pll.h b/arch/arm/mach-rockchip/include/mach/rockchip-pll.h deleted file mode 100644 index c2cd888b00..0000000000 --- a/arch/arm/mach-rockchip/include/mach/rockchip-pll.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (C) 2014 Beniamino Galvani - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MACH_ROCKCHIP_PLL_H -#define __MACH_ROCKCHIP_PLL_H - -enum rk3188_plls { - RK3188_APLL = 0, /* ARM */ - RK3188_DPLL, /* DDR */ - RK3188_CPLL, /* Codec */ - RK3188_GPLL, /* General */ -}; - -int rk3188_pll_set_parameters(int pll, int nr, int nf, int no); - -#endif /* __MACH_ROCKCHIP_PLL_H */ diff --git a/arch/arm/mach-rockchip/pll.c b/arch/arm/mach-rockchip/pll.c deleted file mode 100644 index fce192ccdb..0000000000 --- a/arch/arm/mach-rockchip/pll.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (C) 2014 Beniamino Galvani - * - * Based on Linux clk driver: - * Copyright (c) 2014 MundoReader S.L. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -#define RK3188_CLK_BASE 0x20000000 -#define RK3188_PLL_LOCK_REG 0x200080ac - -#define PLL_MODE_MASK 0x3 -#define PLL_MODE_SLOW 0x0 -#define PLL_MODE_NORM 0x1 -#define PLL_MODE_DEEP 0x2 - -#define PLL_RESET_DELAY(nr) ((nr * 500) / 24 + 1) - -#define PLLCON0_OD_MASK 0xf -#define PLLCON0_OD_SHIFT 0 -#define PLLCON0_NR_MASK 0x3f -#define PLLCON0_NR_SHIFT 8 - -#define PLLCON1_NF_MASK 0x1fff -#define PLLCON1_NF_SHIFT 0 - -#define PLLCON2_BWADJ_MASK 0xfff -#define PLLCON2_BWADJ_SHIFT 0 - -#define PLLCON3_RESET (1 << 1) -#define PLLCON3_BYPASS (1 << 0) - -struct rockchip_pll_data { - int con_base; - int mode_offset; - int mode_shift; - int lock_shift; -}; - -struct rockchip_pll_data rk3188_plls[] = { - { 0x00, 0x40, 0x00, 0x06 }, - { 0x10, 0x40, 0x04, 0x05 }, - { 0x20, 0x40, 0x08, 0x07 }, - { 0x30, 0x40, 0x0c, 0x08 }, -}; - -#define HIWORD_UPDATE(val, mask, shift) \ - ((val) << (shift) | (mask) << ((shift) + 16)) - -int rk3188_pll_set_parameters(int pll, int nr, int nf, int no) -{ - struct rockchip_pll_data *d = &rk3188_plls[pll]; - int delay = 0; - - debug("rk3188 pll %d: set param %d %d %d\n", pll, nr, nf, no); - - /* pull pll in slow mode */ - writel(HIWORD_UPDATE(PLL_MODE_SLOW, PLL_MODE_MASK, d->mode_shift), - RK3188_CLK_BASE + d->mode_offset); - /* enter reset */ - writel(HIWORD_UPDATE(PLLCON3_RESET, PLLCON3_RESET, 0), - RK3188_CLK_BASE + d->con_base + 12); - - /* update pll values */ - writel(HIWORD_UPDATE(nr - 1, PLLCON0_NR_MASK, PLLCON0_NR_SHIFT) | - HIWORD_UPDATE(no - 1, PLLCON0_OD_MASK, PLLCON0_OD_SHIFT), - RK3188_CLK_BASE + d->con_base + 0); - writel(HIWORD_UPDATE(nf - 1, PLLCON1_NF_MASK, PLLCON1_NF_SHIFT), - RK3188_CLK_BASE + d->con_base + 4); - writel(HIWORD_UPDATE(nf >> 1, PLLCON2_BWADJ_MASK, PLLCON2_BWADJ_SHIFT), - RK3188_CLK_BASE + d->con_base + 8); - - /* leave reset and wait the reset_delay */ - writel(HIWORD_UPDATE(0, PLLCON3_RESET, 0), - RK3188_CLK_BASE + d->con_base + 12); - udelay(PLL_RESET_DELAY(nr)); - - /* wait for the pll to lock */ - while (delay++ < 24000000) { - if (readl(RK3188_PLL_LOCK_REG) & BIT(d->lock_shift)) - break; - } - - /* go back to normal mode */ - writel(HIWORD_UPDATE(PLL_MODE_NORM, PLL_MODE_MASK, d->mode_shift), - RK3188_CLK_BASE + d->mode_offset); - - return 0; -} -EXPORT_SYMBOL(rk3188_pll_set_parameters); -- cgit v1.2.3