From 03f8b48daa66a3a613dde735eebbeff222edba40 Mon Sep 17 00:00:00 2001 From: Enrik Berkhan Date: Fri, 14 Mar 2008 17:01:25 +0100 Subject: Some Blackfin CPU revs don't handle the clock pre-divider correctly on reset See anomaly 05000242. Signed-Off-By: Enrik Berkhan --- arch/blackfin/cpu-bf561/init_sdram.S | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/blackfin/cpu-bf561') diff --git a/arch/blackfin/cpu-bf561/init_sdram.S b/arch/blackfin/cpu-bf561/init_sdram.S index 84fda76bcd..88e592a574 100644 --- a/arch/blackfin/cpu-bf561/init_sdram.S +++ b/arch/blackfin/cpu-bf561/init_sdram.S @@ -92,6 +92,18 @@ init_sdram: * all other bits set to zero */ + /* first, explicitly enable DF, due to anomaly 05000242 */ + p0.h = hi(PLL_CTL); + p0.l = lo(PLL_CTL); /* Load the address */ + r0.l = w[p0]; + r1 = 1; + r0 = r0 | r1; + cli r2; + ssync; + w[p0] = r0.l; + idle; + sti r2; + r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */ r0 = r0 << 9; /* Shift it over, */ r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/ -- cgit v1.2.3