From 16b50fcd7f96a71a043e56fd3cfa745d44623e35 Mon Sep 17 00:00:00 2001 From: Antony Pavlov Date: Mon, 8 Sep 2014 10:53:06 +0400 Subject: openrisc: dts: import or1ksim.dts from linux-3.16 There are some minor changes with original linux-3.16 file: * the 'model' attribute is added (it used for barebox banner board name); * all "opencores,*-rtlsvn*" 'compatible' attribute values are dropped; these values are not actually used in the device drivers. Signed-off-by: Antony Pavlov Cc: Franck Jullien Signed-off-by: Sascha Hauer --- arch/openrisc/dts/or1ksim.dts | 51 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 arch/openrisc/dts/or1ksim.dts (limited to 'arch/openrisc') diff --git a/arch/openrisc/dts/or1ksim.dts b/arch/openrisc/dts/or1ksim.dts new file mode 100644 index 0000000000..7316cc6770 --- /dev/null +++ b/arch/openrisc/dts/or1ksim.dts @@ -0,0 +1,51 @@ +/dts-v1/; +/ { + model = "or1ksim"; + compatible = "opencores,or1ksim"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&pic>; + + chosen { + bootargs = "console=uart,mmio,0x90000000,115200"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x02000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "opencores,or1200-rtlsvn481"; + reg = <0>; + clock-frequency = <20000000>; + }; + }; + + /* + * OR1K PIC is built into CPU and accessed via special purpose + * registers. It is not addressable and, hence, has no 'reg' + * property. + */ + pic: pic { + compatible = "opencores,or1k-pic"; + #interrupt-cells = <1>; + interrupt-controller; + }; + + serial0: serial@90000000 { + compatible = "ns16550a"; + reg = <0x90000000 0x100>; + interrupts = <2>; + clock-frequency = <50000000>; + }; + + enet0: ethoc@92000000 { + compatible = "opencores,ethoc"; + reg = <0x92000000 0x100>; + interrupts = <4>; + }; +}; -- cgit v1.2.3