From 1018c7f7320ca34c899b87afe97fe4999cfb2766 Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Fri, 5 Dec 2014 17:41:49 +0100 Subject: ARM: socfpga: socrates: update handoff files to 14.0 Signed-off-by: Steffen Trumtrar Signed-off-by: Sascha Hauer --- .../boards/ebv-socrates/iocsr_config_cyclone5.c | 99 +++++++---- arch/arm/boards/ebv-socrates/pinmux_config.c | 33 +++- arch/arm/boards/ebv-socrates/pll_config.h | 194 +++++++++++---------- arch/arm/boards/ebv-socrates/sdram_config.h | 49 +++++- 4 files changed, 242 insertions(+), 133 deletions(-) (limited to 'arch') diff --git a/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c b/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c index aa02724643..ab6733f92b 100644 --- a/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c +++ b/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c @@ -1,4 +1,31 @@ -/* This file is generated by Preloader Generator */ +/* GENERATED FILE - DO NOT EDIT */ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Altera Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ #include @@ -121,7 +148,7 @@ static const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2 static const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = { 0x0CC20D80, - 0x8C3000FF, + 0x0C3000FF, 0x0A804001, 0x07900000, 0x08020000, @@ -171,17 +198,17 @@ static const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3 0x00001000, 0xA0000034, 0x0D000001, - 0xA0680514, - 0xCF034069, - 0x1E781A03, - 0x805140D0, - 0x34069A06, - 0x01A03CF0, - 0x340D0000, - 0x1860680D, - 0x03CF0340, + 0xC0680A28, + 0x45034030, + 0x12481A01, + 0x80A280D0, + 0x34030C06, + 0x01A01450, + 0x280D0000, + 0x30C0680A, + 0x02490340, 0xD000001A, - 0x0680D340, + 0x0680A280, 0x10040000, 0x00200000, 0x10040000, @@ -245,17 +272,17 @@ static const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3 0x00001000, 0xA0000034, 0x0D000001, - 0x60680D34, - 0xCF034018, - 0x0E381A03, - 0x80D340D0, - 0x34018606, + 0xC0680A28, + 0x49034030, + 0x12481A02, + 0x80A280D0, + 0x34030C06, 0x01A00040, - 0x340D0002, - 0x1860680D, - 0x03CF0340, - 0xD01E781A, - 0x06805140, + 0x280D0002, + 0x30C0680A, + 0x02490340, + 0xD00A281A, + 0x0680A280, 0x10040000, 0x00200000, 0x10040000, @@ -316,9 +343,9 @@ static const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3 0x00104120, 0x00000200, 0xAC0D5F80, - 0xFFFFFFFF, - 0x14F3690D, - 0x1A041414, + 0x7FFFFFFF, + 0x14F36080, + 0x1A041404, 0x00D00000, 0x18864000, 0x49247A06, @@ -327,7 +354,7 @@ static const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3 0x0342E388, 0x821A0000, 0x0000D000, - 0x028A0680, + 0x05140680, 0xD949247A, 0x1EF228A3, 0x88F6D145, @@ -390,16 +417,16 @@ static const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3 0x00104120, 0x00000200, 0xAC0D5F80, - 0xFFFFFFFF, - 0x14F3690D, - 0x1A041414, + 0x7FFFFFFF, + 0x14F36080, + 0x1A041404, 0x00D00000, 0x18864000, 0x49247A06, 0xF3CF23D5, 0xF4D1451E, 0x034A9248, - 0x821A00C3, + 0x821A038E, 0x0000D000, 0x00000680, 0xD949247A, @@ -464,9 +491,9 @@ static const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3 0x00104120, 0x00000200, 0xAC0D5F80, - 0xFFFFFFFF, - 0x14F3690D, - 0x1A041414, + 0x7FFFFFFF, + 0x14F36080, + 0x1A041404, 0x00D00000, 0x18864000, 0x49247A06, @@ -538,9 +565,9 @@ static const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3 0x00104120, 0x00000200, 0xAC0D5F80, - 0xFFFFFFFF, - 0x14F1690D, - 0x1A041414, + 0x7FFFFFFF, + 0x14F16080, + 0x1A041404, 0x00D00000, 0x08864000, 0x49247A02, diff --git a/arch/arm/boards/ebv-socrates/pinmux_config.c b/arch/arm/boards/ebv-socrates/pinmux_config.c index e259078410..faa3122466 100644 --- a/arch/arm/boards/ebv-socrates/pinmux_config.c +++ b/arch/arm/boards/ebv-socrates/pinmux_config.c @@ -1,3 +1,34 @@ +/* GENERATED FILE - DO NOT EDIT */ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Altera Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + /* pin MUX configuration data */ static unsigned long sys_mgr_init_table[] = { 0, /* EMACIO0 */ @@ -207,4 +238,4 @@ static unsigned long sys_mgr_init_table[] = { 0, /* SPIM1USEFPGA */ 0, /* USB0USEFPGA */ 0 /* SPIM0USEFPGA */ -}; +}; \ No newline at end of file diff --git a/arch/arm/boards/ebv-socrates/pll_config.h b/arch/arm/boards/ebv-socrates/pll_config.h index 7682f6302d..083ebd4a87 100644 --- a/arch/arm/boards/ebv-socrates/pll_config.h +++ b/arch/arm/boards/ebv-socrates/pll_config.h @@ -1,97 +1,113 @@ +/* GENERATED FILE - DO NOT EDIT */ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Altera Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + #ifndef _PRELOADER_PLL_CONFIG_H_ #define _PRELOADER_PLL_CONFIG_H_ -/* PLL configuration data */ -/* Main PLL */ -#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0) -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (63) -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0) -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0) -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0) -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (3) -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (3) -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (15) -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1) -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1) -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1) -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (1) -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0) -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1) -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0) -/* - * To tell where is the clock source: - * 0 = MAINPLL - * 1 = PERIPHPLL - */ -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1) -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1) +#define CONFIG_HPS_DBCTRL_STAYOSC1 (1) -/* Peripheral PLL */ -#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (1) -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (79) -/* - * To tell where is the VCOs source: - * 0 = EOSC1 - * 1 = EOSC2 - * 2 = F2S - */ -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0) -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (3) -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (3) -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (1) -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (19) -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4) -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (9) -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0) -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (0) -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (1) -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (1) -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249) -/* - * To tell where is the clock source: - * 0 = F2S_PERIPH_REF_CLK - * 1 = MAIN_CLK - * 2 = PERIPH_CLK - */ -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (1) -#define CONFIG_HPS_PERPLLGRP_SRC_NAND (2) -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1) +#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0) +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (63) +#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0) +#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0) +#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0) +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (3) +#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (511) +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (15) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0) +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1) +#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0) +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1) +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1) -/* SDRAM PLL */ -#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (2) -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (79) -/* - * To tell where is the VCOs source: - * 0 = EOSC1 - * 1 = EOSC2 - * 2 = F2S - */ -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0) -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1) -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0) -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0) -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0) -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1) -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4) -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (5) -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0) +#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (0) +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (39) +#define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0) +#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (511) +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (3) +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (511) +#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4) +#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4) +#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (511) +#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0) +#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (0) +#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (1) +#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (4) +#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249) +#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (2) +#define CONFIG_HPS_PERPLLGRP_SRC_NAND (2) +#define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1) + +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (2) +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (79) +#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0) +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1) +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0) +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0) +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0) +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1) +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4) +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (5) +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0) + +#define CONFIG_HPS_CLK_OSC1_HZ (25000000) +#define CONFIG_HPS_CLK_OSC2_HZ (25000000) +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ (0) +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ (0) +#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000) +#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000) +#define CONFIG_HPS_CLK_SDRVCO_HZ (666666666) +#define CONFIG_HPS_CLK_OSC1_HZ (25000000) +#define CONFIG_HPS_CLK_OSC2_HZ (25000000) +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ (0) +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ (0) +#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000) +#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000) +#define CONFIG_HPS_CLK_EMAC0_HZ (1953125) +#define CONFIG_HPS_CLK_EMAC1_HZ (250000000) +#define CONFIG_HPS_CLK_USBCLK_HZ (200000000) +#define CONFIG_HPS_CLK_NAND_HZ (50000000) +#define CONFIG_HPS_CLK_SDMMC_HZ (200000000) +#define CONFIG_HPS_CLK_QSPI_HZ (400000000) +#define CONFIG_HPS_CLK_SPIM_HZ (200000000) +#define CONFIG_HPS_CLK_CAN0_HZ (100000000) +#define CONFIG_HPS_CLK_CAN1_HZ (12500000) +#define CONFIG_HPS_CLK_GPIODB_HZ (32000) +#define CONFIG_HPS_CLK_L4_MP_HZ (100000000) +#define CONFIG_HPS_CLK_L4_SP_HZ (100000000) -/* Info for driver */ -#define CONFIG_HPS_CLK_OSC1_HZ (25000000) -#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000) -#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000) -#define CONFIG_HPS_CLK_SDRVCO_HZ (600000000) -#define CONFIG_HPS_CLK_EMAC0_HZ (50000000) -#define CONFIG_HPS_CLK_EMAC1_HZ (50000000) -#define CONFIG_HPS_CLK_USBCLK_HZ (200000000) -#define CONFIG_HPS_CLK_NAND_HZ (100000000) -#define CONFIG_HPS_CLK_SDMMC_HZ (50000000) -#define CONFIG_HPS_CLK_QSPI_HZ (400000000) -#define CONFIG_HPS_CLK_SPIM_HZ (200000000) -#define CONFIG_HPS_CLK_CAN0_HZ (100000000) -#define CONFIG_HPS_CLK_CAN1_HZ (100000000) -#define CONFIG_HPS_CLK_GPIODB_HZ (32000) -#define CONFIG_HPS_CLK_L4_MP_HZ (100000000) -#define CONFIG_HPS_CLK_L4_SP_HZ (100000000) +#define CONFIG_HPS_ALTERAGRP_MPUCLK (1) +#define CONFIG_HPS_ALTERAGRP_MAINCLK (3) +#define CONFIG_HPS_ALTERAGRP_DBGATCLK (3) #endif /* _PRELOADER_PLL_CONFIG_H_ */ diff --git a/arch/arm/boards/ebv-socrates/sdram_config.h b/arch/arm/boards/ebv-socrates/sdram_config.h index 94d1cbe470..16dd783bf0 100644 --- a/arch/arm/boards/ebv-socrates/sdram_config.h +++ b/arch/arm/boards/ebv-socrates/sdram_config.h @@ -1,3 +1,32 @@ +/* GENERATED FILE - DO NOT EDIT */ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Altera Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + #ifndef __SDRAM_CONFIG_H #define __SDRAM_CONFIG_H @@ -26,9 +55,10 @@ #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC (17) #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD (4) #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD (4) -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT (200) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT (512) #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT (3) #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES (0) +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES (8) #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS (10) #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS (15) #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS (3) @@ -36,6 +66,7 @@ #define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH (32) #define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH (8) #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN (0) +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK (3) #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL (2) #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA (0) #define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH (2) @@ -61,13 +92,17 @@ #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 (0) #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 (0x41041041) #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 (0x410410) -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 (0x80808080) -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 (0x80808080) -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 (0x8080) +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 \ +(0x01010101) +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 \ +(0x01010101) +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 \ +(0x0101) #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ (0) #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE (1) -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED (0) -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED (0) -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED (0) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED (0x0) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED (0x0) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED (0x0) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST (0x0) #endif /*#ifndef__SDRAM_CONFIG_H*/ -- cgit v1.2.3