From 25ab9fcaf862459650ae052e20527331d3ceefb9 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 30 Mar 2016 12:00:24 +0200 Subject: ARM: i.MX6: esdctl: Fix CS0_end for 4GiB/cs On i.MX6 a single chipselect can have 4GiB. In this case the calculation for CS0_end overflows the 7 bit field. Clamp it to 127, the maximum supported value. Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/imx6-mmdc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-imx/imx6-mmdc.c b/arch/arm/mach-imx/imx6-mmdc.c index 146df573e4..8f661e3dfe 100644 --- a/arch/arm/mach-imx/imx6-mmdc.c +++ b/arch/arm/mach-imx/imx6-mmdc.c @@ -1199,7 +1199,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, twtr = ROUND(max(4 * clkper, 7500) / clkper, 1) - 1; trcd = trp; trtp = twtr; - cs0_end = 4 * sysinfo->cs_density - 1 + 8; + cs0_end = min(4 * sysinfo->cs_density - 1 + 8, 127); debug("density:%d Gb (%d Gb per chip)\n", sysinfo->cs_density, ddr3_cfg->density); -- cgit v1.2.3