From 3375252d35eb74ad3e867809aac06ec1ab4446fa Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Fri, 20 Apr 2018 18:05:30 -0700 Subject: ARM: i.MX: Add infrastructure to record SoC reset reason Signed-off-by: Andrey Smirnov Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/imx.c | 33 +++++++++++++++++++++++++++ arch/arm/mach-imx/include/mach/reset-reason.h | 25 ++++++++++++++++++++ 2 files changed, 58 insertions(+) create mode 100644 arch/arm/mach-imx/include/mach/reset-reason.h (limited to 'arch') diff --git a/arch/arm/mach-imx/imx.c b/arch/arm/mach-imx/imx.c index 9400105c66..29dad9a412 100644 --- a/arch/arm/mach-imx/imx.c +++ b/arch/arm/mach-imx/imx.c @@ -14,8 +14,10 @@ #include #include #include +#include #include #include +#include static int __imx_silicon_revision = IMX_CHIP_REV_UNKNOWN; @@ -147,3 +149,34 @@ static int imx_init(void) return ret; } postcore_initcall(imx_init); + +void imx_set_reset_reason(void __iomem *srsr, + const struct imx_reset_reason *reasons) +{ + enum reset_src_type type = RESET_UKWN; + const u32 reg = readl(srsr); + int i, instance = 0; + + /* + * SRSR register captures ALL reset event that occured since + * POR, so we need to clear it to make sure we only caputre + * the latest one. + */ + writel(reg, srsr); + + for (i = 0; reasons[i].mask; i++) { + if (reg & reasons[i].mask) { + type = reasons[i].type; + instance = reasons[i].instance; + break; + } + } + + /* + * Report this with above default priority in order to make + * sure we'll always override info from watchdog driver. + */ + reset_source_set_priority(type, + RESET_SOURCE_DEFAULT_PRIORITY + 1); + reset_source_set_instance(type, instance); +} diff --git a/arch/arm/mach-imx/include/mach/reset-reason.h b/arch/arm/mach-imx/include/mach/reset-reason.h new file mode 100644 index 0000000000..39afc4b287 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/reset-reason.h @@ -0,0 +1,25 @@ +#ifndef __MACH_RESET_REASON_H__ +#define __MACH_RESET_REASON_H__ + +#include + +#define IMX_SRC_SRSR_IPP_RESET BIT(0) +#define IMX_SRC_SRSR_CSU_RESET BIT(1) +#define IMX_SRC_SRSR_IPP_USER_RESET BIT(3) +#define IMX_SRC_SRSR_WDOG1_RESET BIT(4) +#define IMX_SRC_SRSR_JTAG_RESET BIT(5) +#define IMX_SRC_SRSR_JTAG_SW_RESET BIT(6) +#define IMX_SRC_SRSR_WDOG3_RESET BIT(7) +#define IMX_SRC_SRSR_WDOG4_RESET BIT(8) +#define IMX_SRC_SRSR_TEMPSENSE_RESET BIT(9) +#define IMX_SRC_SRSR_WARM_BOOT BIT(16) + +struct imx_reset_reason { + uint32_t mask; + enum reset_src_type type; + int instance; +}; + +void imx_set_reset_reason(void __iomem *, const struct imx_reset_reason *); + +#endif /* __MACH_RESET_REASON_H__ */ -- cgit v1.2.3