From 3ccc8873c1dc10b63e75223622dfc6301d72df68 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 13 Feb 2020 15:16:24 +0100 Subject: ARM: i.MX8M: rename imx8-ccm-regs.h to imx8m-ccm-regs.h i.MX8 is something different than the i.MX8M and both will not share this header file, so rename it to imx8m-ccm-regs.h Signed-off-by: Sascha Hauer --- arch/arm/boards/nxp-imx8mq-evk/lowlevel.c | 2 +- arch/arm/boards/phytec-som-imx8mq/lowlevel.c | 2 +- arch/arm/boards/zii-imx8mq-dev/lowlevel.c | 2 +- arch/arm/mach-imx/include/mach/imx8-ccm-regs.h | 51 ------------------------- arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h | 51 +++++++++++++++++++++++++ 5 files changed, 54 insertions(+), 54 deletions(-) delete mode 100644 arch/arm/mach-imx/include/mach/imx8-ccm-regs.h create mode 100644 arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h (limited to 'arch') diff --git a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c index 0f4b27a9af..ac97023631 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c +++ b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c @@ -5,7 +5,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c index 0abe0a6bc2..08287a135f 100644 --- a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c +++ b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c index 0bb141fbf2..bc966589c3 100644 --- a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c +++ b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/include/mach/imx8-ccm-regs.h b/arch/arm/mach-imx/include/mach/imx8-ccm-regs.h deleted file mode 100644 index 66ace0f1c4..0000000000 --- a/arch/arm/mach-imx/include/mach/imx8-ccm-regs.h +++ /dev/null @@ -1,51 +0,0 @@ -#ifndef __MACH_IMX8_CCM_REGS_H__ -#define __MACH_IMX8_CCM_REGS_H__ - -#include - -#define IMX8M_CCM_CCGR_DDR1 5 -#define IMX8M_CCM_CCGR_I2C1 23 -#define IMX8M_CCM_CCGR_I2C2 24 -#define IMX8M_CCM_CCGR_I2C3 25 -#define IMX8M_CCM_CCGR_I2C4 26 -#define IMX8M_CCM_CCGR_SCTR 57 -#define IMX8M_CCM_CCGR_UART1 73 -#define IMX8M_CCM_CCGR_UART2 74 -#define IMX8M_CCM_CCGR_UART3 75 -#define IMX8M_CCM_CCGR_UART4 76 -#define IMX8M_CCM_CCGR_GIC 92 - -/* - * Taken from "Table 5-1. Clock Root Table" from i.MX8M Quad - * Applications Processor Reference Manual - */ -#define IMX8M_ARM_A53_CLK_ROOT 0 -#define IMX8M_DRAM_SEL_CFG 48 -#define IMX8M_DRAM_ALT_CLK_ROOT 64 -#define IMX8M_DRAM_APB_CLK_ROOT 65 -#define IMX8M_UART1_CLK_ROOT 94 -#define IMX8M_UART2_CLK_ROOT 95 -#define IMX8M_UART3_CLK_ROOT 96 -#define IMX8M_UART4_CLK_ROOT 97 -#define IMX8M_GIC_CLK_ROOT 100 -#define IMX8M_UART1_CLK_ROOT__25M_REF_CLK IMX8M_CCM_TARGET_ROOTn_MUX(0b000) - -/* 0 <= n <= 190 */ -#define IMX8M_CCM_CCGRn_SET(n) (0x4004 + 16 * (n)) -#define IMX8M_CCM_CCGRn_CLR(n) (0x4008 + 16 * (n)) - -/* 0 <= n <= 120 */ -#define IMX8M_CCM_TARGET_ROOTn(n) (0x8000 + 128 * (n)) - -#define IMX8M_CCM_TARGET_ROOTn_POST_DIV(n) ((n) & 0x0000003f) -#define IMX8M_CCM_TARGET_ROOTn_PRE_DIV(n) (((n) << 16) & 0x00070000) -#define IMX8M_CCM_TARGET_ROOTn_MUX(x) ((x) << 24) -#define IMX8M_CCM_TARGET_ROOTn_ENABLE BIT(28) - -#define IMX8M_CCM_CCGR_SETTINGn(n, s) ((s) << ((n) * 4)) -#define IMX8M_CCM_CCGR_SETTINGn_NOT_NEEDED(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b00) -#define IMX8M_CCM_CCGR_SETTINGn_NEEDED_RUN(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b01) -#define IMX8M_CCM_CCGR_SETTINGn_NEEDED_RUN_WAIT(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b10) -#define IMX8M_CCM_CCGR_SETTINGn_NEEDED(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b11) - -#endif diff --git a/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h b/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h new file mode 100644 index 0000000000..66ace0f1c4 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h @@ -0,0 +1,51 @@ +#ifndef __MACH_IMX8_CCM_REGS_H__ +#define __MACH_IMX8_CCM_REGS_H__ + +#include + +#define IMX8M_CCM_CCGR_DDR1 5 +#define IMX8M_CCM_CCGR_I2C1 23 +#define IMX8M_CCM_CCGR_I2C2 24 +#define IMX8M_CCM_CCGR_I2C3 25 +#define IMX8M_CCM_CCGR_I2C4 26 +#define IMX8M_CCM_CCGR_SCTR 57 +#define IMX8M_CCM_CCGR_UART1 73 +#define IMX8M_CCM_CCGR_UART2 74 +#define IMX8M_CCM_CCGR_UART3 75 +#define IMX8M_CCM_CCGR_UART4 76 +#define IMX8M_CCM_CCGR_GIC 92 + +/* + * Taken from "Table 5-1. Clock Root Table" from i.MX8M Quad + * Applications Processor Reference Manual + */ +#define IMX8M_ARM_A53_CLK_ROOT 0 +#define IMX8M_DRAM_SEL_CFG 48 +#define IMX8M_DRAM_ALT_CLK_ROOT 64 +#define IMX8M_DRAM_APB_CLK_ROOT 65 +#define IMX8M_UART1_CLK_ROOT 94 +#define IMX8M_UART2_CLK_ROOT 95 +#define IMX8M_UART3_CLK_ROOT 96 +#define IMX8M_UART4_CLK_ROOT 97 +#define IMX8M_GIC_CLK_ROOT 100 +#define IMX8M_UART1_CLK_ROOT__25M_REF_CLK IMX8M_CCM_TARGET_ROOTn_MUX(0b000) + +/* 0 <= n <= 190 */ +#define IMX8M_CCM_CCGRn_SET(n) (0x4004 + 16 * (n)) +#define IMX8M_CCM_CCGRn_CLR(n) (0x4008 + 16 * (n)) + +/* 0 <= n <= 120 */ +#define IMX8M_CCM_TARGET_ROOTn(n) (0x8000 + 128 * (n)) + +#define IMX8M_CCM_TARGET_ROOTn_POST_DIV(n) ((n) & 0x0000003f) +#define IMX8M_CCM_TARGET_ROOTn_PRE_DIV(n) (((n) << 16) & 0x00070000) +#define IMX8M_CCM_TARGET_ROOTn_MUX(x) ((x) << 24) +#define IMX8M_CCM_TARGET_ROOTn_ENABLE BIT(28) + +#define IMX8M_CCM_CCGR_SETTINGn(n, s) ((s) << ((n) * 4)) +#define IMX8M_CCM_CCGR_SETTINGn_NOT_NEEDED(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b00) +#define IMX8M_CCM_CCGR_SETTINGn_NEEDED_RUN(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b01) +#define IMX8M_CCM_CCGR_SETTINGn_NEEDED_RUN_WAIT(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b10) +#define IMX8M_CCM_CCGR_SETTINGn_NEEDED(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b11) + +#endif -- cgit v1.2.3