From 51140eec25a489d1259d24814af5aaa2c09f82b1 Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Fri, 1 Oct 2021 12:09:47 +0200 Subject: ddr: imx8m: ddrphy_train: add DDR4 support There are DDR3L, DDR4 and LPDDR4 variants of the i.MX8M* SoMs used with the NXP EVKs. So far, we only supported LPDDR4. For DDR4, we just need different PHY training code. Encode the DRAM variant information into a new dram_timing_info::dram_type and adjust the driver to make use of it. The new CONFIG_FIRMWARE_IMX_DDR4_PMU_TRAIN Kconfig symbol can co-exist with CONFIG_FIRMWARE_IMX_LPDDR4_PMU_TRAIN, allowing the same barebox binary to target different memory types, provided board code can determine what kind of DRAM is fitted. Signed-off-by: Ahmad Fatoum Link: https://lore.barebox.org/20211001100949.6891-7-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer --- arch/arm/boards/mnt-reform/lpddr4-timing.c | 1 + arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c | 1 + arch/arm/boards/nxp-imx8mp-evk/lpddr4-timing.c | 1 + arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c | 6 +++--- arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c | 6 +++--- arch/arm/boards/protonic-imx8m/lpddr4-timing-prt8mm.c | 1 + arch/arm/boards/zii-imx8mq-dev/ddrphy_train.c | 6 +++--- 7 files changed, 13 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/arm/boards/mnt-reform/lpddr4-timing.c b/arch/arm/boards/mnt-reform/lpddr4-timing.c index 0b5853000d..0e962890fd 100644 --- a/arch/arm/boards/mnt-reform/lpddr4-timing.c +++ b/arch/arm/boards/mnt-reform/lpddr4-timing.c @@ -1000,6 +1000,7 @@ static struct dram_fsp_msg mnt_reform_lpddr4_dram_fsp_msg[] = { /* ddr timing config params */ struct dram_timing_info mnt_reform_dram_timing = { + .dram_type = DRAM_TYPE_LPDDR4, .ddrc_cfg = mnt_reform_lpddr4_ddrc_cfg, .ddrc_cfg_num = ARRAY_SIZE(mnt_reform_lpddr4_ddrc_cfg), .ddrphy_cfg = mnt_reform_lpddr4_ddrphy_cfg, diff --git a/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c b/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c index e7c01f9cc9..68efbbdf91 100644 --- a/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c +++ b/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c @@ -1965,6 +1965,7 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { /* lpddr4 timing config params on EVK board */ struct dram_timing_info imx8mm_evk_dram_timing = { + .dram_type = DRAM_TYPE_LPDDR4, .ddrc_cfg = lpddr4_ddrc_cfg, .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg), .ddrphy_cfg = lpddr4_ddrphy_cfg, diff --git a/arch/arm/boards/nxp-imx8mp-evk/lpddr4-timing.c b/arch/arm/boards/nxp-imx8mp-evk/lpddr4-timing.c index 3028bc084c..681e70d060 100644 --- a/arch/arm/boards/nxp-imx8mp-evk/lpddr4-timing.c +++ b/arch/arm/boards/nxp-imx8mp-evk/lpddr4-timing.c @@ -1834,6 +1834,7 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = { /* ddr timing config params */ struct dram_timing_info imx8mp_evk_dram_timing = { + .dram_type = DRAM_TYPE_LPDDR4, .ddrc_cfg = ddr_ddrc_cfg, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), .ddrphy_cfg = ddr_ddrphy_cfg, diff --git a/arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c b/arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c index 1b30ff7257..d2c73fc7ce 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c +++ b/arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c @@ -142,7 +142,7 @@ void ddr_cfg_phy(void) { //enable APB bus to access DDRPHY RAM reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); //load the 1D training image - ddr_load_train_code(FW_1D_IMAGE); + ddr_load_train_code(DRAM_TYPE_LPDDR4, FW_1D_IMAGE); //configure DDRPHY-FW DMEM structure @clock0... reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); @@ -289,7 +289,7 @@ void ddr_cfg_phy(void) { //enable APB bus to access DDRPHY RAM reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); //load the 2D training image - ddr_load_train_code(FW_2D_IMAGE); + ddr_load_train_code(DRAM_TYPE_LPDDR4, FW_2D_IMAGE); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0xc80); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x11); @@ -932,4 +932,4 @@ void ddr_cfg_phy(void) { reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2006e, 0x0); //disable APB bus to access DDRPHY RAM reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); -} \ No newline at end of file +} diff --git a/arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c b/arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c index cc00527649..2c84a0f5fd 100644 --- a/arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c +++ b/arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c @@ -146,7 +146,7 @@ void ddr_cfg_phy(void) { //enable APB bus to access DDRPHY RAM reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); //load the 1D training image - ddr_load_train_code(FW_1D_IMAGE); + ddr_load_train_code(DRAM_TYPE_LPDDR4, FW_1D_IMAGE); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0xc80); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2); @@ -222,7 +222,7 @@ void ddr_cfg_phy(void) { //enable APB bus to access DDRPHY RAM reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); //load the 1D training image - ddr_load_train_code(FW_1D_IMAGE); + ddr_load_train_code(DRAM_TYPE_LPDDR4, FW_1D_IMAGE); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002,0x1); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0x29c); @@ -298,7 +298,7 @@ void ddr_cfg_phy(void) { //enable APB bus to access DDRPHY RAM reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); //load the 2D training image - ddr_load_train_code(FW_2D_IMAGE); + ddr_load_train_code(DRAM_TYPE_LPDDR4, FW_2D_IMAGE); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0xc80); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2); diff --git a/arch/arm/boards/protonic-imx8m/lpddr4-timing-prt8mm.c b/arch/arm/boards/protonic-imx8m/lpddr4-timing-prt8mm.c index 2c55e7d451..ea5c0b9154 100644 --- a/arch/arm/boards/protonic-imx8m/lpddr4-timing-prt8mm.c +++ b/arch/arm/boards/protonic-imx8m/lpddr4-timing-prt8mm.c @@ -1981,6 +1981,7 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { /* lpddr4 timing config params on EVK board */ struct dram_timing_info prt8mm_dram_timing = { + .dram_type = DRAM_TYPE_LPDDR4, .ddrc_cfg = lpddr4_ddrc_cfg, .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg), .ddrphy_cfg = lpddr4_ddrphy_cfg, diff --git a/arch/arm/boards/zii-imx8mq-dev/ddrphy_train.c b/arch/arm/boards/zii-imx8mq-dev/ddrphy_train.c index 1b30ff7257..d2c73fc7ce 100644 --- a/arch/arm/boards/zii-imx8mq-dev/ddrphy_train.c +++ b/arch/arm/boards/zii-imx8mq-dev/ddrphy_train.c @@ -142,7 +142,7 @@ void ddr_cfg_phy(void) { //enable APB bus to access DDRPHY RAM reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); //load the 1D training image - ddr_load_train_code(FW_1D_IMAGE); + ddr_load_train_code(DRAM_TYPE_LPDDR4, FW_1D_IMAGE); //configure DDRPHY-FW DMEM structure @clock0... reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); @@ -289,7 +289,7 @@ void ddr_cfg_phy(void) { //enable APB bus to access DDRPHY RAM reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); //load the 2D training image - ddr_load_train_code(FW_2D_IMAGE); + ddr_load_train_code(DRAM_TYPE_LPDDR4, FW_2D_IMAGE); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0xc80); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x11); @@ -932,4 +932,4 @@ void ddr_cfg_phy(void) { reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2006e, 0x0); //disable APB bus to access DDRPHY RAM reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); -} \ No newline at end of file +} -- cgit v1.2.3