From 5127d8013793828f9e50e1124e85b661fe19eee0 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Tue, 15 Mar 2016 20:33:49 -0700 Subject: i.MX6: Apply PL310 errata base on PL310's revision I.MX6Q Plus parts have r3p2 revision of PL310 so double linefill errata no longer applies for all of the i.MX6Q SoCs. Change the code to use PL310's revision inforation to determine if workaround needs to be applied. Signed-off-by: Andrey Smirnov Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/imx6.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c index db1530c1d0..0c7338d0b5 100644 --- a/arch/arm/mach-imx/imx6.c +++ b/arch/arm/mach-imx/imx6.c @@ -210,11 +210,15 @@ int imx6_devices_init(void) static int imx6_mmu_init(void) { void __iomem *l2x0_base = IOMEM(0x00a02000); - u32 val; + u32 val, cache_part, cache_rtl; if (!cpu_is_mx6()) return 0; + val = readl(l2x0_base + L2X0_CACHE_ID); + cache_part = val & L2X0_CACHE_ID_PART_MASK; + cache_rtl = val & L2X0_CACHE_ID_RTL_MASK; + /* configure the PREFETCH register */ val = readl(l2x0_base + L2X0_PREFETCH_CTRL); val |= L2X0_DOUBLE_LINEFILL_EN | @@ -230,7 +234,8 @@ static int imx6_mmu_init(void) * Workaround: The only workaround to this erratum is to disable the * double linefill feature. This is the default behavior. */ - if (cpu_is_mx6q()) + if (cache_part == L2X0_CACHE_ID_PART_L310 && + cache_rtl < L2X0_CACHE_ID_RTL_R3P2) val &= ~(L2X0_DOUBLE_LINEFILL_EN | L2X0_INCR_DOUBLE_LINEFILL_EN); -- cgit v1.2.3