From a29f0eb51f21d25ea2829366984f35711f8bca15 Mon Sep 17 00:00:00 2001 From: Renaud Barbier Date: Fri, 13 Aug 2021 09:16:48 +0100 Subject: ls1046ardb: enable IFC NAND. Set the NAND timings and enable the IFC NAND driver. Signed-off-by: Renaud Barbier Link: https://lore.barebox.org/1628842608-17031-4-git-send-email-renaud.barbier@abaco.com Signed-off-by: Sascha Hauer --- arch/arm/boards/ls1046ardb/board.c | 38 ++++++++++++++++++++++++++++++++++- arch/arm/configs/layerscape_defconfig | 11 ++++++++++ 2 files changed, 48 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boards/ls1046ardb/board.c b/arch/arm/boards/ls1046ardb/board.c index ef68e9c7f9..5e42209c8b 100644 --- a/arch/arm/boards/ls1046ardb/board.c +++ b/arch/arm/boards/ls1046ardb/board.c @@ -15,6 +15,8 @@ #include #include #include +#include +#include #define MAX_NUM_PORTS 16 struct nxid { @@ -147,6 +149,40 @@ static int rdb_mem_init(void) } mem_initcall(rdb_mem_init); +static int rdb_nand_init(void) +{ + struct device_node *np; + void __iomem *ifc; + + np = of_find_compatible_node(NULL, NULL, "fsl,ifc"); + if (!np) + return -EINVAL; + + ifc = of_iomap(np, 0); + if (!ifc) + return -EINVAL; + + set_ifc_cspr(ifc, IFC_CS0, CSPR_PHYS_ADDR(0x7e800000) | + CSPR_PORT_SIZE_8 | CSPR_MSEL_NAND | CSPR_V); + set_ifc_csor(ifc, IFC_CS0, CSOR_NAND_ECC_ENC_EN | CSOR_NAND_ECC_DEC_EN | + CSOR_NAND_ECC_MODE_8 | + CSOR_NAND_RAL_3 | CSOR_NAND_PGS_4K | + CSOR_NAND_SPRZ_224 | CSOR_NAND_PB(64) | + CSOR_NAND_TRHZ_20); + set_ifc_amask(ifc, IFC_CS0, IFC_AMASK(64*1024)); + set_ifc_ftim(ifc, IFC_CS0, IFC_FTIM0, FTIM0_NAND_TCCST(0x07) | + FTIM0_NAND_TWP(0x18) | FTIM0_NAND_TWCHT(0x07) | + FTIM0_NAND_TWH(0x0a)); + set_ifc_ftim(ifc, IFC_CS0, IFC_FTIM1, FTIM1_NAND_TADLE(0x32) | + FTIM1_NAND_TWBE(0x39) | FTIM1_NAND_TRR(0x0e)| + FTIM1_NAND_TRP(0x18)); + set_ifc_ftim(ifc, IFC_CS0, IFC_FTIM2, FTIM2_NAND_TRAD(0xf) | + FTIM2_NAND_TREH(0xa) | FTIM2_NAND_TWHRE(0x1e)); + set_ifc_ftim(ifc, IFC_CS0, IFC_FTIM3, 0); + + return 0; +} + static int rdb_postcore_init(void) { if (!of_machine_is_compatible("fsl,ls1046a-rdb")) @@ -157,7 +193,7 @@ static int rdb_postcore_init(void) ls1046a_bbu_mmc_register_handler("sd", "/dev/mmc0.barebox", BBU_HANDLER_FLAG_DEFAULT); - return 0; + return rdb_nand_init(); } postcore_initcall(rdb_postcore_init); diff --git a/arch/arm/configs/layerscape_defconfig b/arch/arm/configs/layerscape_defconfig index 394cd95c98..fb8e885353 100644 --- a/arch/arm/configs/layerscape_defconfig +++ b/arch/arm/configs/layerscape_defconfig @@ -34,6 +34,10 @@ CONFIG_CMD_GO=y CONFIG_CMD_RESET=y CONFIG_CMD_UIMAGE=y CONFIG_CMD_PARTITION=y +CONFIG_CMD_MOUNT=y +CONFIG_CMD_UBI=y +CONFIG_CMD_UBIFORMAT=y +CONFIG_CMD_UMOUNT=y CONFIG_CMD_EXPORT=y CONFIG_CMD_LOADENV=y CONFIG_CMD_PRINTENV=y @@ -69,6 +73,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_LED=y CONFIG_CMD_SPI=y +CONFIG_CMD_NAND=y CONFIG_CMD_LED_TRIGGER=y CONFIG_CMD_WD=y CONFIG_CMD_BAREBOX_UPDATE=y @@ -85,6 +90,10 @@ CONFIG_DP83867_PHY=y CONFIG_REALTEK_PHY=y CONFIG_NET_DSA_MV88E6XXX=y CONFIG_DRIVER_SPI_FSL_QUADSPI=y +CONFIG_NAND=y +CONFIG_NAND_FSL_IFC=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 CONFIG_I2C=y CONFIG_I2C_IMX=y CONFIG_I2C_MUX=y @@ -112,5 +121,7 @@ CONFIG_FS_NFS=y CONFIG_FS_FAT=y CONFIG_FS_FAT_WRITE=y CONFIG_FS_FAT_LFN=y +CONFIG_FS_UBIFS=y +CONFIG_FS_UBIFS_COMPRESSION_LZO=y CONFIG_ZLIB=y CONFIG_LZO_DECOMPRESS=y -- cgit v1.2.3