From 8974b63acff909ca10c0a21d3e3dbe463cbfb191 Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Mon, 30 Mar 2020 16:39:08 +0200 Subject: ARM: stm32mp: init: don't cast signed error to unsigned bsec_read_field returns a negative value on error, pass it along signed. This doesn't matter now, because we ignore the error code, but it's the correct thing to do. Signed-off-by: Ahmad Fatoum Signed-off-by: Sascha Hauer --- arch/arm/mach-stm32mp/init.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-stm32mp/init.c b/arch/arm/mach-stm32mp/init.c index 7bad989a60..6280d94da6 100644 --- a/arch/arm/mach-stm32mp/init.c +++ b/arch/arm/mach-stm32mp/init.c @@ -155,7 +155,7 @@ static inline u32 read_idc(void) } /* Get Device Part Number (RPN) from OTP */ -static u32 get_cpu_rpn(u32 *rpn) +static int get_cpu_rpn(u32 *rpn) { int ret = bsec_read_field(BSEC_OTP_RPN, rpn); if (ret) @@ -170,7 +170,7 @@ static u32 get_cpu_revision(void) return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT; } -static u32 get_cpu_type(u32 *type) +static int get_cpu_type(u32 *type) { u32 id; int ret = get_cpu_rpn(type); -- cgit v1.2.3 From 2e45f03730101082633bd50d3d14ac0eac776de8 Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Mon, 30 Mar 2020 16:39:09 +0200 Subject: ARM: stm32mp: init: detect Revision Z and 800 MHz profiles Revision A was 0x1000 and B was 0x2000, so I assumed the next would be revision C valued 0x3000. Alas, it's revision Z with 0x2001... Change the code accordingly and add detection for the new 800Mhz profiles. Code taken from U-Boot commit cf0818b477 ("stm32mp1: support of STM32MP15x Rev.Z") and Patch[1] "stm32mp1: add 800 MHz profile support". [1]: https://st-md-mailman.stormreply.com/pipermail/uboot-stm32/2020-February/002170.html Signed-off-by: Ahmad Fatoum Signed-off-by: Sascha Hauer --- arch/arm/mach-stm32mp/include/mach/revision.h | 18 +++++++++++- arch/arm/mach-stm32mp/init.c | 41 +++++++++++++++++++++++---- 2 files changed, 53 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-stm32mp/include/mach/revision.h b/arch/arm/mach-stm32mp/include/mach/revision.h index 387201421d..2eb4d44b33 100644 --- a/arch/arm/mach-stm32mp/include/mach/revision.h +++ b/arch/arm/mach-stm32mp/include/mach/revision.h @@ -6,17 +6,33 @@ #ifndef __MACH_CPUTYPE_H__ #define __MACH_CPUTYPE_H__ -/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit15:0)*/ + +/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit7:0) + * 157X: 2x Cortex-A7, Cortex-M4, CAN FD, GPU, DSI + * 153X: 2x Cortex-A7, Cortex-M4, CAN FD + * 151X: 1x Cortex-A7, Cortex-M4 + * XXXA: Cortex-A7 @ 650 MHz + * XXXC: Cortex-A7 @ 650 MHz + Secure Boot + HW Crypto + * XXXD: Cortex-A7 @ 800 MHz + * XXXF: Cortex-A7 @ 800 MHz + Secure Boot + HW Crypto + */ #define CPU_STM32MP157Cxx 0x05000000 #define CPU_STM32MP157Axx 0x05000001 #define CPU_STM32MP153Cxx 0x05000024 #define CPU_STM32MP153Axx 0x05000025 #define CPU_STM32MP151Cxx 0x0500002E #define CPU_STM32MP151Axx 0x0500002F +#define CPU_STM32MP157Fxx 0x05000080 +#define CPU_STM32MP157Dxx 0x05000081 +#define CPU_STM32MP153Fxx 0x050000A4 +#define CPU_STM32MP153Dxx 0x050000A5 +#define CPU_STM32MP151Fxx 0x050000AE +#define CPU_STM32MP151Dxx 0x050000AF /* silicon revisions */ #define CPU_REV_A 0x1000 #define CPU_REV_B 0x2000 +#define CPU_REV_Z 0x2001 int stm32mp_silicon_revision(void); int stm32mp_cputype(void); diff --git a/arch/arm/mach-stm32mp/init.c b/arch/arm/mach-stm32mp/init.c index 6280d94da6..8a50657664 100644 --- a/arch/arm/mach-stm32mp/init.c +++ b/arch/arm/mach-stm32mp/init.c @@ -194,17 +194,29 @@ static int get_cpu_package(u32 *pkg) static int setup_cpu_type(void) { - const char *cputypestr; - const char *cpupkgstr; + const char *cputypestr, *cpupkgstr, *cpurevstr; + u32 pkg; get_cpu_type(&__stm32mp_cputype); switch (__stm32mp_cputype) { + case CPU_STM32MP157Fxx: + cputypestr = "157F"; + break; + case CPU_STM32MP157Dxx: + cputypestr = "157D"; + break; case CPU_STM32MP157Cxx: cputypestr = "157C"; break; case CPU_STM32MP157Axx: cputypestr = "157A"; break; + case CPU_STM32MP153Fxx: + cputypestr = "153F"; + break; + case CPU_STM32MP153Dxx: + cputypestr = "153D"; + break; case CPU_STM32MP153Cxx: cputypestr = "153C"; break; @@ -217,6 +229,12 @@ static int setup_cpu_type(void) case CPU_STM32MP151Axx: cputypestr = "151A"; break; + case CPU_STM32MP151Fxx: + cputypestr = "151F"; + break; + case CPU_STM32MP151Dxx: + cputypestr = "151D"; + break; default: cputypestr = "????"; break; @@ -242,11 +260,24 @@ static int setup_cpu_type(void) } __stm32mp_silicon_revision = get_cpu_revision(); + switch (__stm32mp_silicon_revision) { + case CPU_REV_A: + cpurevstr = "A"; + break; + case CPU_REV_B: + cpurevstr = "B"; + break; + case CPU_REV_Z: + cpurevstr = "Z"; + break; + default: + cpurevstr = "?"; + } pr_debug("cputype = 0x%x, package = 0x%x, revision = 0x%x\n", - __stm32mp_cputype, __stm32mp_package, __stm32mp_silicon_revision); - pr_info("detected STM32MP%s%s Rev.%c\n", cputypestr, cpupkgstr, - (__stm32mp_silicon_revision >> 12) + 'A' - 1); + __stm32mp_cputype, pkg, __stm32mp_silicon_revision); + pr_info("detected STM32MP%s%s Rev.%s\n", cputypestr, cpupkgstr, cpurevstr); + return 0; } -- cgit v1.2.3 From 01daf3c9dcf0e22af335cc5b39a6a72a5f941c8d Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Mon, 30 Mar 2020 16:39:10 +0200 Subject: ARM: stm32mp: init: fix up CPU device tree nodes To facilitate using the same barebox binary for multiple variants of the STM32MP15x, have it fix up the CPU device tree nodes. Signed-off-by: Ahmad Fatoum Signed-off-by: Sascha Hauer --- arch/arm/mach-stm32mp/init.c | 45 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-stm32mp/init.c b/arch/arm/mach-stm32mp/init.c index 8a50657664..d687e44af1 100644 --- a/arch/arm/mach-stm32mp/init.c +++ b/arch/arm/mach-stm32mp/init.c @@ -75,6 +75,9 @@ #define TAMP_BOOT_FORCED_MASK GENMASK(7, 0) #define TAMP_BOOT_DEBUG_ON BIT(16) +#define FIXUP_CPU_MASK(num, mhz) (((num) << 16) | (mhz)) +#define FIXUP_CPU_NUM(mask) ((mask) >> 16) +#define FIXUP_CPU_HZ(mask) (((mask) & GENMASK(15, 0)) * 1000UL * 1000UL) static enum stm32mp_forced_boot_mode __stm32mp_forced_boot_mode; enum stm32mp_forced_boot_mode st32mp_get_forced_boot_mode(void) @@ -192,48 +195,87 @@ static int get_cpu_package(u32 *pkg) return 0; } +static int stm32mp15_fixup_cpus(struct device_node *root, void *_ctx) +{ + unsigned long ctx = (unsigned long)_ctx; + struct device_node *cpus_node, *np, *tmp; + + cpus_node = of_find_node_by_name(root, "cpus"); + if (!cpus_node) + return 0; + + for_each_child_of_node_safe(cpus_node, tmp, np) { + u32 cpu_index; + + if (of_property_read_u32(np, "reg", &cpu_index)) + continue; + + if (cpu_index >= FIXUP_CPU_NUM(ctx)) { + of_delete_node(np); + continue; + } + + of_property_write_u32(np, "clock-frequency", FIXUP_CPU_HZ(ctx)); + } + + return 0; +} + static int setup_cpu_type(void) { const char *cputypestr, *cpupkgstr, *cpurevstr; + unsigned long fixupctx = 0; u32 pkg; get_cpu_type(&__stm32mp_cputype); switch (__stm32mp_cputype) { case CPU_STM32MP157Fxx: cputypestr = "157F"; + fixupctx = FIXUP_CPU_MASK(2, 800); break; case CPU_STM32MP157Dxx: cputypestr = "157D"; + fixupctx = FIXUP_CPU_MASK(2, 800); break; case CPU_STM32MP157Cxx: cputypestr = "157C"; + fixupctx = FIXUP_CPU_MASK(2, 650); break; case CPU_STM32MP157Axx: cputypestr = "157A"; + fixupctx = FIXUP_CPU_MASK(2, 650); break; case CPU_STM32MP153Fxx: cputypestr = "153F"; + fixupctx = FIXUP_CPU_MASK(2, 800); break; case CPU_STM32MP153Dxx: cputypestr = "153D"; + fixupctx = FIXUP_CPU_MASK(2, 800); break; case CPU_STM32MP153Cxx: cputypestr = "153C"; + fixupctx = FIXUP_CPU_MASK(2, 650); break; case CPU_STM32MP153Axx: cputypestr = "153A"; + fixupctx = FIXUP_CPU_MASK(2, 650); break; case CPU_STM32MP151Cxx: cputypestr = "151C"; + fixupctx = FIXUP_CPU_MASK(1, 650); break; case CPU_STM32MP151Axx: cputypestr = "151A"; + fixupctx = FIXUP_CPU_MASK(1, 650); break; case CPU_STM32MP151Fxx: cputypestr = "151F"; + fixupctx = FIXUP_CPU_MASK(1, 800); break; case CPU_STM32MP151Dxx: cputypestr = "151D"; + fixupctx = FIXUP_CPU_MASK(1, 800); break; default: cputypestr = "????"; @@ -278,6 +320,9 @@ static int setup_cpu_type(void) __stm32mp_cputype, pkg, __stm32mp_silicon_revision); pr_info("detected STM32MP%s%s Rev.%s\n", cputypestr, cpupkgstr, cpurevstr); + if (fixupctx) + return of_register_fixup(stm32mp15_fixup_cpus, (void*)fixupctx); + return 0; } -- cgit v1.2.3 From f3121d6fc82cd5097f7d8cc7a5935d7b0acc310a Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Mon, 30 Mar 2020 16:39:12 +0200 Subject: nvmem: bsec: remove wrongly named bsec_field type BSEC_SMC_READ_SHADOW and BSEC_SMC_WRITE_SHADOW aren't fields, but operations to apply on fields. Rename it accordingly and fix up instances where it was used wrongly. Signed-off-by: Ahmad Fatoum Signed-off-by: Sascha Hauer --- arch/arm/mach-stm32mp/include/mach/bsec.h | 6 +++--- drivers/nvmem/bsec.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-stm32mp/include/mach/bsec.h b/arch/arm/mach-stm32mp/include/mach/bsec.h index 559faaa2ba..d3cb91b1fd 100644 --- a/arch/arm/mach-stm32mp/include/mach/bsec.h +++ b/arch/arm/mach-stm32mp/include/mach/bsec.h @@ -17,7 +17,7 @@ enum bsec_smc { }; /* Service for BSEC */ -enum bsec_field { +enum bsec_op { BSEC_SMC_READ_SHADOW = 1, BSEC_SMC_PROG_OTP = 2, BSEC_SMC_WRITE_SHADOW = 3, @@ -26,13 +26,13 @@ enum bsec_field { BSEC_SMC_WRITE_ALL = 6, }; -static inline enum bsec_smc bsec_read_field(enum bsec_field field, unsigned *val) +static inline enum bsec_smc bsec_read_field(unsigned field, unsigned *val) { return stm32mp_smc(STM32_SMC_BSEC, BSEC_SMC_READ_SHADOW, field, 0, val); } -static inline enum bsec_smc bsec_write_field(enum bsec_field field, unsigned val) +static inline enum bsec_smc bsec_write_field(unsigned field, unsigned val) { return stm32mp_smc(STM32_SMC_BSEC, BSEC_SMC_WRITE_SHADOW, field, val, NULL); diff --git a/drivers/nvmem/bsec.c b/drivers/nvmem/bsec.c index 209c50dc70..836e62ecbc 100644 --- a/drivers/nvmem/bsec.c +++ b/drivers/nvmem/bsec.c @@ -33,7 +33,7 @@ struct stm32_bsec_data { int num_regs; }; -static int bsec_smc(struct bsec_priv *priv, u8 op, enum bsec_field field, +static int bsec_smc(struct bsec_priv *priv, enum bsec_op op, u32 field, unsigned data2, unsigned *val) { enum bsec_smc ret = stm32mp_smc(priv->svc_id, op, field / 4, data2, val); -- cgit v1.2.3 From fc3df9414a57db628abb0f5145e35da9199f9b61 Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Mon, 11 May 2020 09:41:49 +0200 Subject: stm32mp: init: fix up st, package into stm32mp pinctrl nodes Since Linux v5.1, the pinctrl driver can use the st,package property if provided to validate whether the ball to be configured exists on the package. The upstream device trees provide this property, but if we'll want barebox to supply it instead, so we can use the same barebox binary for different SoC variants. Signed-off-by: Ahmad Fatoum Signed-off-by: Sascha Hauer --- arch/arm/mach-stm32mp/init.c | 63 +++++++++++++++++++++++++++++++++----------- 1 file changed, 48 insertions(+), 15 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-stm32mp/init.c b/arch/arm/mach-stm32mp/init.c index d687e44af1..7f687fa4f2 100644 --- a/arch/arm/mach-stm32mp/init.c +++ b/arch/arm/mach-stm32mp/init.c @@ -13,6 +13,7 @@ #include #include #include +#include /* DBGMCU register */ #define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00) @@ -221,61 +222,83 @@ static int stm32mp15_fixup_cpus(struct device_node *root, void *_ctx) return 0; } +static int fixup_pinctrl(struct device_node *root, const char *compat, u32 pkg) +{ + struct device_node *np = of_find_compatible_node(root, NULL, compat); + if (!np) + return -ENODEV; + + return of_property_write_u32(np, "st,package", pkg); +} + +static int stm32mp15_fixup_pkg(struct device_node *root, void *_pkg) +{ + unsigned long pkg = (unsigned long)_pkg; + int ret; + + ret = fixup_pinctrl(root, "st,stm32mp157-pinctrl", pkg); + if (ret) + return ret; + + return fixup_pinctrl(root, "st,stm32mp157-z-pinctrl", pkg); +} + static int setup_cpu_type(void) { const char *cputypestr, *cpupkgstr, *cpurevstr; - unsigned long fixupctx = 0; + unsigned long cpufixupctx = 0, pkgfixupctx = 0; u32 pkg; + int ret; get_cpu_type(&__stm32mp_cputype); switch (__stm32mp_cputype) { case CPU_STM32MP157Fxx: cputypestr = "157F"; - fixupctx = FIXUP_CPU_MASK(2, 800); + cpufixupctx = FIXUP_CPU_MASK(2, 800); break; case CPU_STM32MP157Dxx: cputypestr = "157D"; - fixupctx = FIXUP_CPU_MASK(2, 800); + cpufixupctx = FIXUP_CPU_MASK(2, 800); break; case CPU_STM32MP157Cxx: cputypestr = "157C"; - fixupctx = FIXUP_CPU_MASK(2, 650); + cpufixupctx = FIXUP_CPU_MASK(2, 650); break; case CPU_STM32MP157Axx: cputypestr = "157A"; - fixupctx = FIXUP_CPU_MASK(2, 650); + cpufixupctx = FIXUP_CPU_MASK(2, 650); break; case CPU_STM32MP153Fxx: cputypestr = "153F"; - fixupctx = FIXUP_CPU_MASK(2, 800); + cpufixupctx = FIXUP_CPU_MASK(2, 800); break; case CPU_STM32MP153Dxx: cputypestr = "153D"; - fixupctx = FIXUP_CPU_MASK(2, 800); + cpufixupctx = FIXUP_CPU_MASK(2, 800); break; case CPU_STM32MP153Cxx: cputypestr = "153C"; - fixupctx = FIXUP_CPU_MASK(2, 650); + cpufixupctx = FIXUP_CPU_MASK(2, 650); break; case CPU_STM32MP153Axx: cputypestr = "153A"; - fixupctx = FIXUP_CPU_MASK(2, 650); + cpufixupctx = FIXUP_CPU_MASK(2, 650); break; case CPU_STM32MP151Cxx: cputypestr = "151C"; - fixupctx = FIXUP_CPU_MASK(1, 650); + cpufixupctx = FIXUP_CPU_MASK(1, 650); break; case CPU_STM32MP151Axx: cputypestr = "151A"; - fixupctx = FIXUP_CPU_MASK(1, 650); + cpufixupctx = FIXUP_CPU_MASK(1, 650); break; case CPU_STM32MP151Fxx: cputypestr = "151F"; - fixupctx = FIXUP_CPU_MASK(1, 800); + cpufixupctx = FIXUP_CPU_MASK(1, 800); break; case CPU_STM32MP151Dxx: cputypestr = "151D"; - fixupctx = FIXUP_CPU_MASK(1, 800); + cpufixupctx = FIXUP_CPU_MASK(1, 800); break; default: cputypestr = "????"; @@ -286,15 +309,19 @@ static int setup_cpu_type(void) switch (__stm32mp_package) { case PKG_AA_LBGA448: cpupkgstr = "AA"; + pkgfixupctx = STM32MP_PKG_AA; break; case PKG_AB_LBGA354: cpupkgstr = "AB"; + pkgfixupctx = STM32MP_PKG_AB; break; case PKG_AC_TFBGA361: cpupkgstr = "AC"; + pkgfixupctx = STM32MP_PKG_AC; break; case PKG_AD_TFBGA257: cpupkgstr = "AD"; + pkgfixupctx = STM32MP_PKG_AD; break; default: cpupkgstr = "??"; @@ -320,8 +347,14 @@ static int setup_cpu_type(void) __stm32mp_cputype, pkg, __stm32mp_silicon_revision); pr_info("detected STM32MP%s%s Rev.%s\n", cputypestr, cpupkgstr, cpurevstr); - if (fixupctx) - return of_register_fixup(stm32mp15_fixup_cpus, (void*)fixupctx); + if (cpufixupctx) { + ret = of_register_fixup(stm32mp15_fixup_cpus, (void*)cpufixupctx); + if (ret) + return ret; + } + + if (pkgfixupctx) + return of_register_fixup(stm32mp15_fixup_pkg, (void*)pkgfixupctx); return 0; } -- cgit v1.2.3