From fee27d41640f4732f7df1648ba8c44b0f91153e3 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Sat, 9 Nov 2019 15:28:29 +0100 Subject: clk: zynq: use base address of clock controller The clock controller is a subregion of the SLCR, use the real base of this region for mapping the registers. This will allow to switch to DT based probing later. Signed-off-by: Lucas Stach Signed-off-by: Sascha Hauer --- arch/arm/mach-zynq/zynq.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-zynq/zynq.c b/arch/arm/mach-zynq/zynq.c index f6112fd249..ec22b16c91 100644 --- a/arch/arm/mach-zynq/zynq.c +++ b/arch/arm/mach-zynq/zynq.c @@ -48,7 +48,8 @@ static int zynq_init(void) writel(val, 0xf8f00000); dmb(); - add_generic_device("zynq-clock", 0, NULL, ZYNQ_SLCR_BASE, 0x4000, IORESOURCE_MEM, NULL); + add_generic_device("zynq-clock", 0, NULL, ZYNQ_SLCR_BASE + 0x100, + 0x4000, IORESOURCE_MEM, NULL); add_generic_device("smp_twd", 0, NULL, CORTEXA9_SCU_TIMER_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL); restart_handler_register_fn(zynq_restart_soc); -- cgit v1.2.3