From f2fdfe875fee5b94feab7f2e79e3de8875b3eb3f Mon Sep 17 00:00:00 2001 From: Eric Benard Date: Thu, 10 Jun 2010 09:43:02 +0200 Subject: Add support for Eukrea CPUIMX35 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit this modules is based on Freescale's i.MX357 CPU, with 128MB of mDDR, 256 MB NAND, and ethernet PHY. Signed-off-by: Eric Bénard Signed-off-by: Sascha Hauer --- board/eukrea_cpuimx35/Makefile | 25 ++ board/eukrea_cpuimx35/config.h | 23 ++ board/eukrea_cpuimx35/env/bin/_update | 36 +++ board/eukrea_cpuimx35/env/bin/boot | 52 +++++ board/eukrea_cpuimx35/env/bin/hush_hack | 1 + board/eukrea_cpuimx35/env/bin/init | 41 ++++ board/eukrea_cpuimx35/env/bin/update_kernel | 8 + board/eukrea_cpuimx35/env/bin/update_root | 8 + board/eukrea_cpuimx35/env/config | 27 +++ board/eukrea_cpuimx35/eukrea_cpuimx35.c | 343 ++++++++++++++++++++++++++++ board/eukrea_cpuimx35/eukrea_cpuimx35.dox | 4 + board/eukrea_cpuimx35/flash_header.c | 60 +++++ board/eukrea_cpuimx35/lowlevel.c | 218 ++++++++++++++++++ 13 files changed, 846 insertions(+) create mode 100644 board/eukrea_cpuimx35/Makefile create mode 100644 board/eukrea_cpuimx35/config.h create mode 100644 board/eukrea_cpuimx35/env/bin/_update create mode 100644 board/eukrea_cpuimx35/env/bin/boot create mode 100644 board/eukrea_cpuimx35/env/bin/hush_hack create mode 100644 board/eukrea_cpuimx35/env/bin/init create mode 100644 board/eukrea_cpuimx35/env/bin/update_kernel create mode 100644 board/eukrea_cpuimx35/env/bin/update_root create mode 100644 board/eukrea_cpuimx35/env/config create mode 100644 board/eukrea_cpuimx35/eukrea_cpuimx35.c create mode 100644 board/eukrea_cpuimx35/eukrea_cpuimx35.dox create mode 100644 board/eukrea_cpuimx35/flash_header.c create mode 100644 board/eukrea_cpuimx35/lowlevel.c (limited to 'board') diff --git a/board/eukrea_cpuimx35/Makefile b/board/eukrea_cpuimx35/Makefile new file mode 100644 index 0000000000..32ffe42cb1 --- /dev/null +++ b/board/eukrea_cpuimx35/Makefile @@ -0,0 +1,25 @@ +# +# (C) Copyright 2007 Juergen Beisert +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +obj-y += lowlevel.o +obj-y += eukrea_cpuimx35.o +obj-$(CONFIG_ARCH_IMX_INTERNAL_BOOT) += flash_header.o diff --git a/board/eukrea_cpuimx35/config.h b/board/eukrea_cpuimx35/config.h new file mode 100644 index 0000000000..bfd3b3964e --- /dev/null +++ b/board/eukrea_cpuimx35/config.h @@ -0,0 +1,23 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MX35_HCLK_FREQ 24000000 + +#endif /* __CONFIG_H */ diff --git a/board/eukrea_cpuimx35/env/bin/_update b/board/eukrea_cpuimx35/env/bin/_update new file mode 100644 index 0000000000..014bce3512 --- /dev/null +++ b/board/eukrea_cpuimx35/env/bin/_update @@ -0,0 +1,36 @@ +#!/bin/sh + +if [ -z "$part" -o -z "$image" ]; then + echo "define \$part and \$image" + exit 1 +fi + +if [ ! -e "$part" ]; then + echo "Partition $part does not exist" + exit 1 +fi + +if [ $# = 1 ]; then + image=$1 +fi + +if [ x$ip = xdhcp ]; then + dhcp +fi + +ping $eth0.serverip +if [ $? -ne 0 ] ; then + echo "update aborted" + exit 1 +fi + +unprotect $part + +echo +echo "erasing partition $part" +erase $part + +echo +echo "flashing $image to $part" +echo +tftp $image $part diff --git a/board/eukrea_cpuimx35/env/bin/boot b/board/eukrea_cpuimx35/env/bin/boot new file mode 100644 index 0000000000..fca5b8cc19 --- /dev/null +++ b/board/eukrea_cpuimx35/env/bin/boot @@ -0,0 +1,52 @@ +#!/bin/sh + +. /env/config + +if [ x$1 = xjffS2 ]; then + root=jffs2 + kernel=nand +fi + +if [ x$1 = xubifs ]; then + root=ubifs + kernel=nand +fi + +if [ x$1 = xnet ]; then + root=net + kernel=net +fi + +if [ x$ip = xdhcp ]; then + bootargs="$bootargs ip=dhcp" +else + if [ x$ip = xoff ]; then + bootargs="$bootargs ip=off" + else + bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" + fi +fi + +if [ x$root = xjffs2 ]; then + bootargs="$bootargs root=/dev/mtdblock$rootpartnum_nand rootfstype=jffs2" +fi + +if [ x$root = xubifs ]; then + bootargs="$bootargs root=ubi0:$ubiroot ubi.mtd=$rootpartnum_nand rootfstype=ubifs" +fi + +if [ x$root = xnet ]; then + bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp" +fi + +bootargs="$bootargs mtdparts=mxc_nand:$nand_parts" + +if [ $kernel = net ]; then + if [ x$ip = xdhcp ]; then + dhcp + fi + tftp $uimage uImage || exit 1 + bootm uImage +else + bootm /dev/nand0.kernel.bb +fi diff --git a/board/eukrea_cpuimx35/env/bin/hush_hack b/board/eukrea_cpuimx35/env/bin/hush_hack new file mode 100644 index 0000000000..5fffa92ecd --- /dev/null +++ b/board/eukrea_cpuimx35/env/bin/hush_hack @@ -0,0 +1 @@ +nand -a /dev/nand0.* diff --git a/board/eukrea_cpuimx35/env/bin/init b/board/eukrea_cpuimx35/env/bin/init new file mode 100644 index 0000000000..49e54c5fdd --- /dev/null +++ b/board/eukrea_cpuimx35/env/bin/init @@ -0,0 +1,41 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config +if [ -e /dev/nand0 ]; then + addpart /dev/nand0 $nand_parts + + # Uh, oh, hush first expands wildcards and then starts executing + # commands. What a bug! + source /env/bin/hush_hack +fi + +if [ -f /env/logo.bmp ]; then + bmp /env/logo.bmp +elif [ -f /env/logo.bmp.lzo ]; then + unlzo /env/logo.bmp.lzo /logo.bmp + bmp /logo.bmp +fi + +if [ -z $eth0.ethaddr ]; then + while [ -z $eth0.ethaddr ]; do + readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr + done + echo -a /env/config "eth0.ethaddr=$eth0.ethaddr" + saveenv +fi + +echo +echo -n "Hit any key to stop autoboot: " +timeout -a $autoboot_timeout +if [ $? != 0 ]; then + echo + echo "type update_kernel [] to update kernel into flash" + echo "type update_root [] to update rootfs into flash" + echo + exit +fi + +boot diff --git a/board/eukrea_cpuimx35/env/bin/update_kernel b/board/eukrea_cpuimx35/env/bin/update_kernel new file mode 100644 index 0000000000..c2d2cc3fa9 --- /dev/null +++ b/board/eukrea_cpuimx35/env/bin/update_kernel @@ -0,0 +1,8 @@ +#!/bin/sh + +. /env/config + +image=$uimage +part=/dev/nand0.kernel.bb + +. /env/bin/_update $1 diff --git a/board/eukrea_cpuimx35/env/bin/update_root b/board/eukrea_cpuimx35/env/bin/update_root new file mode 100644 index 0000000000..dd89a5afad --- /dev/null +++ b/board/eukrea_cpuimx35/env/bin/update_root @@ -0,0 +1,8 @@ +#!/bin/sh + +. /env/config + +image=$rootfs +part=/dev/nand0.root.bb + +. /env/bin/_update $1 diff --git a/board/eukrea_cpuimx35/env/config b/board/eukrea_cpuimx35/env/config new file mode 100644 index 0000000000..df2079fa58 --- /dev/null +++ b/board/eukrea_cpuimx35/env/config @@ -0,0 +1,27 @@ +#!/bin/sh + +# can be either 'net' or 'nand'' +kernel=nand +root=ubifs + +basedir=cpuimx35 +uimage=$basedir/uImage +rootfs=$basedir/rootfs + +autoboot_timeout=1 + +nfsroot="" +bootargs="console=ttymxc0,115200" + +nand_parts="256k(barebox)ro,128k(bareboxenv),2176k(kernel),-(root)" +rootpartnum_nand=3 +ubiroot="eukrea-cpuimx35-rootfs" + +# use 'dhcp' to do dhcp in barebox and in kernel +ip=off + +# or set your networking parameters here +#eth0.ipaddr=a.b.c.d +#eth0.netmask=a.b.c.d +#eth0.gateway=a.b.c.d +#eth0.serverip=a.b.c.d diff --git a/board/eukrea_cpuimx35/eukrea_cpuimx35.c b/board/eukrea_cpuimx35/eukrea_cpuimx35.c new file mode 100644 index 0000000000..7f1c782f1e --- /dev/null +++ b/board/eukrea_cpuimx35/eukrea_cpuimx35.c @@ -0,0 +1,343 @@ +/* + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * 2009 Marc Kleine-Budde, Pengutronix + * (c) 2010 Eukrea Electromatique, Eric Bénard + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Derived from: + * + * * mx35_3stack.c - board file for uboot-v1 + * Copyright (C) 2007, Guennadi Liakhovetski + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +static struct fec_platform_data fec_info = { + .xcv_type = MII100, + .phy_addr = 0x1F, +}; + +static struct device_d fec_dev = { + .name = "fec_imx", + .map_base = IMX_FEC_BASE, + .platform_data = &fec_info, +}; + +static struct memory_platform_data sdram_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +}; + +static struct device_d sdram_dev = { + .name = "mem", + .map_base = IMX_SDRAM_CS0, + .size = 128 * 1024 * 1024, + .platform_data = &sdram_pdata, +}; + +struct imx_nand_platform_data nand_info = { + .width = 1, + .hw_ecc = 1, + .flash_bbt = 1, +}; + +static struct device_d nand_dev = { + .name = "imx_nand", + .map_base = IMX_NFC_BASE, + .platform_data = &nand_info, +}; + +static struct fb_videomode imxfb_mode = { + .name = "CMO_QVGA", + .refresh = 60, + .xres = 320, + .yres = 240, + .pixclock = KHZ2PICOS(7000), + .left_margin = 68, + .right_margin = 20, + .upper_margin = 15, + .lower_margin = 4, + .hsync_len = 30, + .vsync_len = 3, + .sync = FB_SYNC_OE_ACT_HIGH, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, +}; + +static struct imx_ipu_fb_platform_data ipu_fb_data = { + .mode = &imxfb_mode, + .bpp = 16, +}; + +static struct device_d imxfb_dev = { + .name = "imx-ipu-fb", + .map_base = 0x53fc0000, + .size = 0x1000, + .platform_data = &ipu_fb_data, +}; + +#ifdef CONFIG_MMU +static int eukrea_cpuimx35_mmu_init(void) +{ + mmu_init(); + + arm_create_section(0x80000000, 0x80000000, 128, PMD_SECT_DEF_CACHED); + arm_create_section(0x90000000, 0x80000000, 128, PMD_SECT_DEF_UNCACHED); + + setup_dma_coherent(0x10000000); + +#if TEXT_BASE & (0x100000 - 1) +#warning cannot create vector section. Adjust TEXT_BASE to a 1M boundary +#else + arm_create_section(0x0, TEXT_BASE, 1, PMD_SECT_DEF_UNCACHED); +#endif + mmu_enable(); + +#ifdef CONFIG_CACHE_L2X0 + l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000); +#endif + return 0; +} +postcore_initcall(eukrea_cpuimx35_mmu_init); +#endif + +static int eukrea_cpuimx35_devices_init(void) +{ + register_device(&nand_dev); + + devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); + + register_device(&fec_dev); + + register_device(&sdram_dev); + register_device(&imxfb_dev); + + armlinux_add_dram(&sdram_dev); + armlinux_set_bootparams((void *)0x80000100); + armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX35); + + return 0; +} + +device_initcall(eukrea_cpuimx35_devices_init); + +static int eukrea_cpuimx35_enable_display(void) +{ + gpio_direction_output(1, 1); + gpio_direction_output(0, 0); + return 0; +} + +late_initcall(eukrea_cpuimx35_enable_display); + +static struct device_d eukrea_cpuimx35_serial_device = { + .name = "imx_serial", + .map_base = IMX_UART1_BASE, + .size = 4096, +}; + +static struct pad_desc eukrea_cpuimx35_pads[] = { + MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, + MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, + MX35_PAD_FEC_RX_DV__FEC_RX_DV, + MX35_PAD_FEC_COL__FEC_COL, + MX35_PAD_FEC_RDATA0__FEC_RDATA_0, + MX35_PAD_FEC_TDATA0__FEC_TDATA_0, + MX35_PAD_FEC_TX_EN__FEC_TX_EN, + MX35_PAD_FEC_MDC__FEC_MDC, + MX35_PAD_FEC_MDIO__FEC_MDIO, + MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, + MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, + MX35_PAD_FEC_CRS__FEC_CRS, + MX35_PAD_FEC_RDATA0__FEC_RDATA_0, + MX35_PAD_FEC_TDATA0__FEC_TDATA_0, + MX35_PAD_FEC_RDATA1__FEC_RDATA_1, + MX35_PAD_FEC_TDATA1__FEC_TDATA_1, + MX35_PAD_FEC_RDATA2__FEC_RDATA_2, + MX35_PAD_FEC_TDATA2__FEC_TDATA_2, + MX35_PAD_FEC_RDATA3__FEC_RDATA_3, + MX35_PAD_FEC_TDATA3__FEC_TDATA_3, + + MX35_PAD_RXD1__UART1_RXD_MUX, + MX35_PAD_TXD1__UART1_TXD_MUX, + MX35_PAD_RTS1__UART1_RTS, + MX35_PAD_CTS1__UART1_CTS, +}; + +static int eukrea_cpuimx35_console_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads, + ARRAY_SIZE(eukrea_cpuimx35_pads)); + + register_device(&eukrea_cpuimx35_serial_device); + return 0; +} + +console_initcall(eukrea_cpuimx35_console_init); + +static int eukrea_cpuimx35_core_init(void) +{ + u32 reg; + + /* enable clock for I2C1 and FEC */ + reg = readl(IMX_CCM_BASE + CCM_CGR1); + reg |= 0x3 << CCM_CGR1_FEC_SHIFT; + reg = writel(reg, IMX_CCM_BASE + CCM_CGR1); + + /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/ + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + writel(0x77777777, IMX_AIPS1_BASE); + writel(0x77777777, IMX_AIPS1_BASE + 0x4); + writel(0x77777777, IMX_AIPS2_BASE); + writel(0x77777777, IMX_AIPS2_BASE + 0x4); + + /* + * Clear the on and off peripheral modules Supervisor Protect bit + * for SDMA to access them. Did not change the AIPS control registers + * (offset 0x20) access type + */ + writel(0x0, IMX_AIPS1_BASE + 0x40); + writel(0x0, IMX_AIPS1_BASE + 0x44); + writel(0x0, IMX_AIPS1_BASE + 0x48); + writel(0x0, IMX_AIPS1_BASE + 0x4C); + reg = readl(IMX_AIPS1_BASE + 0x50); + reg &= 0x00FFFFFF; + writel(reg, IMX_AIPS1_BASE + 0x50); + + writel(0x0, IMX_AIPS2_BASE + 0x40); + writel(0x0, IMX_AIPS2_BASE + 0x44); + writel(0x0, IMX_AIPS2_BASE + 0x48); + writel(0x0, IMX_AIPS2_BASE + 0x4C); + reg = readl(IMX_AIPS2_BASE + 0x50); + reg &= 0x00FFFFFF; + writel(reg, IMX_AIPS2_BASE + 0x50); + + /* MAX (Multi-Layer AHB Crossbar Switch) setup */ + + /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ +#define MAX_PARAM1 0x00302154 + writel(MAX_PARAM1, IMX_MAX_BASE + 0x000); /* for S0 */ + writel(MAX_PARAM1, IMX_MAX_BASE + 0x100); /* for S1 */ + writel(MAX_PARAM1, IMX_MAX_BASE + 0x200); /* for S2 */ + writel(MAX_PARAM1, IMX_MAX_BASE + 0x300); /* for S3 */ + writel(MAX_PARAM1, IMX_MAX_BASE + 0x400); /* for S4 */ + + /* SGPCR - always park on last master */ + writel(0x10, IMX_MAX_BASE + 0x10); /* for S0 */ + writel(0x10, IMX_MAX_BASE + 0x110); /* for S1 */ + writel(0x10, IMX_MAX_BASE + 0x210); /* for S2 */ + writel(0x10, IMX_MAX_BASE + 0x310); /* for S3 */ + writel(0x10, IMX_MAX_BASE + 0x410); /* for S4 */ + + /* MGPCR - restore default values */ + writel(0x0, IMX_MAX_BASE + 0x800); /* for M0 */ + writel(0x0, IMX_MAX_BASE + 0x900); /* for M1 */ + writel(0x0, IMX_MAX_BASE + 0xa00); /* for M2 */ + writel(0x0, IMX_MAX_BASE + 0xb00); /* for M3 */ + writel(0x0, IMX_MAX_BASE + 0xc00); /* for M4 */ + writel(0x0, IMX_MAX_BASE + 0xd00); /* for M5 */ + + /* + * M3IF Control Register (M3IFCTL) + * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 + * MRRP[1] = MAX1 not on priority list (0 << 0) = 0x00000000 + * MRRP[2] = L2CC1 not on priority list (0 << 0) = 0x00000000 + * MRRP[3] = USB not on priority list (0 << 0) = 0x00000000 + * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 + * MRRP[5] = GPU not on priority list (0 << 0) = 0x00000000 + * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 + * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 + * ------------ + * 0x00000040 + */ + writel(0x40, IMX_M3IF_BASE); + + return 0; +} + +core_initcall(eukrea_cpuimx35_core_init); + +#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5)) +#define MPCTL_PARAM_532 ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1)) + +static int do_cpufreq(struct command *cmdtp, int argc, char *argv[]) +{ + unsigned long freq; + + if (argc != 2) + return COMMAND_ERROR_USAGE; + + freq = simple_strtoul(argv[1], NULL, 0); + + switch (freq) { + case 399: + writel(MPCTL_PARAM_399, IMX_CCM_BASE + CCM_MPCTL); + break; + case 532: + writel(MPCTL_PARAM_532, IMX_CCM_BASE + CCM_MPCTL); + break; + default: + return COMMAND_ERROR_USAGE; + } + + printf("Switched CPU frequency to %dMHz\n", freq); + + return 0; +} + +static const __maybe_unused char cmd_cpufreq_help[] = +"Usage: cpufreq 399|532\n" +"\n" +"Set CPU frequency to MHz\n"; + +BAREBOX_CMD_START(cpufreq) + .cmd = do_cpufreq, + .usage = "adjust CPU frequency", + BAREBOX_CMD_HELP(cmd_cpufreq_help) +BAREBOX_CMD_END diff --git a/board/eukrea_cpuimx35/eukrea_cpuimx35.dox b/board/eukrea_cpuimx35/eukrea_cpuimx35.dox new file mode 100644 index 0000000000..cbdf69db35 --- /dev/null +++ b/board/eukrea_cpuimx35/eukrea_cpuimx35.dox @@ -0,0 +1,4 @@ +/** @page eukrea_cpuimx35 Eukrea's CPUIMX35 + + +*/ diff --git a/board/eukrea_cpuimx35/flash_header.c b/board/eukrea_cpuimx35/flash_header.c new file mode 100644 index 0000000000..a0ccf5c8f7 --- /dev/null +++ b/board/eukrea_cpuimx35/flash_header.c @@ -0,0 +1,60 @@ +#include +#include + +extern unsigned long _stext; + +void __naked __flash_header_start go(void) +{ + __asm__ __volatile__("b exception_vectors\n"); +} + +struct imx_dcd_entry __dcd_entry_0x400 dcd_entry[] = { + { .ptr_type = 4, .addr = 0xB8001010, .val = 0x00000004, }, + { .ptr_type = 4, .addr = 0xB8001010, .val = 0x0000000C, }, + { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc3f, }, + { .ptr_type = 4, .addr = 0xB8001000, .val = 0x92220000, }, + { .ptr_type = 1, .addr = 0x80000400, .val = 0x12345678, }, + { .ptr_type = 4, .addr = 0xB8001000, .val = 0xA2220000, }, + { .ptr_type = 1, .addr = 0x80000000, .val = 0x87654321, }, + { .ptr_type = 1, .addr = 0x80000000, .val = 0x87654321, }, + { .ptr_type = 4, .addr = 0xB8001000, .val = 0xB2220000, }, + { .ptr_type = 1, .addr = 0x80000033, .val = 0xda, }, + { .ptr_type = 1, .addr = 0x82000000, .val = 0xda, }, + { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, }, + { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, }, + { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, }, + { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, }, + { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, }, + { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, }, + { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, }, + { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, }, + { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, }, + { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, }, + { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, }, + { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, }, + { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, }, + { .ptr_type = 4, .addr = 0xB8001000, .val = 0x82220080, }, + { .ptr_type = 4, .addr = 0xB8001000, .val = 0x82228080, }, + { .ptr_type = 4, .addr = 0xB8001020, .val = 0x80000028, }, + { .ptr_type = 4, .addr = 0xB8001024, .val = 0x80000028, }, + { .ptr_type = 4, .addr = 0xB8001028, .val = 0x80000028, }, + { .ptr_type = 4, .addr = 0xB800102c, .val = 0x80000028, }, + { .ptr_type = 4, .addr = 0xB8001030, .val = 0x80000028, }, +}; + +#define APP_DEST 0x80000000 + +struct imx_flash_header __flash_header_0x400 flash_header = { + .app_code_jump_vector = APP_DEST + 0x1000, + .app_code_barker = APP_CODE_BARKER, + .app_code_csf = 0, + .dcd_ptr_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd), + .super_root_key = 0, + .dcd = APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd_barker), + .app_dest = APP_DEST, + .dcd_barker = DCD_BARKER, + .dcd_block_len = sizeof (dcd_entry), +}; + +unsigned long __image_len_0x400 barebox_len = 0x40000; + diff --git a/board/eukrea_cpuimx35/lowlevel.c b/board/eukrea_cpuimx35/lowlevel.c new file mode 100644 index 0000000000..44f3cf0725 --- /dev/null +++ b/board/eukrea_cpuimx35/lowlevel.c @@ -0,0 +1,218 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Assuming 24MHz input clock */ +#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5)) +#define MPCTL_PARAM_532 ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1)) +#define PPCTL_PARAM_300 (IMX_PLL_PD(0) | IMX_PLL_MFD(3) | IMX_PLL_MFI(6) | IMX_PLL_MFN(1)) + +#ifdef CONFIG_NAND_IMX_BOOT +static void __bare_init __naked insdram(void) +{ + uint32_t r; + + /* Speed up NAND controller by adjusting the NFC divider */ + r = readl(IMX_CCM_BASE + CCM_PDR4); + r &= ~(0xf << 28); + r |= 0x1 << 28; + writel(r, IMX_CCM_BASE + CCM_PDR4); + + /* setup a stack to be able to call imx_nand_load_image() */ + r = STACK_BASE + STACK_SIZE - 12; + __asm__ __volatile__("mov sp, %0" : : "r"(r)); + + imx_nand_load_image((void *)TEXT_BASE, 256 * 1024); + + board_init_lowlevel_return(); +} +#endif + +void __bare_init __naked board_init_lowlevel(void) +{ + uint32_t r, s; + unsigned long ccm_base = IMX_CCM_BASE; + unsigned long iomuxc_base = IMX_IOMUXC_BASE; +#ifdef CONFIG_NAND_IMX_BOOT + unsigned int *trg, *src; + int i; +#endif + + r = get_cr(); + r |= CR_Z; /* Flow prediction (Z) */ + r |= CR_U; /* unaligned accesses */ + r |= CR_FI; /* Low Int Latency */ + + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(s)); + s |= 0x7; + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1" : : "r"(s)); + + set_cr(r); + + r = 0; + __asm__ __volatile__("mcr p15, 0, %0, c15, c2, 4" : : "r"(r)); + + /* + * Branch predicition is now enabled. Flush the BTAC to ensure a valid + * starting point. Don't flush BTAC while it is disabled to avoid + * ARM1136 erratum 408023. + */ + __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 6" : : "r"(r)); + + /* invalidate I cache and D cache */ + __asm__ __volatile__("mcr p15, 0, %0, c7, c7, 0" : : "r"(r)); + + /* invalidate TLBs */ + __asm__ __volatile__("mcr p15, 0, %0, c8, c7, 0" : : "r"(r)); + + /* Drain the write buffer */ + __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" : : "r"(r)); + + /* Also setup the Peripheral Port Remap register inside the core */ + r = 0x40000015; /* start from AIPS 2GB region */ + __asm__ __volatile__("mcr p15, 0, %0, c15, c2, 4" : : "r"(r)); + + /* + * End of ARM1136 init + */ + + writel(0x003F4208, ccm_base + CCM_CCMR); + + /* Set MPLL , arm clock and ahb clock*/ + writel(MPCTL_PARAM_532, ccm_base + CCM_MPCTL); + + writel(PPCTL_PARAM_300, ccm_base + CCM_PPCTL); + writel(0x00001000, ccm_base + CCM_PDR0); + + r = readl(ccm_base + CCM_CGR0); + r |= 0x00300000; + writel(r, ccm_base + CCM_CGR0); + + r = readl(ccm_base + CCM_CGR1); + r |= 0x00000C00; + r |= 0x00000003; + writel(r, ccm_base + CCM_CGR1); + + r = readl(IMX_L2CC_BASE + L2X0_AUX_CTRL); + r |= 0x1000; + writel(r, IMX_L2CC_BASE + L2X0_AUX_CTRL); + + /* Skip SDRAM initialization if we run from RAM */ + r = get_pc(); + if (r > 0x80000000 && r < 0x90000000) + board_init_lowlevel_return(); + + /* Set DDR Type to SDRAM, drive strength workaround * + * 0x00000000 MDDR * + * 0x00000800 3,3V SDRAM */ + + r = 0x00000800; + writel(r, iomuxc_base + 0x794); + writel(r, iomuxc_base + 0x798); + writel(r, iomuxc_base + 0x79c); + writel(r, iomuxc_base + 0x7a0); + writel(r, iomuxc_base + 0x7a4); + + /* MDDR init, enable mDDR*/ + writel(0x00000304, ESDMISC); /* was 0x00000004 */ + + /* set timing paramters */ + writel(0x00255417, ESDCFG0); + /* select Precharge-All mode */ + writel(0x92220000, ESDCTL0); + /* Precharge-All */ + writel(0x12345678, IMX_SDRAM_CS0 + 0x400); + + /* select Load-Mode-Register mode */ + writel(0xB8001000, ESDCTL0); + /* Load reg EMR2 */ + writeb(0xda, 0x84000000); + /* Load reg EMR3 */ + writeb(0xda, 0x86000000); + /* Load reg EMR1 -- enable DLL */ + writeb(0xda, 0x82000400); + /* Load reg MR -- reset DLL */ + writeb(0xda, 0x80000333); + + /* select Precharge-All mode */ + writel(0x92220000, ESDCTL0); + /* Precharge-All */ + writel(0x12345678, IMX_SDRAM_CS0 + 0x400); + + /* select Manual-Refresh mode */ + writel(0xA2220000, ESDCTL0); + /* Manual-Refresh 2 times */ + writel(0x87654321, IMX_SDRAM_CS0); + writel(0x87654321, IMX_SDRAM_CS0); + + /* select Load-Mode-Register mode */ + writel(0xB2220000, ESDCTL0); + /* Load reg MR -- CL3, BL8, end DLL reset */ + writeb(0xda, 0x80000233); + /* Load reg EMR1 -- OCD default */ + writeb(0xda, 0x82000780); + /* Load reg EMR1 -- OCD exit */ + writeb(0xda, 0x82000400); + + /* select normal-operation mode + * DSIZ32-bit, BL8, COL10-bit, ROW13-bit + * disable PWT & PRCT + * disable Auto-Refresh */ + writel(0x82220080, ESDCTL0); + + /* enable Auto-Refresh */ + writel(0x82228080, ESDCTL0); + /* enable Auto-Refresh */ + writel(0x00002000, ESDCTL1); + +#ifdef CONFIG_NAND_IMX_BOOT + /* skip NAND boot if not running from NFC space */ + r = get_pc(); + if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800) + board_init_lowlevel_return(); + + src = (unsigned int *)IMX_NFC_BASE; + trg = (unsigned int *)TEXT_BASE; + + /* Move ourselves out of NFC SRAM */ + for (i = 0; i < 0x800 / sizeof(int); i++) + *trg++ = *src++; + + /* Jump to SDRAM */ + r = (unsigned int)&insdram; + __asm__ __volatile__("mov pc, %0" : : "r"(r)); +#else + board_init_lowlevel_return(); +#endif +} + -- cgit v1.2.3