From 7a8d295cdf605e2bc01c201b9998917ebaf2f46f Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Tue, 10 Jan 2017 07:08:58 -0800 Subject: i.MX: clk: Add IMX_PLLV3_SYS_VF610 subtype Add IMX_PLLV3_SYS_VF610 subtype to pllv3 code to be able to control and re-clock PLL1 and PLL2 on Vybrid SoC. This commit also introduces imx_clk_pllv3_locked which allows the user to create PLLv3 and specify how it should be polled for "locked" status (used in .set_rate callback) Signed-off-by: Andrey Smirnov Signed-off-by: Sascha Hauer --- drivers/clk/imx/clk.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers/clk/imx/clk.h') diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 970f65c7d1..0b28fb24fb 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -78,6 +78,7 @@ struct clk *imx_clk_pllv2(const char *name, const char *parent, enum imx_pllv3_type { IMX_PLLV3_GENERIC, IMX_PLLV3_SYS, + IMX_PLLV3_SYS_VF610, IMX_PLLV3_USB, IMX_PLLV3_USB_VF610, IMX_PLLV3_AV, @@ -89,6 +90,10 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, const char *parent, void __iomem *base, u32 div_mask); +struct clk *imx_clk_pllv3_locked(enum imx_pllv3_type type, const char *name, + const char *parent, void __iomem *base, + u32 div_mask, void __iomem *lock_reg, u32 lock_mask); + struct clk *imx_clk_pfd(const char *name, const char *parent, void __iomem *reg, u8 idx); -- cgit v1.2.3