From 459bf1fd31da2c091c6c1e3a7e0f6a1b1cbf588b Mon Sep 17 00:00:00 2001 From: "perachet7@gmail.com" Date: Thu, 8 Nov 2018 15:34:29 +0100 Subject: ARM: clk: rk3188: don't set same clk rate twice We found setting a clock rate which has already been set, rk3188 (radxa rock pro) bails out. This is a quick fix only. Underlying situation not (yet) investigated: why it is even trying to set it to the same rate again. It remains to state that some but not all rrpro boards exhibit this behaviour, no other rk3188 boards have been tested. Signed-off-by: P. Rachet Signed-off-by: Sascha Hauer --- drivers/clk/rockchip/clk-pll.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/clk/rockchip/clk-pll.c') diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index f0dc12091b..87a3969c28 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -164,6 +164,9 @@ static int rockchip_rk3066_pll_set_rate(struct clk *hw, unsigned long drate, int cur_parent; int ret; + if (old_rate == drate) + return 0; + pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n", __func__, __clk_get_name(hw), old_rate, drate, prate); -- cgit v1.2.3