From 7b6c063f5786b7552c2c8a97f3c57a3cd5b966a7 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Tue, 3 Dec 2013 20:56:56 +0100 Subject: tegra: speed up system bus We run the system bus from the OSC clock during init, to avoid crashing the system while reconfiguring the PLLs. Switch to a more reasonable clock when we are done with this. Signed-off-by: Lucas Stach Signed-off-by: Sascha Hauer --- drivers/clk/tegra/clk-tegra20.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers/clk/tegra') diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index e70f99a1fc..b94b7bc888 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -325,6 +325,13 @@ static int tegra20_car_probe(struct device_d *dev) tegra_init_from_table(init_table, clks, clk_max); + /* speed up system bus */ + writel(CRC_SCLK_BURST_POLICY_SYS_STATE_RUN << + CRC_SCLK_BURST_POLICY_SYS_STATE_SHIFT | + CRC_SCLK_BURST_POLICY_SRC_PLLC_OUT1 << + CRC_SCLK_BURST_POLICY_RUN_SRC_SHIFT, + car_base + CRC_SCLK_BURST_POLICY); + clk_data.clks = clks; clk_data.clk_num = ARRAY_SIZE(clks); of_clk_add_provider(dev->device_node, of_clk_src_onecell_get, -- cgit v1.2.3