From 8eba1cd4bbedec75161d42ef9fab38737c9a2333 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 8 Mar 2022 11:52:30 +0100 Subject: clk: imx6: Add hdmi_isfr clk The hdmi_isfr clk is requested and enabled by the hdmi driver, but it is never registered, so effectively a dummy clk is used in the hdmi driver. Add the clk and its parents so that the real clk is used. One of the parents is pll3_pfd1_540m which happens to be enabled in our pfd clock workaround in imx6_init_lowlevel(). This patch is necessary when that workaround is removed later. Signed-off-by: Sascha Hauer --- drivers/clk/imx/clk-imx6.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/imx/clk-imx6.c b/drivers/clk/imx/clk-imx6.c index e3afcf7858..aa5876d21b 100644 --- a/drivers/clk/imx/clk-imx6.c +++ b/drivers/clk/imx/clk-imx6.c @@ -152,7 +152,7 @@ static const char *cko1_sels[] = { "pll2_bus", "pll1_sys", "pll5_video", - "dummy", + "video_27m", "axi", "enfc", "ipu1_di0", @@ -612,6 +612,8 @@ static void imx6_add_video_clks(void __iomem *anab, void __iomem *cb, struct dev clks[IMX6QDL_CLK_IPU2_DI0_PRE] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", cb + 0x38, 3, 3); clks[IMX6QDL_CLK_IPU2_DI1_PRE] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", cb + 0x38, 12, 3); + clks[IMX6QDL_CLK_HDMI_IAHB] = imx_clk_gate2("hdmi_iahb", "ahb", cb + 0x70, 0); + clks[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_gate2("hdmi_isfr", "mipi_core_cfg", cb + 0x70, 4); clks[IMX6QDL_CLK_IPU1] = imx_clk_gate2("ipu1", "ipu1_podf", cb + 0x74, 0); clks[IMX6QDL_CLK_IPU1_DI0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", cb + 0x74, 2); clks[IMX6QDL_CLK_IPU1_DI1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", cb + 0x74, 4); @@ -620,6 +622,8 @@ static void imx6_add_video_clks(void __iomem *anab, void __iomem *cb, struct dev clks[IMX6QDL_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", cb + 0x74, 12); clks[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", cb + 0x74, 14); clks[IMX6QDL_CLK_IPU2_DI1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", cb + 0x74, 10); + clks[IMX6QDL_CLK_MIPI_CORE_CFG] = imx_clk_gate2("mipi_core_cfg", "video_27m", cb + 0x74, 16); + clks[IMX6QDL_CLK_VIDEO_27M] = imx_clk_fixed_factor("video_27m", "pll3_pfd1_540m", 1, 20); clk_set_parent(clks[IMX6QDL_CLK_IPU1_DI0_SEL], clks[IMX6QDL_CLK_IPU1_DI0_PRE]); clk_set_parent(clks[IMX6QDL_CLK_IPU1_DI1_SEL], clks[IMX6QDL_CLK_IPU1_DI1_PRE]); -- cgit v1.2.3