From 9c6f1ff171687360721d68518d8ece264b01bf25 Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Wed, 8 Feb 2023 14:35:18 +0100 Subject: ddr: imx8m: add support for 3720 MHz DDR rate Signed-off-by: Ahmad Fatoum Signed-off-by: Lucas Stach Link: https://lore.barebox.org/20230208133519.1114700-1-l.stach@pengutronix.de Signed-off-by: Sascha Hauer --- drivers/ddr/imx8m/ddrphy_utils.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/ddr') diff --git a/drivers/ddr/imx8m/ddrphy_utils.c b/drivers/ddr/imx8m/ddrphy_utils.c index 98e6ae648a..7f863a1736 100644 --- a/drivers/ddr/imx8m/ddrphy_utils.c +++ b/drivers/ddr/imx8m/ddrphy_utils.c @@ -17,6 +17,7 @@ * clock / 2, which is therefor transfer rate / 4. */ enum ddr_rate { DDR_4000, + DDR_3720, DDR_3200, DDR_3000, DDR_2600, /* Unused */ @@ -52,6 +53,7 @@ static const struct imx8mm_fracpll_config { bool valid; } imx8mm_fracpll_table[DDR_NUM_RATES] = { [DDR_4000] = { .valid = true, .r1 = MDIV(250) | PDIV(3) | SDIV(1), .r2 = 0 }, + [DDR_3720] = { .valid = true, .r1 = MDIV(310) | PDIV(2) | SDIV(2), .r2 = 0 }, [DDR_3200] = { .valid = true, .r1 = MDIV(300) | PDIV(9) | SDIV(0), .r2 = 0 }, [DDR_3000] = { .valid = true, .r1 = MDIV(250) | PDIV(8) | SDIV(0), .r2 = 0 }, [DDR_2600] = { .valid = true, .r1 = MDIV(325) | PDIV(3) | SDIV(2), .r2 = 0 }, @@ -335,6 +337,7 @@ void ddrphy_init_set_dfi_clk(unsigned int drate_mhz, enum ddrc_type type) switch (drate_mhz) { case 4000: drate = DDR_4000; break; + case 3720: drate = DDR_3720; break; case 3200: drate = DDR_3200; break; case 3000: drate = DDR_3000; break; case 2400: drate = DDR_2400; break; -- cgit v1.2.3