From df17efad5986db403854e8d694d1d12e7aab58f9 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 26 Nov 2014 15:49:22 +0100 Subject: mci: imx-esdhc: Fix Interrupt enable register for i.MX6sx The reset default of this register has changed on i.MX6sx. Explicitly write the value we want to have to make it work on i.MX6sx. Signed-off-by: Sascha Hauer --- drivers/mci/imx-esdhc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/mci') diff --git a/drivers/mci/imx-esdhc.c b/drivers/mci/imx-esdhc.c index 487cd41958..5ac58c3a28 100644 --- a/drivers/mci/imx-esdhc.c +++ b/drivers/mci/imx-esdhc.c @@ -474,8 +474,9 @@ static int esdhc_init(struct mci_host *mci, struct device_d *dev) /* Set the initial clock speed */ set_sysctl(mci, 400000); - /* Disable the BRR and BWR bits in IRQSTAT */ - esdhc_clrbits32(regs + SDHCI_INT_ENABLE, IRQSTATEN_BRR | IRQSTATEN_BWR); + writel(IRQSTATEN_CC | IRQSTATEN_TC | IRQSTATEN_CINT | IRQSTATEN_CTOE | + IRQSTATEN_CCE | IRQSTATEN_CEBE | IRQSTATEN_CIE | IRQSTATEN_DTOE | + IRQSTATEN_DCE | IRQSTATEN_DEBE | IRQSTATEN_DINT, regs + SDHCI_INT_ENABLE); /* Put the PROCTL reg back to the default */ esdhc_write32(regs + SDHCI_HOST_CONTROL__POWER_CONTROL__BLOCK_GAP_CONTROL, -- cgit v1.2.3