From b6bcd96de5a75bdc5d06a06f2efffc2d89e346ec Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 30 Oct 2020 12:30:31 +0100 Subject: mtd: nand: Update to Linux-5.9 This updates the barebox NAND layer and parts of the mtd layer to Linux-5.9. This patch is huge, but the barebox NAND layer is so far away from the Linux NAND layer that a step by step update would have taken ages. Unlike Linux barebox has functions to mark a block as good. This feature has been preserved. Also barebox used to make NAND write support optional, this feature is lost during the update for the sake of better compatibility to the Linux NAND layer. This patch has been tested: - GPMI aka nand_mxs on i.MX6 - nand_imx on i.MX25 - nand_omap_gpmc on AM335x - atmel_nand on Atmel sama5d3 - nand_denali on SoCFPGA Currently untested: - nand_orion - nand_mrvl_nfc - nand_s3c24xx The nand_denali driver is tested with the update of that driver to Linux-5.9 following in the next patch. I could only test the drivers with the NAND chips found on my boards, so there's still enough room for regressions, especially given that the NAND drivers themselves are mostly not updated. With the NAND layer being up-to-date with Linux it should hopefully be easy to update drivers to their Linux counterpart as well if necessary. Signed-off-by: Sascha Hauer --- drivers/mtd/nand/nand_amd.c | 53 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 drivers/mtd/nand/nand_amd.c (limited to 'drivers/mtd/nand/nand_amd.c') diff --git a/drivers/mtd/nand/nand_amd.c b/drivers/mtd/nand/nand_amd.c new file mode 100644 index 0000000000..c3d4dae3cd --- /dev/null +++ b/drivers/mtd/nand/nand_amd.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2017 Free Electrons + * Copyright (C) 2017 NextThing Co + * + * Author: Boris Brezillon + */ + +#include "internals.h" + +static void amd_nand_decode_id(struct nand_chip *chip) +{ + struct mtd_info *mtd = nand_to_mtd(chip); + struct nand_memory_organization *memorg; + + memorg = nanddev_get_memorg(&chip->base); + + nand_decode_ext_id(chip); + + /* + * Check for Spansion/AMD ID + repeating 5th, 6th byte since + * some Spansion chips have erasesize that conflicts with size + * listed in nand_ids table. + * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) + */ + if (chip->id.data[4] != 0x00 && chip->id.data[5] == 0x00 && + chip->id.data[6] == 0x00 && chip->id.data[7] == 0x00 && + memorg->pagesize == 512) { + memorg->pages_per_eraseblock = 256; + memorg->pages_per_eraseblock <<= ((chip->id.data[3] & 0x03) << 1); + mtd->erasesize = memorg->pages_per_eraseblock * + memorg->pagesize; + } +} + +static int amd_nand_init(struct nand_chip *chip) +{ + if (nand_is_slc(chip)) + /* + * According to the datasheet of some Cypress SLC NANDs, + * the bad block markers can be in the first, second or last + * page of a block. So let's check all three locations. + */ + chip->options |= NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE | + NAND_BBM_LASTPAGE; + + return 0; +} + +const struct nand_manufacturer_ops amd_nand_manuf_ops = { + .detect = amd_nand_decode_id, + .init = amd_nand_init, +}; -- cgit v1.2.3