From e3bc3f751d75d077756b162a5c2b800b0ebfa9fd Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 20 Sep 2012 22:02:06 +0200 Subject: serial i.MX: Switch to clk support Signed-off-by: Sascha Hauer --- drivers/serial/serial_imx.c | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) (limited to 'drivers/serial/serial_imx.c') diff --git a/drivers/serial/serial_imx.c b/drivers/serial/serial_imx.c index 012ab028a1..96f67122cc 100644 --- a/drivers/serial/serial_imx.c +++ b/drivers/serial/serial_imx.c @@ -22,6 +22,8 @@ #include #include #include +#include +#include #define URXD0 0x0 /* Receiver Register */ #define URTX0 0x40 /* Transmitter Register */ @@ -170,16 +172,17 @@ struct imx_serial_priv { int baudrate; struct notifier_block notify; void __iomem *regs; + struct clk *clk; }; -static int imx_serial_reffreq(void __iomem *regs) +static int imx_serial_reffreq(struct imx_serial_priv *priv) { ulong rfdiv; - rfdiv = (readl(regs + UFCR) >> 7) & 7; + rfdiv = (readl(priv->regs + UFCR) >> 7) & 7; rfdiv = rfdiv < 6 ? 6 - rfdiv : 7; - return imx_get_uartclk() / rfdiv; + return clk_get_rate(priv->clk) / rfdiv; } /* @@ -209,7 +212,7 @@ static int imx_serial_init_port(struct console_device *cdev) writel(0xa81, regs + UFCR); #ifdef ONEMS - writel(imx_serial_reffreq(regs) / 1000, regs + ONEMS); + writel(imx_serial_reffreq(priv) / 1000, regs + ONEMS); #endif /* Enable FIFOs */ @@ -291,7 +294,7 @@ static int imx_serial_setbaudrate(struct console_device *cdev, int baudrate) /* Set the numerator value minus one of the BRM ratio */ writel((baudrate / 100) - 1, regs + UBIR); /* Set the denominator value minus one of the BRM ratio */ - writel((imx_serial_reffreq(regs) / 1600) - 1, regs + UBMR); + writel((imx_serial_reffreq(priv) / 1600) - 1, regs + UBMR); writel(ucr1, regs + UCR1); @@ -316,11 +319,18 @@ static int imx_serial_probe(struct device_d *dev) struct console_device *cdev; struct imx_serial_priv *priv; uint32_t val; + int ret; priv = xzalloc(sizeof(*priv)); cdev = &priv->cdev; dev->priv = priv; + priv->clk = clk_get(dev, NULL); + if (IS_ERR(priv->clk)) { + ret = PTR_ERR(priv->clk); + goto err_free; + } + priv->regs = dev_request_mem_region(dev, 0); cdev->dev = dev; cdev->f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR; @@ -343,6 +353,11 @@ static int imx_serial_probe(struct device_d *dev) clock_register_client(&priv->notify); return 0; + +err_free: + free(priv); + + return ret; } static void imx_serial_remove(struct device_d *dev) -- cgit v1.2.3 From d4edd480b2ab0754361b142e307796405310d34b Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 24 Sep 2012 12:16:12 +0200 Subject: ARM i.MX: Remove old clock support The old clock support is now unused. Remove it. The former i.MX clko command is superseeded by generic clock manipulation commands. Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/Kconfig | 8 - arch/arm/mach-imx/Makefile | 20 +- arch/arm/mach-imx/clko.c | 60 ----- arch/arm/mach-imx/clocksource.c | 1 - arch/arm/mach-imx/include/mach/clock.h | 42 +--- arch/arm/mach-imx/speed-imx1.c | 91 -------- arch/arm/mach-imx/speed-imx21.c | 193 ---------------- arch/arm/mach-imx/speed-imx25.c | 155 ------------- arch/arm/mach-imx/speed-imx27.c | 227 ------------------ arch/arm/mach-imx/speed-imx31.c | 79 ------- arch/arm/mach-imx/speed-imx35.c | 255 --------------------- arch/arm/mach-imx/speed-imx51.c | 311 ------------------------- arch/arm/mach-imx/speed-imx53.c | 236 ------------------- arch/arm/mach-imx/speed-imx6.c | 404 --------------------------------- arch/arm/mach-imx/speed.c | 82 ------- drivers/mci/imx-esdhc.c | 1 - drivers/serial/serial_imx.c | 1 - drivers/spi/imx_spi.c | 1 - drivers/video/imx.c | 1 - 19 files changed, 10 insertions(+), 2158 deletions(-) delete mode 100644 arch/arm/mach-imx/clko.c delete mode 100644 arch/arm/mach-imx/speed-imx1.c delete mode 100644 arch/arm/mach-imx/speed-imx21.c delete mode 100644 arch/arm/mach-imx/speed-imx25.c delete mode 100644 arch/arm/mach-imx/speed-imx27.c delete mode 100644 arch/arm/mach-imx/speed-imx31.c delete mode 100644 arch/arm/mach-imx/speed-imx35.c delete mode 100644 arch/arm/mach-imx/speed-imx51.c delete mode 100644 arch/arm/mach-imx/speed-imx53.c delete mode 100644 arch/arm/mach-imx/speed-imx6.c delete mode 100644 arch/arm/mach-imx/speed.c (limited to 'drivers/serial/serial_imx.c') diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 7ab812abc5..d27d4f34d5 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -552,14 +552,6 @@ endmenu menu "i.MX specific settings " -config IMX_CLKO - bool "clko command" - depends on ARCH_IMX21 || ARCH_IMX27 || ARCH_IMX35 || ARCH_IMX25 || ARCH_IMX51 - help - The i.MX SoCs have a Pin which can output different reference frequencies. - Say y here if you want to have the clko command which lets you select the - frequency to output on this pin. - config IMX_IIM tristate "IIM fusebox device" depends on !ARCH_IMX21 && !ARCH_IMX21 diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index f7a5ba4a3a..e43f92e430 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -1,20 +1,18 @@ obj-y += clocksource.o gpio.o obj-$(CONFIG_RESET_SOURCE) += reset_source.o -obj-$(CONFIG_ARCH_IMX1) += speed-imx1.o imx1.o iomux-v1.o clk-imx1.o -obj-$(CONFIG_ARCH_IMX25) += speed-imx25.o imx25.o iomux-v3.o clk-imx25.o -obj-$(CONFIG_ARCH_IMX21) += speed-imx21.o imx21.o iomux-v1.o clk-imx21.o -obj-$(CONFIG_ARCH_IMX27) += speed-imx27.o imx27.o iomux-v1.o clk-imx27.o -obj-$(CONFIG_ARCH_IMX31) += speed-imx31.o imx31.o iomux-v2.o clk-imx31.o -obj-$(CONFIG_ARCH_IMX35) += speed-imx35.o imx35.o iomux-v3.o clk-imx35.o -obj-$(CONFIG_ARCH_IMX51) += speed-imx51.o imx51.o iomux-v3.o imx5.o clk-imx5.o -obj-$(CONFIG_ARCH_IMX53) += speed-imx53.o imx53.o iomux-v3.o imx5.o clk-imx5.o -obj-$(CONFIG_ARCH_IMX6) += speed-imx6.o imx6.o iomux-v3.o usb-imx6.o clk-imx6.o -obj-$(CONFIG_IMX_CLKO) += clko.o +obj-$(CONFIG_ARCH_IMX1) += imx1.o iomux-v1.o clk-imx1.o +obj-$(CONFIG_ARCH_IMX25) += imx25.o iomux-v3.o clk-imx25.o +obj-$(CONFIG_ARCH_IMX21) += imx21.o iomux-v1.o clk-imx21.o +obj-$(CONFIG_ARCH_IMX27) += imx27.o iomux-v1.o clk-imx27.o +obj-$(CONFIG_ARCH_IMX31) += imx31.o iomux-v2.o clk-imx31.o +obj-$(CONFIG_ARCH_IMX35) += imx35.o iomux-v3.o clk-imx35.o +obj-$(CONFIG_ARCH_IMX51) += imx51.o iomux-v3.o imx5.o clk-imx5.o +obj-$(CONFIG_ARCH_IMX53) += imx53.o iomux-v3.o imx5.o clk-imx5.o +obj-$(CONFIG_ARCH_IMX6) += imx6.o iomux-v3.o usb-imx6.o clk-imx6.o obj-$(CONFIG_IMX_IIM) += iim.o obj-$(CONFIG_NAND_IMX) += nand.o obj-$(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND) += external-nand-boot.o pbl-$(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND) += external-nand-boot.o obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-pfd.o -obj-y += speed.o obj-y += devices.o obj-y += boot.o diff --git a/arch/arm/mach-imx/clko.c b/arch/arm/mach-imx/clko.c deleted file mode 100644 index aeafaa9c41..0000000000 --- a/arch/arm/mach-imx/clko.c +++ /dev/null @@ -1,60 +0,0 @@ -#include -#include -#include -#include -#include - -static int do_clko(int argc, char *argv[]) -{ - int opt, div = 0, src = -2, num = 1, ret; - - while((opt = getopt(argc, argv, "n:d:s:")) > 0) { - switch(opt) { - case 'n': - num = simple_strtoul(optarg, NULL, 0); - break; - case 'd': - div = simple_strtoul(optarg, NULL, 0); - break; - case 's': - src = simple_strtol(optarg, NULL, 0); - break; - } - } - - if (div == 0 && src == -2) - return COMMAND_ERROR_USAGE; - - if (src == -1) { - imx_clko_set_src(num, -1); - return 0; - } - - if (src != -2) - imx_clko_set_src(num, src); - - if (div != 0) { - ret = imx_clko_set_div(num, div); - if (ret < 0) - printf("CLKO-line %i not supported.\n", num); - else if (ret != div) - printf("Divider limited to %d.\n", ret); - } - - return 0; -} - -static __maybe_unused char cmd_clko_help[] = -"Usage: clko [OPTION]...\n" -"Route different signals to the i.MX clko pin\n" -" -n Number of CLKO-line (Default 1)\n" -" -d
Divider\n" -" -s Clock select. See Ref. Manual for valid sources. Use -1\n" -" for disabling clock output\n"; - -BAREBOX_CMD_START(clko) - .cmd = do_clko, - .usage = "Adjust CLKO setting", - BAREBOX_CMD_HELP(cmd_clko_help) -BAREBOX_CMD_END - diff --git a/arch/arm/mach-imx/clocksource.c b/arch/arm/mach-imx/clocksource.c index df018e68c6..9229fb78c9 100644 --- a/arch/arm/mach-imx/clocksource.c +++ b/arch/arm/mach-imx/clocksource.c @@ -33,7 +33,6 @@ #include #include #include -#include #include /* Part 1: Registers */ diff --git a/arch/arm/mach-imx/include/mach/clock.h b/arch/arm/mach-imx/include/mach/clock.h index f613395768..304a7c885c 100644 --- a/arch/arm/mach-imx/include/mach/clock.h +++ b/arch/arm/mach-imx/include/mach/clock.h @@ -1,41 +1 @@ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H -unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref); - -ulong imx_get_mpllclk(void); - -#ifdef CONFIG_ARCH_IMX27 -ulong imx_get_armclk(void); -#endif -#ifdef CONFIG_ARCH_IMX1 -static inline ulong imx_get_armclk(void) -{ - return imx_get_mpllclk(); -} -#endif - -ulong imx_get_spllclk(void); -ulong imx_get_fclk(void); -ulong imx_get_hclk(void); -ulong imx_get_bclk(void); -ulong imx_get_perclk1(void); -ulong imx_get_perclk2(void); -ulong imx_get_perclk3(void); -ulong imx_get_ahbclk(void); -ulong imx_get_fecclk(void); -ulong imx_get_gptclk(void); -ulong imx_get_uartclk(void); -ulong imx_get_lcdclk(void); -ulong fsl_get_i2cclk(void); -ulong imx_get_mmcclk(void); -ulong imx_get_cspiclk(void); -ulong imx_get_ipgclk(void); -ulong imx_get_usbclk(void); - -int imx_clko_set_div(int num, int div); -void imx_clko_set_src(int num, int src); - -void imx_dump_clocks(void); - -#endif /* __ASM_ARCH_CLOCK_H */ +/* nothing, but some drivers need this include */ diff --git a/arch/arm/mach-imx/speed-imx1.c b/arch/arm/mach-imx/speed-imx1.c deleted file mode 100644 index 2b62f6168f..0000000000 --- a/arch/arm/mach-imx/speed-imx1.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * - * (c) 2004 Sascha Hauer - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - - -#include -#include -#include -#include -#include - -ulong imx_get_spllclk(void) -{ - return imx_decode_pll(SPCTL0, CONFIG_SYSPLL_CLK_FREQ); -} - -ulong imx_get_mpllclk(void) -{ - return imx_decode_pll(MPCTL0, CONFIG_SYSPLL_CLK_FREQ); -} - -ulong imx_get_fclk(void) -{ - return (( CSCR>>15)&1) ? imx_get_mpllclk()>>1 : imx_get_mpllclk(); -} - -ulong imx_get_hclk(void) -{ - u32 bclkdiv = (( CSCR >> 10 ) & 0xf) + 1; - return imx_get_spllclk() / bclkdiv; -} - -ulong imx_get_bclk(void) -{ - return imx_get_hclk(); -} - -ulong imx_get_perclk1(void) -{ - return imx_get_spllclk() / (((PCDR) & 0xf)+1); -} - -ulong imx_get_perclk2(void) -{ - return imx_get_spllclk() / (((PCDR>>4) & 0xf)+1); -} - -ulong imx_get_perclk3(void) -{ - return imx_get_spllclk() / (((PCDR>>16) & 0x7f)+1); -} - -ulong imx_get_uartclk(void) -{ - return imx_get_perclk1(); -} - -ulong imx_get_gptclk(void) -{ - return imx_get_perclk1(); -} - -void imx_dump_clocks(void) -{ - printf("spll: %10ld Hz\n", imx_get_spllclk()); - printf("mpll: %10ld Hz\n", imx_get_mpllclk()); - printf("fclk: %10ld Hz\n", imx_get_fclk()); - printf("hclk: %10ld Hz\n", imx_get_hclk()); - printf("bclk: %10ld Hz\n", imx_get_bclk()); - printf("perclk1: %10ld Hz\n", imx_get_perclk1()); - printf("perclk2: %10ld Hz\n", imx_get_perclk2()); - printf("perclk3: %10ld Hz\n", imx_get_perclk3()); - printf("uart: %10ld Hz\n", imx_get_uartclk()); - printf("gpt: %10ld Hz\n", imx_get_gptclk()); -} - diff --git a/arch/arm/mach-imx/speed-imx21.c b/arch/arm/mach-imx/speed-imx21.c deleted file mode 100644 index b9ecd2fa70..0000000000 --- a/arch/arm/mach-imx/speed-imx21.c +++ /dev/null @@ -1,193 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include - -#ifndef CLK32 -#define CLK32 32768 -#endif - -static ulong clk_in_32k(void) -{ - return 512 * CLK32; -} - -static ulong clk_in_26m(void) -{ - if (CSCR & CSCR_OSC26M_DIV1P5) { - /* divide by 1.5 */ - return 173333333; - } else { - /* divide by 1 */ - return 26000000; - } -} - -ulong imx_get_mpllclk(void) -{ - ulong cscr = CSCR; - ulong fref; - - if (cscr & CSCR_MCU_SEL) - fref = clk_in_26m(); - else - fref = clk_in_32k(); - - return imx_decode_pll(MPCTL0, fref); -} - -ulong imx_get_fclk(void) -{ - ulong cscr = CSCR; - ulong fref = imx_get_mpllclk(); - ulong div; - - div = ((cscr >> 29) & 0x7) + 1; - - return fref / div; -} - -/* HCLK */ -ulong imx_get_armclk(void) -{ - ulong cscr = CSCR; - ulong fref = imx_get_mpllclk(); - ulong div; - - div = ((cscr >> 10) & 0xF) + 1; - - return fref / div; -} - -ulong imx_get_spllclk(void) -{ - ulong cscr = CSCR; - ulong spctl0; - ulong fref; - - if (cscr & CSCR_SP_SEL) - fref = clk_in_26m(); - else - fref = clk_in_32k(); - - spctl0 = SPCTL0; - SPCTL0 = spctl0; - return imx_decode_pll(spctl0, fref); -} - -static ulong imx_decode_perclk(ulong div) -{ - return imx_get_mpllclk() / div; -} - -static ulong imx_get_nfcclk(void) -{ - ulong fref = imx_get_fclk(); - ulong div = ((PCDR0 >> 12) & 0xF) + 1; - return fref / div; -} - -ulong imx_get_perclk1(void) -{ - return imx_decode_perclk((PCDR1 & 0x3f) + 1); -} - -ulong imx_get_perclk2(void) -{ - return imx_decode_perclk(((PCDR1 >> 8) & 0x3f) + 1); -} - -ulong imx_get_perclk3(void) -{ - return imx_decode_perclk(((PCDR1 >> 16) & 0x3f) + 1); -} - -ulong imx_get_perclk4(void) -{ - return imx_decode_perclk(((PCDR1 >> 24) & 0x3f) + 1); -} - -ulong imx_get_uartclk(void) -{ - return imx_get_perclk1(); -} - -ulong imx_get_gptclk(void) -{ - return imx_decode_perclk((PCDR1 & 0x3f) + 1); -} - -ulong imx_get_lcdclk(void) -{ - return imx_get_perclk3(); -} - -void imx_dump_clocks(void) -{ - uint32_t cid = CID; - - printf("chip id: [%08x]\n", cid); - printf("mpll: %10ld Hz\n", imx_get_mpllclk()); - printf("spll: %10ld Hz\n", imx_get_spllclk()); - printf("arm: %10ld Hz\n", imx_get_armclk()); - printf("fclk: %10ld Hz\n", imx_get_fclk()); - printf("nfcclk: %10ld Hz\n", imx_get_nfcclk()); - printf("perclk1: %10ld Hz\n", imx_get_perclk1()); - printf("perclk2: %10ld Hz\n", imx_get_perclk2()); - printf("perclk3: %10ld Hz\n", imx_get_perclk3()); - printf("perclk4: %10ld Hz\n", imx_get_perclk4()); - printf("clkin26: %10ld Hz\n", clk_in_26m()); -} - -/* - * Set the divider of the CLKO pin (when CLK48DIV_CLKO is chosen). - * Returns the new divider (which may be smaller - * than the desired one) - */ -int imx_clko_set_div(int num, int div) -{ - ulong pcdr; - - if (num != 1) - return -ENODEV; - - div--; - div &= 0x7; - - pcdr = PCDR0 & ~(7 << 5); - pcdr |= div << 5; - PCDR0 = pcdr; - - return div + 1; -} - -/* - * Set the clock source for the CLKO pin - */ -void imx_clko_set_src(int num, int src) -{ - unsigned long ccsr; - - if (src < 0 || num != 1) { - return; - } - - ccsr = CCSR & ~0x1f; - ccsr |= src & 0x1f; - CCSR = ccsr; -} diff --git a/arch/arm/mach-imx/speed-imx25.c b/arch/arm/mach-imx/speed-imx25.c deleted file mode 100644 index 3c85713c4d..0000000000 --- a/arch/arm/mach-imx/speed-imx25.c +++ /dev/null @@ -1,155 +0,0 @@ -#include -#include -#include -#include -#include -#include - -unsigned long imx_get_mpllclk(void) -{ - ulong mpctl = readl(MX25_CCM_BASE_ADDR + CCM_MPCTL); - return imx_decode_pll(mpctl, CONFIG_MX25_HCLK_FREQ); -} - -unsigned long imx_get_upllclk(void) -{ - ulong ppctl = readl(MX25_CCM_BASE_ADDR + CCM_UPCTL); - return imx_decode_pll(ppctl, CONFIG_MX25_HCLK_FREQ); -} - -unsigned long imx_get_armclk(void) -{ - unsigned long rate, cctl; - - cctl = readl(MX25_CCM_BASE_ADDR + CCM_CCTL); - rate = imx_get_mpllclk(); - - if (cctl & (1 << 14)) { - rate *= 3; - rate >>= 2; - } - - return rate / ((cctl >> 30) + 1); -} - -unsigned long imx_get_ahbclk(void) -{ - ulong cctl = readl(MX25_CCM_BASE_ADDR + CCM_CCTL); - return imx_get_armclk() / (((cctl >> 28) & 0x3) + 1); -} - -unsigned long imx_get_ipgclk(void) -{ - return imx_get_ahbclk() / 2; -} - -unsigned long imx_get_gptclk(void) -{ - return imx_get_ipgclk(); -} - -unsigned long imx_get_perclk(int per) -{ - ulong ofs = (per & 0x3) * 8; - ulong reg = per & ~0x3; - ulong val = (readl(MX25_CCM_BASE_ADDR + CCM_PCDR0 + reg) >> ofs) & 0x3f; - ulong fref; - - if (readl(MX25_CCM_BASE_ADDR + 0x64) & (1 << per)) - fref = imx_get_upllclk(); - else - fref = imx_get_ahbclk(); - - return fref / (val + 1); -} - -unsigned long imx_get_uartclk(void) -{ - return imx_get_perclk(15); -} - -unsigned long imx_get_fecclk(void) -{ - return imx_get_ipgclk(); -} - -unsigned long imx_get_lcdclk(void) -{ - return imx_get_perclk(7); -} - -unsigned long fsl_get_i2cclk(void) -{ - return imx_get_perclk(6); -} - -unsigned long imx_get_mmcclk(void) -{ - return imx_get_perclk(3); -} - -unsigned long imx_get_cspiclk(void) -{ - return imx_get_ipgclk(); -} - -void imx_dump_clocks(void) -{ - printf("mpll: %10ld Hz\n", imx_get_mpllclk()); - printf("upll: %10ld Hz\n", imx_get_upllclk()); - printf("arm: %10ld Hz\n", imx_get_armclk()); - printf("ahb: %10ld Hz\n", imx_get_ahbclk()); - printf("uart: %10ld Hz\n", imx_get_perclk(15)); - printf("gpt: %10ld Hz\n", imx_get_ipgclk()); - printf("nand: %10ld Hz\n", imx_get_perclk(8)); - printf("lcd: %10ld Hz\n", imx_get_perclk(7)); - printf("i2c: %10ld Hz\n", imx_get_perclk(6)); - printf("sdhc1: %10ld Hz\n", imx_get_perclk(3)); -} - -/* - * Set the divider of the CLKO pin. Returns - * the new divider (which may be smaller - * than the desired one) - */ -int imx_clko_set_div(int num, int div) -{ - unsigned long mcr = readl(MX25_CCM_BASE_ADDR + 0x64); - - if (num != 1) - return -ENODEV; - - div -= 1; - div &= 0x3f; - - mcr &= ~(0x3f << 24); - mcr |= div << 24; - - writel(mcr, MX25_CCM_BASE_ADDR + 0x64); - - return div + 1; -} - -/* - * Set the clock source for the CLKO pin - */ -void imx_clko_set_src(int num, int src) -{ - unsigned long mcr = readl(MX25_CCM_BASE_ADDR + 0x64); - - if (num != 1) - return; - - if (src < 0) { - mcr &= ~(1 << 30); - writel(mcr, MX25_CCM_BASE_ADDR + 0x64); - return; - } - - mcr |= 1 << 30; - mcr &= ~(0xf << 20); - mcr |= (src & 0xf) << 20; - - writel(mcr, MX25_CCM_BASE_ADDR + 0x64); -} - diff --git a/arch/arm/mach-imx/speed-imx27.c b/arch/arm/mach-imx/speed-imx27.c deleted file mode 100644 index 33ec4487b6..0000000000 --- a/arch/arm/mach-imx/speed-imx27.c +++ /dev/null @@ -1,227 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include - -#ifndef CLK32 -#define CLK32 32000 -#endif - -static ulong clk_in_32k(void) -{ - return 1024 * CLK32; -} - -static ulong clk_in_26m(void) -{ - if (CSCR & CSCR_OSC26M_DIV1P5) { - /* divide by 1.5 */ - return 173333333; - } else { - /* divide by 1 */ - return 26000000; - } -} - -ulong imx_get_mpllclk(void) -{ - ulong cscr = CSCR; - ulong fref; - - if (cscr & CSCR_MCU_SEL) - fref = clk_in_26m(); - else - fref = clk_in_32k(); - - return imx_decode_pll(MPCTL0, fref); -} - -ulong imx_get_armclk(void) -{ - ulong cscr = CSCR; - ulong fref = imx_get_mpllclk(); - ulong div; - - if (!(cscr & CSCR_ARM_SRC_MPLL) && - (imx_silicon_revision() != IMX27_CHIP_REVISION_1_0)) - fref = (fref * 2) / 3; - - div = ((cscr >> 12) & 0x3) + 1; - - return fref / div; -} - -ulong imx_get_ahbclk(void) -{ - ulong cscr = CSCR; - ulong fref = imx_get_mpllclk(); - ulong div; - - if (imx_silicon_revision() == IMX27_CHIP_REVISION_1_0) - div = ((cscr >> 9) & 0xf) + 1; - else - div = ((cscr >> 8) & 0x3) + 1; - - return ((fref * 2) / 3) / div; -} - -ulong imx_get_ipgclk(void) -{ - ulong clk = imx_get_ahbclk(); - - return clk >> 1; -} - -ulong imx_get_fecclk(void) -{ - return imx_get_ipgclk(); -} - -ulong imx_get_spllclk(void) -{ - ulong cscr = CSCR; - ulong spctl0; - ulong fref; - - if (cscr & CSCR_SP_SEL) - fref = clk_in_26m(); - else - fref = clk_in_32k(); - - spctl0 = SPCTL0; - SPCTL0 = spctl0; - return imx_decode_pll(spctl0, fref); -} - -static ulong imx_decode_perclk(ulong div) -{ - if (imx_silicon_revision() == IMX27_CHIP_REVISION_1_0) - return imx_get_mpllclk() / div; - else - return (imx_get_mpllclk() * 2) / (div * 3); -} - -ulong imx_get_perclk1(void) -{ - return imx_decode_perclk((PCDR1 & 0x3f) + 1); -} - -ulong imx_get_perclk2(void) -{ - return imx_decode_perclk(((PCDR1 >> 8) & 0x3f) + 1); -} - -ulong imx_get_perclk3(void) -{ - return imx_decode_perclk(((PCDR1 >> 16) & 0x3f) + 1); -} - -ulong imx_get_perclk4(void) -{ - return imx_decode_perclk(((PCDR1 >> 24) & 0x3f) + 1); -} - -ulong imx_get_uartclk(void) -{ - return imx_get_perclk1(); -} - -ulong imx_get_gptclk(void) -{ - return imx_decode_perclk((PCDR1 & 0x3f) + 1); -} - -ulong imx_get_lcdclk(void) -{ - return imx_get_perclk3(); -} - -ulong fsl_get_i2cclk(void) -{ - return imx_get_ipgclk(); -} - -ulong imx_get_mmcclk(void) -{ - return imx_get_perclk2(); -} - -void imx_dump_clocks(void) -{ - uint32_t cid = CID; - - printf("chip id: [%d,%03x,%d,%03x]\n", - (cid >> 28) & 0xf, (cid >> 16) & 0xfff, - (cid >> 12) & 0xf, (cid >> 0) & 0xfff); - - printf("mpll: %10ld Hz\n", imx_get_mpllclk()); - printf("spll: %10ld Hz\n", imx_get_spllclk()); - printf("arm: %10ld Hz\n", imx_get_armclk()); - printf("perclk1: %10ld Hz\n", imx_get_perclk1()); - printf("perclk2: %10ld Hz\n", imx_get_perclk2()); - printf("perclk3: %10ld Hz\n", imx_get_perclk3()); - printf("perclk4: %10ld Hz\n", imx_get_perclk4()); - printf("clkin26: %10ld Hz\n", clk_in_26m()); - printf("ahb: %10ld Hz\n", imx_get_ahbclk()); - printf("ipg: %10ld Hz\n", imx_get_ipgclk()); -} - -/* - * Set the divider of the CLKO pin. Returns - * the new divider (which may be smaller - * than the desired one) - */ -int imx_clko_set_div(int num, int div) -{ - ulong pcdr; - - if (num != 1) - return -ENODEV; - - div--; - div &= 0x7; - - pcdr = PCDR0 & ~(7 << 22); - pcdr |= div << 22; - PCDR0 = pcdr; - - return div + 1; -} - -/* - * Set the clock source for the CLKO pin - */ -void imx_clko_set_src(int num, int src) -{ - unsigned long ccsr; - - if (num != 1) - return; - - if (src < 0) { - PCDR0 &= ~(1 << 25); - return; - } - - ccsr = CCSR & ~0x1f; - ccsr |= src & 0x1f; - CCSR = ccsr; - - PCDR0 |= (1 << 25); -} - diff --git a/arch/arm/mach-imx/speed-imx31.c b/arch/arm/mach-imx/speed-imx31.c deleted file mode 100644 index f8f73c18b1..0000000000 --- a/arch/arm/mach-imx/speed-imx31.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include - -ulong imx_get_mpl_dpdgck_clk(void) -{ - ulong infreq; - - if ((readl(MX31_CCM_BASE_ADDR + CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM) - infreq = CONFIG_MX31_CLK32 * 1024; - else - infreq = CONFIG_MX31_HCLK_FREQ; - - return imx_decode_pll(readl(MX31_CCM_BASE_ADDR + CCM_MPCTL), infreq); -} - -ulong imx_get_mcu_main_clk(void) -{ - /* For now we assume mpl_dpdgck_clk == mcu_main_clk - * which should be correct for most boards - */ - return imx_get_mpl_dpdgck_clk(); -} - -/** - * Calculate the current pixel clock speed (aka HSP or IPU) - * @return 0 on failure or current frequency in Hz - */ -ulong imx_get_lcdclk(void) -{ - ulong hsp_podf = (readl(MX31_CCM_BASE_ADDR + CCM_PDR0) >> 11) & 0x03; - ulong base_clk = imx_get_mcu_main_clk(); - - return base_clk / (hsp_podf + 1); -} - -ulong imx_get_perclk1(void) -{ - u32 freq = imx_get_mcu_main_clk(); - u32 pdr0 = readl(MX31_CCM_BASE_ADDR + CCM_PDR0); - - freq /= ((pdr0 >> 3) & 0x7) + 1; - freq /= ((pdr0 >> 6) & 0x3) + 1; - - return freq; -} - -void imx_dump_clocks(void) -{ - ulong cpufreq = imx_get_mcu_main_clk(); - printf("mx31 cpu clock: %ldMHz\n",cpufreq / 1000000); - printf("ipg clock : %ldHz\n", imx_get_perclk1()); -} - -ulong imx_get_uartclk(void) -{ - return imx_get_perclk1(); -} - -ulong imx_get_gptclk(void) -{ - return imx_get_perclk1(); -} - diff --git a/arch/arm/mach-imx/speed-imx35.c b/arch/arm/mach-imx/speed-imx35.c deleted file mode 100644 index a8063f20b3..0000000000 --- a/arch/arm/mach-imx/speed-imx35.c +++ /dev/null @@ -1,255 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include - -unsigned long imx_get_mpllclk(void) -{ - ulong mpctl = readl(MX35_CCM_BASE_ADDR + CCM_MPCTL); - return imx_decode_pll(mpctl, CONFIG_MX35_HCLK_FREQ); -} - -static unsigned long imx_get_ppllclk(void) -{ - ulong ppctl = readl(MX35_CCM_BASE_ADDR + CCM_PPCTL); - return imx_decode_pll(ppctl, CONFIG_MX35_HCLK_FREQ); -} - -struct arm_ahb_div { - unsigned char arm, ahb, sel; -}; - -static struct arm_ahb_div clk_consumer[] = { - { .arm = 1, .ahb = 4, .sel = 0}, - { .arm = 1, .ahb = 3, .sel = 1}, - { .arm = 2, .ahb = 2, .sel = 0}, - { .arm = 0, .ahb = 0, .sel = 0}, - { .arm = 0, .ahb = 0, .sel = 0}, - { .arm = 0, .ahb = 0, .sel = 0}, - { .arm = 4, .ahb = 1, .sel = 0}, - { .arm = 1, .ahb = 5, .sel = 0}, - { .arm = 1, .ahb = 8, .sel = 0}, - { .arm = 1, .ahb = 6, .sel = 1}, - { .arm = 2, .ahb = 4, .sel = 0}, - { .arm = 0, .ahb = 0, .sel = 0}, - { .arm = 0, .ahb = 0, .sel = 0}, - { .arm = 0, .ahb = 0, .sel = 0}, - { .arm = 4, .ahb = 2, .sel = 0}, - { .arm = 0, .ahb = 0, .sel = 0}, -}; - -static unsigned long imx_get_armclk(void) -{ - unsigned long pdr0 = readl(MX35_CCM_BASE_ADDR + CCM_PDR0); - struct arm_ahb_div *aad; - unsigned long fref = imx_get_mpllclk(); - - /* consumer path is selected */ - aad = &clk_consumer[(pdr0 >> 16) & 0xf]; - if (aad->sel) - fref = fref * 3 / 4; - - return fref / aad->arm; -} - -unsigned long imx_get_ahbclk(void) -{ - unsigned long pdr0 = readl(MX35_CCM_BASE_ADDR + CCM_PDR0); - struct arm_ahb_div *aad; - unsigned long fref = imx_get_mpllclk(); - - aad = &clk_consumer[(pdr0 >> 16) & 0xf]; - if (aad->sel) - fref = fref * 3 / 4; - - return fref / aad->ahb; -} - -unsigned long imx_get_ipgclk(void) -{ - ulong clk = imx_get_ahbclk(); - - return clk >> 1; -} - -static unsigned long get_3_3_div(unsigned long in) -{ - return (((in >> 3) & 0x7) + 1) * ((in & 0x7) + 1); -} - -static unsigned long get_6_div(unsigned long in) -{ - return ((in & 0x3f) + 1); -} - -static unsigned long imx_get_ipg_perclk(void) -{ - ulong pdr0 = readl(MX35_CCM_BASE_ADDR + CCM_PDR0); - ulong pdr4 = readl(MX35_CCM_BASE_ADDR + CCM_PDR4); - ulong div; - ulong fref; - - if (pdr0 & PDR0_PER_SEL) { - /* perclk from arm high frequency clock and synched with AHB clki */ - fref = imx_get_armclk(); - div = get_3_3_div((pdr4 >> 16)); - } else { - /* perclk from AHB divided clock */ - fref = imx_get_ahbclk(); - div = ((pdr0 >> 12) & 0x7) + 1; - } - - return fref / div; -} - -unsigned long imx_get_gptclk(void) -{ - return imx_get_ipgclk(); -} - -/** - * Calculate the current pixel clock speed (aka HSP or IPU) - * @return 0 on failure or current frequency in Hz - */ -unsigned long imx_get_lcdclk(void) -{ - unsigned long hsp_podf = (readl(MX35_CCM_BASE_ADDR + CCM_PDR0) >> 20) & 0x03; - unsigned long base_clk = imx_get_armclk(); - - if (base_clk > 400 * 1000 * 1000) { - switch(hsp_podf) { - case 0: - return base_clk >> 2; - case 1: - return base_clk >> 3; - case 2: - return base_clk / 3; - } - } else { - switch(hsp_podf) { - case 0: - case 2: - return base_clk / 3; - case 1: - return base_clk / 6; - } - } - - return 0; -} - -unsigned long imx_get_uartclk(void) -{ - unsigned long pdr3 = readl(MX35_CCM_BASE_ADDR + CCM_PDR3); - unsigned long pdr4 = readl(MX35_CCM_BASE_ADDR + CCM_PDR4); - unsigned long div = get_3_3_div(pdr4 >> 10); - - if (pdr3 & (1 << 14)) - return imx_get_armclk() / div; - else - return imx_get_ppllclk() / div; -} - -/* mmc0 clk only */ -unsigned long imx_get_mmcclk(void) -{ - unsigned long pdr3 = readl(MX35_CCM_BASE_ADDR + CCM_PDR3); - unsigned long div = get_6_div(pdr3); - - if (pdr3 & (1 << 6)) - return imx_get_armclk() / div; - else - return imx_get_ppllclk() / div; -} - -ulong imx_get_fecclk(void) -{ - return imx_get_ipgclk(); -} - -ulong fsl_get_i2cclk(void) -{ - return imx_get_ipg_perclk(); -} - -unsigned long imx_get_cspiclk(void) -{ - return imx_get_ipgclk(); -} - -void imx_dump_clocks(void) -{ - printf("mpll: %10ld Hz\n", imx_get_mpllclk()); - printf("ppll: %10ld Hz\n", imx_get_ppllclk()); - printf("arm: %10ld Hz\n", imx_get_armclk()); - printf("gpt: %10ld Hz\n", imx_get_gptclk()); - printf("ahb: %10ld Hz\n", imx_get_ahbclk()); - printf("ipg: %10ld Hz\n", imx_get_ipgclk()); - printf("ipg_per: %10ld Hz\n", imx_get_ipg_perclk()); - printf("uart: %10ld Hz\n", imx_get_uartclk()); - printf("sdhc1: %10ld Hz\n", imx_get_mmcclk()); -} - -/* - * Set the divider of the CLKO pin. Returns - * the new divider (which may be smaller - * than the desired one) - */ -int imx_clko_set_div(int num, int div) -{ - unsigned long cosr = readl(MX35_CCM_BASE_ADDR + CCM_COSR); - - if (num != 1) - return -ENODEV; - - div -= 1; - div &= 0x3f; - - cosr &= ~(0x3f << 10); - cosr |= div << 10; - - writel(cosr, MX35_CCM_BASE_ADDR + CCM_COSR); - - return div + 1; -} - -/* - * Set the clock source for the CLKO pin - */ -void imx_clko_set_src(int num, int src) -{ - unsigned long cosr = readl(MX35_CCM_BASE_ADDR + CCM_COSR); - - if (num != 1) - return; - - if (src < 0) { - cosr &= ~(1 << 5); - writel(cosr, MX35_CCM_BASE_ADDR + CCM_COSR); - return; - } - - cosr |= 1 << 5; - cosr &= ~0x1f; - cosr &= ~(1 << 6); - cosr |= src & 0x1f; - - writel(cosr, MX35_CCM_BASE_ADDR + CCM_COSR); -} - diff --git a/arch/arm/mach-imx/speed-imx51.c b/arch/arm/mach-imx/speed-imx51.c deleted file mode 100644 index 3903afc821..0000000000 --- a/arch/arm/mach-imx/speed-imx51.c +++ /dev/null @@ -1,311 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include - -static u32 ccm_readl(u32 ofs) -{ - return readl(IOMEM(MX51_CCM_BASE_ADDR) + ofs); -} - -static void ccm_writel(u32 val, u32 ofs) -{ - writel(val, MX51_CCM_BASE_ADDR + ofs); -} - -static unsigned long ckil_get_rate(void) -{ - return 32768; -} - -static unsigned long osc_get_rate(void) -{ - return 24000000; -} - -static unsigned long fpm_get_rate(void) -{ - return ckil_get_rate() * 512; -} - -static unsigned long lp_apm_get_rate(void) -{ - if (ccm_readl(MX5_CCM_CCSR) & MX5_CCM_CCSR_LP_APM_SEL) - return fpm_get_rate(); - else - return osc_get_rate(); -} - -static unsigned long pll_get_rate(void __iomem *pllbase) -{ - long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; - unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl; - u64 temp; - unsigned long parent_rate; - - dp_ctl = readl(pllbase + MX5_PLL_DP_CTL); - - if ((dp_ctl & MX5_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0) - parent_rate = fpm_get_rate(); - else - parent_rate = osc_get_rate(); - - pll_hfsm = dp_ctl & MX5_PLL_DP_CTL_HFSM; - dbl = dp_ctl & MX5_PLL_DP_CTL_DPDCK0_2_EN; - - if (pll_hfsm == 0) { - dp_op = readl(pllbase + MX5_PLL_DP_OP); - dp_mfd = readl(pllbase + MX5_PLL_DP_MFD); - dp_mfn = readl(pllbase + MX5_PLL_DP_MFN); - } else { - dp_op = readl(pllbase + MX5_PLL_DP_HFS_OP); - dp_mfd = readl(pllbase + MX5_PLL_DP_HFS_MFD); - dp_mfn = readl(pllbase + MX5_PLL_DP_HFS_MFN); - } - pdf = dp_op & MX5_PLL_DP_OP_PDF_MASK; - mfi = (dp_op & MX5_PLL_DP_OP_MFI_MASK) >> MX5_PLL_DP_OP_MFI_OFFSET; - mfi = (mfi <= 5) ? 5 : mfi; - mfd = dp_mfd & MX5_PLL_DP_MFD_MASK; - mfn = mfn_abs = dp_mfn & MX5_PLL_DP_MFN_MASK; - /* Sign extend to 32-bits */ - if (mfn >= 0x04000000) { - mfn |= 0xFC000000; - mfn_abs = -mfn; - } - - ref_clk = 2 * parent_rate; - if (dbl != 0) - ref_clk *= 2; - - ref_clk /= (pdf + 1); - temp = (u64)ref_clk * mfn_abs; - do_div(temp, mfd + 1); - if (mfn < 0) - temp = -temp; - temp = (ref_clk * mfi) + temp; - - return temp; -} - -static unsigned long pll1_main_get_rate(void) -{ - return pll_get_rate((void __iomem *)MX51_PLL1_BASE_ADDR); -} - -static unsigned long pll2_sw_get_rate(void) -{ - return pll_get_rate((void __iomem *)MX51_PLL2_BASE_ADDR); -} - -static unsigned long pll3_sw_get_rate(void) -{ - return pll_get_rate((void __iomem *)MX51_PLL3_BASE_ADDR); -} - -static unsigned long get_rate_select(int select, - unsigned long (* get_rate1)(void), - unsigned long (* get_rate2)(void), - unsigned long (* get_rate3)(void), - unsigned long (* get_rate4)(void)) -{ - switch (select) { - case 0: - return get_rate1 ? get_rate1() : 0; - case 1: - return get_rate2 ? get_rate2() : 0; - case 2: - return get_rate3 ? get_rate3() : 0; - case 3: - return get_rate4 ? get_rate4() : 0; - } - - return 0; -} - -unsigned long imx_get_uartclk(void) -{ - u32 reg, prediv, podf; - unsigned long parent_rate; - - reg = ccm_readl(MX5_CCM_CSCMR1); - reg &= MX5_CCM_CSCMR1_UART_CLK_SEL_MASK; - reg >>= MX5_CCM_CSCMR1_UART_CLK_SEL_OFFSET; - - parent_rate = get_rate_select(reg, - pll1_main_get_rate, - pll2_sw_get_rate, - pll3_sw_get_rate, - lp_apm_get_rate); - - reg = ccm_readl(MX5_CCM_CSCDR1); - prediv = ((reg & MX5_CCM_CSCDR1_UART_CLK_PRED_MASK) >> - MX5_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1; - podf = ((reg & MX5_CCM_CSCDR1_UART_CLK_PODF_MASK) >> - MX5_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1; - - return parent_rate / (prediv * podf); -} - -unsigned long imx_get_ahbclk(void) -{ - u32 reg, div; - - reg = ccm_readl(MX5_CCM_CBCDR); - div = ((reg >> 10) & 0x7) + 1; - - return pll2_sw_get_rate() / div; -} - -unsigned long imx_get_ipgclk(void) -{ - u32 reg, div; - - reg = ccm_readl(MX5_CCM_CBCDR); - div = ((reg >> 8) & 0x3) + 1; - - return imx_get_ahbclk() / div; -} - -unsigned long imx_get_gptclk(void) -{ - return imx_get_ipgclk(); -} - -unsigned long imx_get_fecclk(void) -{ - return imx_get_ipgclk(); -} - -unsigned long fsl_get_i2cclk(void) -{ - return imx_get_ipgclk(); -} - -unsigned long imx_get_mmcclk(void) -{ - u32 reg, prediv, podf, rate; - - reg = ccm_readl(MX5_CCM_CSCMR1); - reg &= MX5_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK; - reg >>= MX5_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET; - rate = get_rate_select(reg, - pll1_main_get_rate, - pll2_sw_get_rate, - pll3_sw_get_rate, - lp_apm_get_rate); - - reg = ccm_readl(MX5_CCM_CSCDR1); - prediv = ((reg & MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK) >> - MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET) + 1; - podf = ((reg & MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK) >> - MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET) + 1; - - return rate / (prediv * podf); -} - -unsigned long imx_get_usbclk(void) -{ - u32 reg, prediv, podf, rate; - - reg = ccm_readl(MX5_CCM_CSCMR1); - reg &= MX5_CCM_CSCMR1_USBOH3_CLK_SEL_MASK; - reg >>= MX5_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET; - rate = get_rate_select(reg, - pll1_main_get_rate, - pll2_sw_get_rate, - pll3_sw_get_rate, - lp_apm_get_rate); - - reg = ccm_readl(MX5_CCM_CSCDR1); - prediv = ((reg & MX5_CCM_CSCDR1_USBOH3_CLK_PRED_MASK) >> - MX5_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET) + 1; - podf = ((reg & MX5_CCM_CSCDR1_USBOH3_CLK_PODF_MASK) >> - MX5_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET) + 1; - - return rate / (prediv * podf); -} - -unsigned long imx_get_cspiclk(void) -{ - return 166000000; /* FIXME: bogus value */ -} - -/* - * Set the divider of the CLKO pin. Returns - * the new divider (which may be smaller - * than the desired one) - */ -int imx_clko_set_div(int num, int div) -{ - u32 ccosr = ccm_readl(MX5_CCM_CCOSR); - - div--; - - switch (num) { - case 1: - div &= 0x7; - ccosr &= ~(0x7 << 4); - ccosr |= div << 4; - ccm_writel(ccosr, MX5_CCM_CCOSR); - break; - case 2: - div &= 0x7; - ccosr &= ~(0x7 << 21); - ccosr |= div << 21; - ccm_writel(ccosr, MX5_CCM_CCOSR); - break; - default: - return -ENODEV; - } - - return div + 1; -} - -/* - * Set the clock source for the CLKO pin - */ -void imx_clko_set_src(int num, int src) -{ - u32 ccosr = ccm_readl(MX5_CCM_CCOSR); - - switch (num) { - case 1: - if (src < 0) { - ccosr &= ~(1 << 7); - break; - } - ccosr &= ~0xf; - ccosr |= src & 0xf; - ccosr |= 1 << 7; - break; - case 2: - if (src < 0) { - ccosr &= ~(1 << 24); - break; - } - ccosr &= ~(0x1f << 16); - ccosr |= (src & 0x1f) << 16; - ccosr |= 1 << 24; - break; - default: - return; - } - - ccm_writel(ccosr, MX5_CCM_CCOSR); -} - -void imx_dump_clocks(void) -{ - printf("pll1: %ld\n", pll1_main_get_rate()); - printf("pll2: %ld\n", pll2_sw_get_rate()); - printf("pll3: %ld\n", pll3_sw_get_rate()); - printf("lp_apm: %ld\n", lp_apm_get_rate()); - printf("uart: %ld\n", imx_get_uartclk()); - printf("ipg: %ld\n", imx_get_ipgclk()); - printf("fec: %ld\n", imx_get_fecclk()); - printf("gpt: %ld\n", imx_get_gptclk()); - printf("usb: %ld\n", imx_get_usbclk()); -} diff --git a/arch/arm/mach-imx/speed-imx53.c b/arch/arm/mach-imx/speed-imx53.c deleted file mode 100644 index b1ba5fd1d2..0000000000 --- a/arch/arm/mach-imx/speed-imx53.c +++ /dev/null @@ -1,236 +0,0 @@ -#include -#include -#include -#include -#include -#include "mach/clock-imx51_53.h" - -static u32 ccm_readl(u32 ofs) -{ - return readl(MX53_CCM_BASE_ADDR + ofs); -} - -static unsigned long ckil_get_rate(void) -{ - return 32768; -} - -static unsigned long osc_get_rate(void) -{ - return 24000000; -} - -static unsigned long fpm_get_rate(void) -{ - return ckil_get_rate() * 512; -} - -static unsigned long pll_get_rate(void __iomem *pllbase) -{ - long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; - unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl; - u64 temp; - unsigned long parent_rate; - - dp_ctl = readl(pllbase + MX5_PLL_DP_CTL); - - if ((dp_ctl & MX5_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0) - parent_rate = fpm_get_rate(); - else - parent_rate = osc_get_rate(); - - pll_hfsm = dp_ctl & MX5_PLL_DP_CTL_HFSM; - dbl = dp_ctl & MX5_PLL_DP_CTL_DPDCK0_2_EN; - - if (pll_hfsm == 0) { - dp_op = readl(pllbase + MX5_PLL_DP_OP); - dp_mfd = readl(pllbase + MX5_PLL_DP_MFD); - dp_mfn = readl(pllbase + MX5_PLL_DP_MFN); - } else { - dp_op = readl(pllbase + MX5_PLL_DP_HFS_OP); - dp_mfd = readl(pllbase + MX5_PLL_DP_HFS_MFD); - dp_mfn = readl(pllbase + MX5_PLL_DP_HFS_MFN); - } - pdf = dp_op & MX5_PLL_DP_OP_PDF_MASK; - mfi = (dp_op & MX5_PLL_DP_OP_MFI_MASK) >> MX5_PLL_DP_OP_MFI_OFFSET; - mfi = (mfi <= 5) ? 5 : mfi; - mfd = dp_mfd & MX5_PLL_DP_MFD_MASK; - mfn = mfn_abs = dp_mfn & MX5_PLL_DP_MFN_MASK; - /* Sign extend to 32-bits */ - if (mfn >= 0x04000000) { - mfn |= 0xFC000000; - mfn_abs = -mfn; - } - - ref_clk = 2 * parent_rate; - if (dbl != 0) - ref_clk *= 2; - - ref_clk /= (pdf + 1); - temp = (u64)ref_clk * mfn_abs; - do_div(temp, mfd + 1); - if (mfn < 0) - temp = -temp; - temp = (ref_clk * mfi) + temp; - - return temp; -} - -static unsigned long pll1_main_get_rate(void) -{ - return pll_get_rate((void __iomem *)MX53_PLL1_BASE_ADDR); -} - -static unsigned long pll2_sw_get_rate(void) -{ - return pll_get_rate((void __iomem *)MX53_PLL2_BASE_ADDR); -} - -static unsigned long pll3_sw_get_rate(void) -{ - return pll_get_rate((void __iomem *)MX53_PLL3_BASE_ADDR); -} - -static unsigned long pll4_sw_get_rate(void) -{ - return pll_get_rate((void __iomem *)MX53_PLL4_BASE_ADDR); -} - -static unsigned long get_rate_select(int select, - unsigned long (* get_rate1)(void), - unsigned long (* get_rate2)(void), - unsigned long (* get_rate3)(void), - unsigned long (* get_rate4)(void)) -{ - switch (select) { - case 0: - return get_rate1 ? get_rate1() : 0; - case 1: - return get_rate2 ? get_rate2() : 0; - case 2: - return get_rate3 ? get_rate3() : 0; - case 3: - return get_rate4 ? get_rate4() : 0; - } - - return 0; -} - -unsigned long imx_get_uartclk(void) -{ - u32 reg, prediv, podf; - unsigned long parent_rate; - - reg = ccm_readl(MX5_CCM_CSCMR1); - reg &= MX5_CCM_CSCMR1_UART_CLK_SEL_MASK; - reg >>= MX5_CCM_CSCMR1_UART_CLK_SEL_OFFSET; - - parent_rate = get_rate_select(reg, - pll1_main_get_rate, - pll2_sw_get_rate, - pll3_sw_get_rate, - pll4_sw_get_rate); - - reg = ccm_readl(MX5_CCM_CSCDR1); - prediv = ((reg & MX5_CCM_CSCDR1_UART_CLK_PRED_MASK) >> - MX5_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1; - podf = ((reg & MX5_CCM_CSCDR1_UART_CLK_PODF_MASK) >> - MX5_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1; - - return parent_rate / (prediv * podf); -} - -unsigned long imx_get_ahbclk(void) -{ - u32 reg, div; - - reg = ccm_readl(MX5_CCM_CBCDR); - div = ((reg >> 10) & 0x7) + 1; - - return pll2_sw_get_rate() / div; -} - -unsigned long imx_get_ipgclk(void) -{ - u32 reg, div; - - reg = ccm_readl(MX5_CCM_CBCDR); - div = ((reg >> 8) & 0x3) + 1; - - return imx_get_ahbclk() / div; -} - -unsigned long imx_get_gptclk(void) -{ - return imx_get_ipgclk(); -} - -unsigned long imx_get_fecclk(void) -{ - return imx_get_ipgclk(); -} - -static unsigned long imx_get_ipg_perclk(void) -{ - u32 reg; - - reg = ccm_readl(MX5_CCM_CBCDR); - if (!(reg & MX5_CCM_CBCDR_PERIPH_CLK_SEL)) - return pll2_sw_get_rate(); - reg = ccm_readl(MX5_CCM_CBCMR); - switch ((reg & MX5_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >> - MX5_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) { - case 0: - return pll1_main_get_rate(); - case 1: - return pll3_sw_get_rate(); - /* case 2: - TODO : LP_APM */ - } - return 0; -} - -unsigned long fsl_get_i2cclk(void) -{ - return imx_get_ipg_perclk(); -} - -unsigned long imx_get_mmcclk(void) -{ - u32 reg, prediv, podf, rate; - - reg = ccm_readl(MX5_CCM_CSCMR1); - reg &= MX5_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK; - reg >>= MX5_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET; - rate = get_rate_select(reg, - pll1_main_get_rate, - pll2_sw_get_rate, - pll3_sw_get_rate, - pll4_sw_get_rate); - - reg = ccm_readl(MX5_CCM_CSCDR1); - prediv = ((reg & MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK) >> - MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET) + 1; - podf = ((reg & MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK) >> - MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET) + 1; - - return rate / (prediv * podf); -} - -unsigned long imx_get_cspiclk(void) -{ - return 166000000; /* FIXME: bogus value */ -} - -void imx_dump_clocks(void) -{ - printf("pll1: %ld\n", pll1_main_get_rate()); - printf("pll2: %ld\n", pll2_sw_get_rate()); - printf("pll3: %ld\n", pll3_sw_get_rate()); - printf("pll4: %ld\n", pll4_sw_get_rate()); - printf("uart: %ld\n", imx_get_uartclk()); - printf("ipg: %ld\n", imx_get_ipgclk()); - printf("fec: %ld\n", imx_get_fecclk()); - printf("gpt: %ld\n", imx_get_gptclk()); - printf("i2c: %ld\n", fsl_get_i2cclk()); -} diff --git a/arch/arm/mach-imx/speed-imx6.c b/arch/arm/mach-imx/speed-imx6.c deleted file mode 100644 index 645b2c9735..0000000000 --- a/arch/arm/mach-imx/speed-imx6.c +++ /dev/null @@ -1,404 +0,0 @@ -#include -#include -#include -#include -#include -#include - -enum pll_clocks { - CPU_PLL1, /* System PLL */ - BUS_PLL2, /* System Bus PLL*/ - USBOTG_PLL3, /* OTG USB PLL */ - AUD_PLL4, /* Audio PLL */ - VID_PLL5, /* Video PLL */ - MLB_PLL6, /* MLB PLL */ - USBHOST_PLL7, /* Host USB PLL */ - ENET_PLL8, /* ENET PLL */ -}; - -#define SZ_DEC_1M 1000000 - -/* Out-of-reset PFDs and clock source definitions */ -#define PLL2_PFD0_FREQ 352000000 -#define PLL2_PFD1_FREQ 594000000 -#define PLL2_PFD2_FREQ 400000000 -#define PLL2_PFD2_DIV_FREQ 200000000 -#define PLL3_PFD0_FREQ 720000000 -#define PLL3_PFD1_FREQ 540000000 -#define PLL3_PFD2_FREQ 508200000 -#define PLL3_PFD3_FREQ 454700000 -#define PLL3_80M 80000000 -#define PLL3_60M 60000000 - -#define AHB_CLK_ROOT 132000000 -#define IPG_CLK_ROOT 66000000 -#define ENET_FREQ_0 25000000 -#define ENET_FREQ_1 50000000 -#define ENET_FREQ_2 100000000 -#define ENET_FREQ_3 125000000 - -#define CONFIG_MX6_HCLK_FREQ 24000000 - -static u32 __decode_pll(enum pll_clocks pll, u32 infreq) -{ - u32 div; - - switch (pll) { - case CPU_PLL1: - div = readl(MX6_ANATOP_BASE_ADDR + HW_ANADIG_PLL_SYS) & - BM_ANADIG_PLL_SYS_DIV_SELECT; - return infreq * (div >> 1); - case BUS_PLL2: - div = readl(MX6_ANATOP_BASE_ADDR + HW_ANADIG_PLL_528) & - BM_ANADIG_PLL_528_DIV_SELECT; - return infreq * (20 + (div << 1)); - case USBOTG_PLL3: - div = readl(MX6_ANATOP_BASE_ADDR + HW_ANADIG_USB2_PLL_480_CTRL) & - BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT; - return infreq * (20 + (div << 1)); - case ENET_PLL8: - div = readl(MX6_ANATOP_BASE_ADDR + HW_ANADIG_PLL_ENET) & - BM_ANADIG_PLL_ENET_DIV_SELECT; - switch (div) { - default: - case 0: - return ENET_FREQ_0; - case 1: - return ENET_FREQ_1; - case 2: - return ENET_FREQ_2; - case 3: - return ENET_FREQ_3; - } - case AUD_PLL4: - case VID_PLL5: - case MLB_PLL6: - case USBHOST_PLL7: - default: - return 0; - } -} - -static u32 __get_mcu_main_clk(void) -{ - u32 reg, freq; - reg = (__REG(MXC_CCM_CACRR) & MXC_CCM_CACRR_ARM_PODF_MASK) >> - MXC_CCM_CACRR_ARM_PODF_OFFSET; - freq = __decode_pll(CPU_PLL1, CONFIG_MX6_HCLK_FREQ); - return freq / (reg + 1); -} - -static u32 __get_periph_clk(void) -{ - u32 reg; - reg = __REG(MXC_CCM_CBCDR); - if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) { - reg = __REG(MXC_CCM_CBCMR); - switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK) >> - MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET) { - case 0: - return __decode_pll(USBOTG_PLL3, CONFIG_MX6_HCLK_FREQ); - case 1: - case 2: - return CONFIG_MX6_HCLK_FREQ; - default: - return 0; - } - } else { - reg = __REG(MXC_CCM_CBCMR); - switch ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) >> - MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET) { - default: - case 0: - return __decode_pll(BUS_PLL2, CONFIG_MX6_HCLK_FREQ); - case 1: - return PLL2_PFD2_FREQ; - case 2: - return PLL2_PFD0_FREQ; - case 3: - return PLL2_PFD2_DIV_FREQ; - } - } -} - -static u32 __get_ipg_clk(void) -{ - u32 ahb_podf, ipg_podf; - - ahb_podf = __REG(MXC_CCM_CBCDR); - ipg_podf = (ahb_podf & MXC_CCM_CBCDR_IPG_PODF_MASK) >> - MXC_CCM_CBCDR_IPG_PODF_OFFSET; - ahb_podf = (ahb_podf & MXC_CCM_CBCDR_AHB_PODF_MASK) >> - MXC_CCM_CBCDR_AHB_PODF_OFFSET; - return __get_periph_clk() / ((ahb_podf + 1) * (ipg_podf + 1)); -} - -u32 imx_get_gptclk(void) -{ - return __get_ipg_clk(); -} - -static u32 __get_ipg_per_clk(void) -{ - u32 podf; - u32 clk_root = __get_ipg_clk(); - - podf = __REG(MXC_CCM_CSCMR1) & MXC_CCM_CSCMR1_PERCLK_PODF_MASK; - return clk_root / (podf + 1); -} - -u32 imx_get_uartclk(void) -{ - u32 freq = PLL3_80M, reg, podf; - - reg = __REG(MXC_CCM_CSCDR1); - podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >> - MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET; - freq /= (podf + 1); - - return freq; -} - -static u32 __get_cspi_clk(void) -{ - u32 freq = PLL3_60M, reg, podf; - - reg = __REG(MXC_CCM_CSCDR2); - podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >> - MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET; - freq /= (podf + 1); - - return freq; -} - -static u32 __get_axi_clk(void) -{ - u32 clkroot; - u32 cbcdr = __REG(MXC_CCM_CBCDR); - u32 podf = (cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK) >> - MXC_CCM_CBCDR_AXI_PODF_OFFSET; - - if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { - if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) - clkroot = PLL2_PFD2_FREQ; - else - clkroot = PLL3_PFD1_FREQ;; - } else - clkroot = __get_periph_clk(); - - return clkroot / (podf + 1); -} - -static u32 __get_ahb_clk(void) -{ - u32 cbcdr = __REG(MXC_CCM_CBCDR); - u32 podf = (cbcdr & MXC_CCM_CBCDR_AHB_PODF_MASK) \ - >> MXC_CCM_CBCDR_AHB_PODF_OFFSET; - - return __get_periph_clk() / (podf + 1); -} - -static u32 __get_emi_slow_clk(void) -{ - u32 cscmr1 = __REG(MXC_CCM_CSCMR1); - u32 emi_clk_sel = (cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK) >> - MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET; - u32 podf = (cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK) >> - MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET; - - switch (emi_clk_sel) { - default: - case 0: - return __get_axi_clk() / (podf + 1); - case 1: - return __decode_pll(USBOTG_PLL3, CONFIG_MX6_HCLK_FREQ) / - (podf + 1); - case 2: - return PLL2_PFD2_FREQ / (podf + 1); - case 3: - return PLL2_PFD0_FREQ / (podf + 1); - } -} - -static u32 __get_nfc_clk(void) -{ - u32 clkroot; - u32 cs2cdr = __REG(MXC_CCM_CS2CDR); - u32 podf = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK) \ - >> MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET; - u32 pred = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK) \ - >> MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET; - - switch ((cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK) >> - MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET) { - default: - case 0: - clkroot = PLL2_PFD0_FREQ; - break; - case 1: - clkroot = __decode_pll(BUS_PLL2, CONFIG_MX6_HCLK_FREQ); - break; - case 2: - clkroot = __decode_pll(USBOTG_PLL3, CONFIG_MX6_HCLK_FREQ); - break; - case 3: - clkroot = PLL2_PFD2_FREQ; - break; - } - - return clkroot / (pred+1) / (podf+1); -} - -static u32 __get_ddr_clk(void) -{ - u32 cbcdr = __REG(MXC_CCM_CBCDR); - u32 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >> - MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET; - - return __get_periph_clk() / (podf + 1); -} - -static u32 __get_usdhc1_clk(void) -{ - u32 clkroot; - u32 cscmr1 = __REG(MXC_CCM_CSCMR1); - u32 cscdr1 = __REG(MXC_CCM_CSCDR1); - u32 podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >> - MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET; - - if (cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL) - clkroot = PLL2_PFD0_FREQ; - else - clkroot = PLL2_PFD2_FREQ; - - return clkroot / (podf + 1); -} - -static u32 __get_usdhc2_clk(void) -{ - u32 clkroot; - u32 cscmr1 = __REG(MXC_CCM_CSCMR1); - u32 cscdr1 = __REG(MXC_CCM_CSCDR1); - u32 podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >> - MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET; - - if (cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL) - clkroot = PLL2_PFD0_FREQ; - else - clkroot = PLL2_PFD2_FREQ; - - return clkroot / (podf + 1); -} - -static u32 __get_usdhc3_clk(void) -{ - u32 clkroot; - u32 cscmr1 = __REG(MXC_CCM_CSCMR1); - u32 cscdr1 = __REG(MXC_CCM_CSCDR1); - u32 podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >> - MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET; - - if (cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL) - clkroot = PLL2_PFD0_FREQ; - else - clkroot = PLL2_PFD2_FREQ; - - return clkroot / (podf + 1); -} - -static u32 __get_usdhc4_clk(void) -{ - u32 clkroot; - u32 cscmr1 = __REG(MXC_CCM_CSCMR1); - u32 cscdr1 = __REG(MXC_CCM_CSCDR1); - u32 podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >> - MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET; - - if (cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL) - clkroot = PLL2_PFD0_FREQ; - else - clkroot = PLL2_PFD2_FREQ; - - return clkroot / (podf + 1); -} - -u32 imx_get_mmcclk(void) -{ - return __get_usdhc3_clk(); -} - -u32 imx_get_fecclk(void) -{ - return __get_ipg_clk(); -} - -u32 imx_get_i2cclk(void) -{ - return __get_ipg_per_clk(); -} - -u32 imx_get_cspiclk(void) -{ - return __get_cspi_clk(); -} - -void imx_dump_clocks(void) -{ - u32 freq; - - freq = __decode_pll(CPU_PLL1, CONFIG_MX6_HCLK_FREQ); - printf("mx6q pll1: %d\n", freq); - freq = __decode_pll(BUS_PLL2, CONFIG_MX6_HCLK_FREQ); - printf("mx6q pll2: %d\n", freq); - freq = __decode_pll(USBOTG_PLL3, CONFIG_MX6_HCLK_FREQ); - printf("mx6q pll3: %d\n", freq); - freq = __decode_pll(ENET_PLL8, CONFIG_MX6_HCLK_FREQ); - printf("mx6q pll8: %d\n", freq); - printf("mcu main: %d\n", __get_mcu_main_clk()); - printf("periph: %d\n", __get_periph_clk()); - printf("i2c: %d\n", __get_ipg_per_clk()); - printf("ipg: %d\n", __get_ipg_clk()); - printf("ipg per: %d\n", __get_ipg_per_clk()); - printf("cspi: %d\n", __get_cspi_clk()); - printf("axi: %d\n", __get_axi_clk()); - printf("ahb: %d\n", __get_ahb_clk()); - printf("emi slow: %d\n", __get_emi_slow_clk()); - printf("nfc: %d\n", __get_nfc_clk()); - printf("ddr: %d\n", __get_ddr_clk()); - printf("usdhc1: %d\n", __get_usdhc1_clk()); - printf("usdhc2: %d\n", __get_usdhc2_clk()); - printf("usdhc3: %d\n", __get_usdhc3_clk()); - printf("usdhc4: %d\n", __get_usdhc4_clk()); -} - -void imx6_ipu_clk_enable(int di) -{ - u32 reg; - - if (di == 1) { - reg = readl(MXC_CCM_CCGR3); - reg |= 0xC033; - writel(reg, MXC_CCM_CCGR3); - } else { - reg = readl(MXC_CCM_CCGR3); - reg |= 0x300F; - writel(reg, MXC_CCM_CCGR3); - } - - reg = readl(MX6_ANATOP_BASE_ADDR + 0xF0); - reg &= ~0x00003F00; - reg |= 0x00001300; - writel(reg, MX6_ANATOP_BASE_ADDR + 0xF4); - - reg = readl(MXC_CCM_CS2CDR); - reg &= ~0x00007E00; - reg |= 0x00001200; - writel(reg, MXC_CCM_CS2CDR); - - reg = readl(MXC_CCM_CSCMR2); - reg |= 0x00000C00; - writel(reg, MXC_CCM_CSCMR2); - - reg = 0x0002A953; - writel(reg, MXC_CCM_CHSCDR); -} diff --git a/arch/arm/mach-imx/speed.c b/arch/arm/mach-imx/speed.c deleted file mode 100644 index c86ad71758..0000000000 --- a/arch/arm/mach-imx/speed.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * - * (c) 2004 Sascha Hauer - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include - -/* - * get the system pll clock in Hz - * - * mfi + mfn / (mfd +1) - * f = 2 * f_ref * -------------------- - * pd + 1 - */ -unsigned int imx_decode_pll(unsigned int reg_val, unsigned int freq) -{ - unsigned long long ll; - int mfn_abs; - unsigned int mfi, mfn, mfd, pd; - - mfi = (reg_val >> 10) & 0xf; - mfn = reg_val & 0x3ff; - mfd = (reg_val >> 16) & 0x3ff; - pd = (reg_val >> 26) & 0xf; - - mfi = mfi <= 5 ? 5 : mfi; - - mfn_abs = mfn; - -#if !defined CONFIG_ARCH_MX1 && !defined CONFIG_ARCH_MX21 - if (mfn >= 0x200) { - mfn |= 0xFFFFFE00; - mfn_abs = -mfn; - } -#endif - - freq *= 2; - freq /= pd + 1; - - ll = (unsigned long long)freq * mfn_abs; - - do_div(ll, mfd + 1); - if (mfn < 0) - ll = -ll; - ll = (freq * mfi) + ll; - - return ll; -} - -extern void imx_dump_clocks(void); - -static int do_clocks(int argc, char *argv[]) -{ - imx_dump_clocks(); - - return 0; -} - -BAREBOX_CMD_START(dump_clocks) - .cmd = do_clocks, - .usage = "show clock frequencies", - BAREBOX_CMD_COMPLETE(empty_complete) -BAREBOX_CMD_END - diff --git a/drivers/mci/imx-esdhc.c b/drivers/mci/imx-esdhc.c index 449fe8dbca..7a13cdb0b2 100644 --- a/drivers/mci/imx-esdhc.c +++ b/drivers/mci/imx-esdhc.c @@ -31,7 +31,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/serial/serial_imx.c b/drivers/serial/serial_imx.c index 96f67122cc..354a1e3a01 100644 --- a/drivers/serial/serial_imx.c +++ b/drivers/serial/serial_imx.c @@ -16,7 +16,6 @@ #include #include -#include #include #include #include diff --git a/drivers/spi/imx_spi.c b/drivers/spi/imx_spi.c index 0229374f7a..568c304c86 100644 --- a/drivers/spi/imx_spi.c +++ b/drivers/spi/imx_spi.c @@ -25,7 +25,6 @@ #include #include #include -#include #include #include diff --git a/drivers/video/imx.c b/drivers/video/imx.c index 810d8e3ab6..7ddc2f1226 100644 --- a/drivers/video/imx.c +++ b/drivers/video/imx.c @@ -26,7 +26,6 @@ #include #include #include -#include #define LCDC_SSA 0x00 -- cgit v1.2.3