From 24ff6d5a11c5f79701292c8ee9827ee724ffce4a Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Fri, 1 Nov 2019 20:54:29 +0100 Subject: serial: cadence: fix serial_flush The TXEMPTY bit gets set as soon as the transmit FIFO gets empty, so flushing must wait until the bit is set instead of being unset. Signed-off-by: Lucas Stach Signed-off-by: Sascha Hauer --- drivers/serial/serial_cadence.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/serial') diff --git a/drivers/serial/serial_cadence.c b/drivers/serial/serial_cadence.c index 0501c400b1..6454888e3c 100644 --- a/drivers/serial/serial_cadence.c +++ b/drivers/serial/serial_cadence.c @@ -199,7 +199,7 @@ static void cadence_serial_flush(struct console_device *cdev) struct cadence_serial_priv, cdev); while ((readl(priv->regs + CADENCE_UART_CHANNEL_STS) & - CADENCE_STS_TEMPTY) != 0) + CADENCE_STS_TEMPTY) == 0) ; } -- cgit v1.2.3