From 04aa7be82a2df5bec926d6e426e36accd44808a2 Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Thu, 11 Jun 2020 19:18:38 +0200 Subject: watchdog: f71808e: maintain watchdog timeout occurred flag If we experience a watchdog reset, the indicating flag should persist till the Linux driver had a chance to see it. The flag bit is special however in that writing 1 clears the bit and writing 0 keeps it intact, i.e. : Bit read written result 0 0 = 0 1 0 = 1 0 1 = 0 1 1 = 0 So in the bootloader, we should write a zero always. The OS on the other hand can either write 1 or the old value after reading to clear the flag. Signed-off-by: Ahmad Fatoum Signed-off-by: Sascha Hauer --- drivers/watchdog/f71808e_wdt.c | 59 ++++++++++++++++++++++++++++-------------- 1 file changed, 40 insertions(+), 19 deletions(-) (limited to 'drivers') diff --git a/drivers/watchdog/f71808e_wdt.c b/drivers/watchdog/f71808e_wdt.c index 6f2d30ec77..925c2f809d 100644 --- a/drivers/watchdog/f71808e_wdt.c +++ b/drivers/watchdog/f71808e_wdt.c @@ -11,7 +11,6 @@ #include #include -#include #include #include #include @@ -114,30 +113,50 @@ static inline void superio_exit(u16 base) outb(SIO_LOCK_KEY, base); } +static inline u8 f71808e_wdt_conf_in(struct f71808e_wdt *wd) +{ + return superio_inb(wd->sioaddr, F71808FG_REG_WDT_CONF); +} + +static inline void f71808e_wdt_conf_out(struct f71808e_wdt *wd, u8 wdt_conf) +{ + /* + * Writing 1 to WDTMOUT_STS clears it. Writing 0 keeps the old state. + * We want the latter, so the OS driver can check it later on. + */ + wdt_conf &= ~BIT(F71808FG_FLAG_WDTMOUT_STS); + superio_outb(wd->sioaddr, F71808FG_REG_WDT_CONF, wdt_conf); +} + static void f71808e_wdt_keepalive(struct f71808e_wdt *wd) { + u8 wdt_conf; + superio_enter(wd->sioaddr); superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT); + wdt_conf = f71808e_wdt_conf_in(wd); + if (wd->minutes_mode) /* select minutes for timer units */ - superio_set_bit(wd->sioaddr, F71808FG_REG_WDT_CONF, - F71808FG_FLAG_WD_UNIT); + wdt_conf |= BIT(F71808FG_FLAG_WD_UNIT); else /* select seconds for timer units */ - superio_clear_bit(wd->sioaddr, F71808FG_REG_WDT_CONF, - F71808FG_FLAG_WD_UNIT); + wdt_conf &= ~BIT(F71808FG_FLAG_WD_UNIT); + + f71808e_wdt_conf_out(wd, wdt_conf); /* Set timer value */ - superio_outb(wd->sioaddr, F71808FG_REG_WD_TIME, - wd->timer_val); + superio_outb(wd->sioaddr, F71808FG_REG_WD_TIME, wd->timer_val); superio_exit(wd->sioaddr); } static void f71808e_wdt_start(struct f71808e_wdt *wd) { + u8 wdt_conf; + /* Make sure we don't die as soon as the watchdog is enabled below */ f71808e_wdt_keepalive(wd); @@ -158,36 +177,38 @@ static void f71808e_wdt_start(struct f71808e_wdt *wd) superio_set_bit(wd->sioaddr, F71808FG_REG_WDO_CONF, F71808FG_FLAG_WDOUT_EN); - superio_set_bit(wd->sioaddr, F71808FG_REG_WDT_CONF, - F71808FG_FLAG_WD_EN); + wdt_conf = f71808e_wdt_conf_in(wd); + wdt_conf |= BIT(F71808FG_FLAG_WD_EN); + f71808e_wdt_conf_out(wd, wdt_conf); if (wd->pulse_width > 0) { /* Select "pulse" output mode with given duration */ - u8 wdt_conf = superio_inb(wd->sioaddr, F71808FG_REG_WDT_CONF); - /* Set WD_PSWIDTH bits (1:0) */ wdt_conf = (wdt_conf & 0xfc) | (wd->pulse_width & 0x03); /* Set WD_PULSE to "pulse" mode */ wdt_conf |= BIT(F71808FG_FLAG_WD_PULSE); - superio_outb(wd->sioaddr, F71808FG_REG_WDT_CONF, wdt_conf); } else { /* Select "level" output mode */ - superio_clear_bit(wd->sioaddr, F71808FG_REG_WDT_CONF, - F71808FG_FLAG_WD_PULSE); + wdt_conf &= ~BIT(F71808FG_FLAG_WD_PULSE); } + f71808e_wdt_conf_out(wd, wdt_conf); + superio_exit(wd->sioaddr); } static void f71808e_wdt_stop(struct f71808e_wdt *wd) { + u8 wdt_conf; + superio_enter(wd->sioaddr); superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT); - superio_clear_bit(wd->sioaddr, F71808FG_REG_WDT_CONF, - F71808FG_FLAG_WD_EN); + wdt_conf = f71808e_wdt_conf_in(wd); + wdt_conf &= ~BIT(F71808FG_FLAG_WD_EN); + f71808e_wdt_conf_out(wd, wdt_conf); superio_exit(wd->sioaddr); } @@ -222,14 +243,14 @@ static int f71808e_wdt_init(struct f71808e_wdt *wd, struct device_d *dev) { struct watchdog *wdd = &wd->wdd; const char * const *names = pulse_width_names; - unsigned long wdt_conf; + u8 wdt_conf; int ret; superio_enter(wd->sioaddr); superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT); - wdt_conf = superio_inb(wd->sioaddr, F71808FG_REG_WDT_CONF); + wdt_conf = f71808e_wdt_conf_in(wd); superio_exit(wd->sioaddr); @@ -262,7 +283,7 @@ static int f71808e_wdt_init(struct f71808e_wdt *wd, struct device_d *dev) } - if (test_bit(F71808FG_FLAG_WD_EN, &wdt_conf)) + if (wdt_conf & BIT(F71808FG_FLAG_WD_EN)) wdd->running = WDOG_HW_RUNNING; else wdd->running = WDOG_HW_NOT_RUNNING; -- cgit v1.2.3 From a5364fea692ecc49c5c987d1dfa22e9a262df7c0 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 16 Jun 2020 10:41:32 +0200 Subject: net: phy: port phy_interface_is_rgmii() from kernel and remove duplicates from other drivers Signed-off-by: Oleksij Rempel Signed-off-by: Sascha Hauer --- drivers/net/phy/dp83867.c | 6 ------ drivers/net/phy/marvell.c | 6 ------ include/linux/phy.h | 21 +++++++++++++++++++++ 3 files changed, 21 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index b3328b7e44..8e6f198ca2 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -177,12 +177,6 @@ static int dp83867_of_init(struct phy_device *phydev) &dp83867->fifo_depth); } -static inline bool phy_interface_is_rgmii(struct phy_device *phydev) -{ - return phydev->interface >= PHY_INTERFACE_MODE_RGMII && - phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID; -} - static inline bool phy_interface_is_sgmii(struct phy_device *phydev) { return phydev->interface == PHY_INTERFACE_MODE_SGMII || diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index 73d6453b36..af39ed68fd 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -168,12 +168,6 @@ static int marvell_read_status(struct phy_device *phydev) #define MII_88E1510_GEN_CTRL_REG_1 0x14 -static inline bool phy_interface_is_rgmii(struct phy_device *phydev) -{ - return phydev->interface >= PHY_INTERFACE_MODE_RGMII && - phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID; -}; - /* * Set and/or override some configuration registers based on the * marvell,reg-init property stored in the of_node for the phydev. diff --git a/include/linux/phy.h b/include/linux/phy.h index a9fdf44f1a..eec1332c9d 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -353,6 +353,27 @@ static inline int phy_clear_bits(struct phy_device *phydev, u32 regnum, u16 val) return phy_modify(phydev, regnum, val, 0); } +/** + * phy_interface_mode_is_rgmii - Convenience function for testing if a + * PHY interface mode is RGMII (all variants) + * @mode: the phy_interface_t enum + */ +static inline bool phy_interface_mode_is_rgmii(phy_interface_t mode) +{ + return mode >= PHY_INTERFACE_MODE_RGMII && + mode <= PHY_INTERFACE_MODE_RGMII_TXID; +}; + +/** + * phy_interface_is_rgmii - Convenience function for testing if a PHY interface + * is RGMII (all variants) + * @phydev: the phy_device struct + */ +static inline bool phy_interface_is_rgmii(struct phy_device *phydev) +{ + return phy_interface_mode_is_rgmii(phydev->interface); +}; + int phy_device_connect(struct eth_device *dev, struct mii_bus *bus, int addr, void (*adjust_link) (struct eth_device *edev), u32 flags, phy_interface_t interface); -- cgit v1.2.3 From 85df5403d69fd33e3b262690a61286aed1c22209 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 16 Jun 2020 10:41:33 +0200 Subject: net: phy: micrel: backport ksz9031 phy-mode support this patch will allow to use proper clock skew configuration from devicetree instead of using board specific fixups. Signed-off-by: Oleksij Rempel Signed-off-by: Sascha Hauer --- drivers/net/phy/micrel.c | 103 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) (limited to 'drivers') diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index 8f0b81d8fa..c13f80cf40 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -18,6 +18,7 @@ #include #include #include +#include /* Operation Mode Strap Override */ #define MII_KSZPHY_OMSO 0x16 @@ -155,9 +156,50 @@ static int ksz9021_config_init(struct phy_device *phydev) /* MMD Address 0x2 */ #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4 +#define MII_KSZ9031RN_RX_CTL_M GENMASK(7, 4) +#define MII_KSZ9031RN_TX_CTL_M GENMASK(3, 0) + #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5 +#define MII_KSZ9031RN_RXD3 GENMASK(15, 12) +#define MII_KSZ9031RN_RXD2 GENMASK(11, 8) +#define MII_KSZ9031RN_RXD1 GENMASK(7, 4) +#define MII_KSZ9031RN_RXD0 GENMASK(3, 0) + #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6 +#define MII_KSZ9031RN_TXD3 GENMASK(15, 12) +#define MII_KSZ9031RN_TXD2 GENMASK(11, 8) +#define MII_KSZ9031RN_TXD1 GENMASK(7, 4) +#define MII_KSZ9031RN_TXD0 GENMASK(3, 0) + #define MII_KSZ9031RN_CLK_PAD_SKEW 8 +#define MII_KSZ9031RN_GTX_CLK GENMASK(9, 5) +#define MII_KSZ9031RN_RX_CLK GENMASK(4, 0) + +/* KSZ9031 has internal RGMII_IDRX = 1.2ns and RGMII_IDTX = 0ns. To + * provide different RGMII options we need to configure delay offset + * for each pad relative to build in delay. + */ +/* keep rx as "No delay adjustment" and set rx_clk to +0.60ns to get delays of + * 1.80ns + */ +#define RX_ID 0x7 +#define RX_CLK_ID 0x19 + +/* set rx to +0.30ns and rx_clk to -0.90ns to compensate the + * internal 1.2ns delay. + */ +#define RX_ND 0xc +#define RX_CLK_ND 0x0 + +/* set tx to -0.42ns and tx_clk to +0.96ns to get 1.38ns delay */ +#define TX_ID 0x0 +#define TX_CLK_ID 0x1f + +/* set tx and tx_clk to "No delay adjustment" to keep 0ns + * dealy + */ +#define TX_ND 0x7 +#define TX_CLK_ND 0xf static int ksz9031_of_load_skew_values(struct phy_device *phydev, const struct device_node *of_node, @@ -206,6 +248,61 @@ static int ksz9031_center_flp_timing(struct phy_device *phydev) return genphy_restart_aneg(phydev); } +static int ksz9031_config_rgmii_delay(struct phy_device *phydev) +{ + u16 rx, tx, rx_clk, tx_clk; + + switch (phydev->interface) { + case PHY_INTERFACE_MODE_RGMII: + tx = TX_ND; + tx_clk = TX_CLK_ND; + rx = RX_ND; + rx_clk = RX_CLK_ND; + break; + case PHY_INTERFACE_MODE_RGMII_ID: + tx = TX_ID; + tx_clk = TX_CLK_ID; + rx = RX_ID; + rx_clk = RX_CLK_ID; + break; + case PHY_INTERFACE_MODE_RGMII_RXID: + tx = TX_ND; + tx_clk = TX_CLK_ND; + rx = RX_ID; + rx_clk = RX_CLK_ID; + break; + case PHY_INTERFACE_MODE_RGMII_TXID: + tx = TX_ID; + tx_clk = TX_CLK_ID; + rx = RX_ND; + rx_clk = RX_CLK_ND; + break; + default: + return 0; + } + + phy_write_mmd_indirect(phydev, MII_KSZ9031RN_CONTROL_PAD_SKEW, 2, + FIELD_PREP(MII_KSZ9031RN_RX_CTL_M, rx) | + FIELD_PREP(MII_KSZ9031RN_TX_CTL_M, tx)); + + phy_write_mmd_indirect(phydev, MII_KSZ9031RN_RX_DATA_PAD_SKEW, 2, + FIELD_PREP(MII_KSZ9031RN_RXD3, rx) | + FIELD_PREP(MII_KSZ9031RN_RXD2, rx) | + FIELD_PREP(MII_KSZ9031RN_RXD1, rx) | + FIELD_PREP(MII_KSZ9031RN_RXD0, rx)); + + phy_write_mmd_indirect(phydev, MII_KSZ9031RN_TX_DATA_PAD_SKEW, 2, + FIELD_PREP(MII_KSZ9031RN_TXD3, tx) | + FIELD_PREP(MII_KSZ9031RN_TXD2, tx) | + FIELD_PREP(MII_KSZ9031RN_TXD1, tx) | + FIELD_PREP(MII_KSZ9031RN_TXD0, tx)); + + phy_write_mmd_indirect(phydev, MII_KSZ9031RN_CLK_PAD_SKEW, 2, + FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) | + FIELD_PREP(MII_KSZ9031RN_RX_CLK, rx_clk)); + return 0; +} + static int ksz9031_config_init(struct phy_device *phydev) { const struct device_d *dev = &phydev->dev; @@ -226,6 +323,12 @@ static int ksz9031_config_init(struct phy_device *phydev) of_node = dev->parent->device_node; if (of_node) { + if (phy_interface_is_rgmii(phydev)) { + ret = ksz9031_config_rgmii_delay(phydev); + if (ret < 0) + return ret; + } + ksz9031_of_load_skew_values(phydev, of_node, MII_KSZ9031RN_CLK_PAD_SKEW, 5, clk_skews, 2); -- cgit v1.2.3 From c6114a600b284d3ef8b1255e7127815c49d20c9d Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Wed, 24 Jun 2020 15:58:36 +0200 Subject: treewide: make use of PTR_ERR_OR_ZERO MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PTR_ERR_OR_ZERO is designed to replace boiler plate like: if (IS_ERR(x)) return PTR_ERR(x); return 0; Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/boards/freescale-mx23-evk/mx23-evk.c | 4 +--- arch/arm/boards/karo-tx28/tx28-stk5.c | 4 +--- common/globalvar.c | 5 +---- common/serdev.c | 5 +---- drivers/mfd/rave-sp.c | 5 +---- drivers/mtd/ubi/eba.c | 12 +++--------- drivers/net/designware_generic.c | 5 +---- drivers/pci/pci-tegra.c | 5 +---- drivers/pwm/core.c | 5 +---- drivers/usb/otg/otgdev.c | 5 +---- drivers/watchdog/rave-sp-wdt.c | 5 +---- 11 files changed, 13 insertions(+), 47 deletions(-) (limited to 'drivers') diff --git a/arch/arm/boards/freescale-mx23-evk/mx23-evk.c b/arch/arm/boards/freescale-mx23-evk/mx23-evk.c index 9dc5967bd9..b12bb0dd79 100644 --- a/arch/arm/boards/freescale-mx23-evk/mx23-evk.c +++ b/arch/arm/boards/freescale-mx23-evk/mx23-evk.c @@ -79,9 +79,7 @@ static int register_persistent_environment(void) /* use the full partition as our persistent environment storage */ cdev = devfs_add_partition("disk0.1", 0, cdev->size, DEVFS_PARTITION_FIXED, "env0"); - if (IS_ERR(cdev)) - return PTR_ERR(cdev); - return 0; + return PTR_ERR_OR_ZERO(cdev); } static int mx23_evk_devices_init(void) diff --git a/arch/arm/boards/karo-tx28/tx28-stk5.c b/arch/arm/boards/karo-tx28/tx28-stk5.c index 838754d042..c9b947953b 100644 --- a/arch/arm/boards/karo-tx28/tx28-stk5.c +++ b/arch/arm/boards/karo-tx28/tx28-stk5.c @@ -333,9 +333,7 @@ static int register_persistent_environment(void) /* use the full partition as our persistent environment storage */ cdev = devfs_add_partition("disk0.1", 0, cdev->size, DEVFS_PARTITION_FIXED, "env0"); - if (IS_ERR(cdev)) - return PTR_ERR(cdev); - return 0; + return PTR_ERR_OR_ZERO(cdev); } static void tx28_get_ethaddr(void) diff --git a/common/globalvar.c b/common/globalvar.c index c87f2c9339..98a028a68a 100644 --- a/common/globalvar.c +++ b/common/globalvar.c @@ -563,10 +563,7 @@ int globalvar_add_simple_bitmask(const char *name, unsigned long *value, p = dev_add_param_bitmask(&global_device, name, NULL, NULL, value, names, max, NULL); - if (IS_ERR(p)) - return PTR_ERR(p); - - return 0; + return PTR_ERR_OR_ZERO(p); } int globalvar_add_simple_ip(const char *name, IPaddr_t *ip) diff --git a/common/serdev.c b/common/serdev.c index c50b3bd26a..4bf11b1618 100644 --- a/common/serdev.c +++ b/common/serdev.c @@ -84,10 +84,7 @@ int serdev_device_open(struct serdev_device *serdev) p = dev_add_param_uint64(serdev->dev, "polling_interval", serdev_device_set_polling_interval, NULL, &serdev->polling_interval, "%llu", serdev); - if (IS_ERR(p)) - return PTR_ERR(p); - - return 0; + return PTR_ERR_OR_ZERO(p); } unsigned int serdev_device_set_baudrate(struct serdev_device *serdev, diff --git a/drivers/mfd/rave-sp.c b/drivers/mfd/rave-sp.c index c6ad57d517..8fc46b66bb 100644 --- a/drivers/mfd/rave-sp.c +++ b/drivers/mfd/rave-sp.c @@ -787,10 +787,7 @@ static int rave_sp_add_params(struct rave_sp *sp) p = dev_add_param_ip(dev, "netmask", NULL, rave_sp_req_ip_addr, &sp->netmask, sp); - if (IS_ERR(p)) - return PTR_ERR(p); - - return 0; + return PTR_ERR_OR_ZERO(p); } static int rave_sp_probe(struct device_d *dev) diff --git a/drivers/mtd/ubi/eba.c b/drivers/mtd/ubi/eba.c index cca6ec4ba9..071bbca236 100644 --- a/drivers/mtd/ubi/eba.c +++ b/drivers/mtd/ubi/eba.c @@ -324,9 +324,7 @@ static int leb_read_lock(struct ubi_device *ubi, int vol_id, int lnum) struct ubi_ltree_entry *le; le = ltree_add_entry(ubi, vol_id, lnum); - if (IS_ERR(le)) - return PTR_ERR(le); - return 0; + return PTR_ERR_OR_ZERO(le); } /** @@ -362,9 +360,7 @@ static int leb_write_lock(struct ubi_device *ubi, int vol_id, int lnum) struct ubi_ltree_entry *le; le = ltree_add_entry(ubi, vol_id, lnum); - if (IS_ERR(le)) - return PTR_ERR(le); - return 0; + return PTR_ERR_OR_ZERO(le); } /** @@ -383,9 +379,7 @@ static int leb_write_trylock(struct ubi_device *ubi, int vol_id, int lnum) struct ubi_ltree_entry *le; le = ltree_add_entry(ubi, vol_id, lnum); - if (IS_ERR(le)) - return PTR_ERR(le); - return 0; + return PTR_ERR_OR_ZERO(le); } /** diff --git a/drivers/net/designware_generic.c b/drivers/net/designware_generic.c index 809c7b7b69..90fca1951d 100644 --- a/drivers/net/designware_generic.c +++ b/drivers/net/designware_generic.c @@ -21,10 +21,7 @@ static int dwc_ether_probe(struct device_d *dev) struct dw_eth_dev *dwc; dwc = dwc_drv_probe(dev); - if (IS_ERR(dwc)) - return PTR_ERR(dwc); - - return 0; + return PTR_ERR_OR_ZERO(dwc); } static __maybe_unused struct of_device_id dwc_ether_compatible[] = { diff --git a/drivers/pci/pci-tegra.c b/drivers/pci/pci-tegra.c index 7f10b7af2e..b534285c97 100644 --- a/drivers/pci/pci-tegra.c +++ b/drivers/pci/pci-tegra.c @@ -822,10 +822,7 @@ static int tegra_pcie_resets_get(struct tegra_pcie *pcie) return PTR_ERR(pcie->afi_rst); pcie->pcie_xrst = reset_control_get(pcie->dev, "pcie_x"); - if (IS_ERR(pcie->pcie_xrst)) - return PTR_ERR(pcie->pcie_xrst); - - return 0; + return PTR_ERR_OR_ZERO(pcie->pcie_xrst); } static int tegra_pcie_get_resources(struct tegra_pcie *pcie) diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c index 878f4d72bb..aba6c2a709 100644 --- a/drivers/pwm/core.c +++ b/drivers/pwm/core.c @@ -122,10 +122,7 @@ int pwmchip_add(struct pwm_chip *chip, struct device_d *dev) p = dev_add_param_bool(&pwm->dev, "inverted", apply_params, NULL, &pwm->params.polarity, pwm); - if (IS_ERR(p)) - return PTR_ERR(p); - - return 0; + return PTR_ERR_OR_ZERO(p); } EXPORT_SYMBOL_GPL(pwmchip_add); diff --git a/drivers/usb/otg/otgdev.c b/drivers/usb/otg/otgdev.c index 7017796e8c..52f43b75d2 100644 --- a/drivers/usb/otg/otgdev.c +++ b/drivers/usb/otg/otgdev.c @@ -62,8 +62,5 @@ int usb_register_otg_device(struct device_d *parent, param_mode = dev_add_param_enum(&otg_device, "mode", otg_set_mode, NULL, &otg_mode, otg_mode_names, ARRAY_SIZE(otg_mode_names), ctx); - if (IS_ERR(param_mode)) - return PTR_ERR(param_mode); - - return 0; + return PTR_ERR_OR_ZERO(param_mode); } diff --git a/drivers/watchdog/rave-sp-wdt.c b/drivers/watchdog/rave-sp-wdt.c index dc673ee35f..cad63e22f9 100644 --- a/drivers/watchdog/rave-sp-wdt.c +++ b/drivers/watchdog/rave-sp-wdt.c @@ -299,10 +299,7 @@ static int rave_sp_wdt_add_params(struct rave_sp_wdt *sp_wd) rave_sp_wdt_set_boot_source, rave_sp_wdt_get_boot_source, &sp_wd->boot_source, "%u", sp_wd); - if (IS_ERR(p)) - return PTR_ERR(p); - - return 0; + return PTR_ERR_OR_ZERO(p); } static int rave_sp_wdt_probe(struct device_d *dev) -- cgit v1.2.3 From 5a38c49c3dafe2323c23b07f883df6e904cf86ba Mon Sep 17 00:00:00 2001 From: Michael Grzeschik Date: Tue, 30 Jun 2020 13:06:02 +0200 Subject: net: phy: add uapi/linux/mdio.h from kernel for MDIO MMD access The headerfile is used in the kernel for access of MDIO Managed Devices (MMD) indirect access. Some drivers already use those device addresses. We add the headerfile from the kernel and change the current users to use the defines instead Reviewed-by: Ahmad Fatoum Signed-off-by: Michael Grzeschik Signed-off-by: Sascha Hauer --- drivers/net/phy/dp83867.c | 3 +- drivers/net/phy/micrel.c | 5 +- include/linux/mdio.h | 327 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 332 insertions(+), 3 deletions(-) create mode 100644 include/linux/mdio.h (limited to 'drivers') diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index 8e6f198ca2..929a407b09 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -18,9 +18,10 @@ #include #include +#include #define DP83867_PHY_ID 0x2000a231 -#define DP83867_DEVADDR 0x1f +#define DP83867_DEVADDR MDIO_MMD_VEND2 #define MII_DP83867_PHYCTRL 0x10 #define MII_DP83867_MICR 0x12 diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index c13f80cf40..4655430573 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -221,7 +222,7 @@ static int ksz9031_of_load_skew_values(struct phy_device *phydev, return 0; if (matches < numfields) - newval = phy_read_mmd_indirect(phydev, reg, 2); + newval = phy_read_mmd_indirect(phydev, reg, MDIO_MMD_WIS); else newval = 0; @@ -235,7 +236,7 @@ static int ksz9031_of_load_skew_values(struct phy_device *phydev, << (field_sz * i)); } - phy_write_mmd_indirect(phydev, reg, 2, newval); + phy_write_mmd_indirect(phydev, reg, MDIO_MMD_WIS, newval); return 0; } diff --git a/include/linux/mdio.h b/include/linux/mdio.h new file mode 100644 index 0000000000..4bcb41c71b --- /dev/null +++ b/include/linux/mdio.h @@ -0,0 +1,327 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* + * linux/mdio.h: definitions for MDIO (clause 45) transceivers + * Copyright 2006-2009 Solarflare Communications Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation, incorporated herein by reference. + */ + +#ifndef _UAPI__LINUX_MDIO_H__ +#define _UAPI__LINUX_MDIO_H__ + +#include +#include + +/* MDIO Manageable Devices (MMDs). */ +#define MDIO_MMD_PMAPMD 1 /* Physical Medium Attachment/ + * Physical Medium Dependent */ +#define MDIO_MMD_WIS 2 /* WAN Interface Sublayer */ +#define MDIO_MMD_PCS 3 /* Physical Coding Sublayer */ +#define MDIO_MMD_PHYXS 4 /* PHY Extender Sublayer */ +#define MDIO_MMD_DTEXS 5 /* DTE Extender Sublayer */ +#define MDIO_MMD_TC 6 /* Transmission Convergence */ +#define MDIO_MMD_AN 7 /* Auto-Negotiation */ +#define MDIO_MMD_C22EXT 29 /* Clause 22 extension */ +#define MDIO_MMD_VEND1 30 /* Vendor specific 1 */ +#define MDIO_MMD_VEND2 31 /* Vendor specific 2 */ + +/* Generic MDIO registers. */ +#define MDIO_CTRL1 MII_BMCR +#define MDIO_STAT1 MII_BMSR +#define MDIO_DEVID1 MII_PHYSID1 +#define MDIO_DEVID2 MII_PHYSID2 +#define MDIO_SPEED 4 /* Speed ability */ +#define MDIO_DEVS1 5 /* Devices in package */ +#define MDIO_DEVS2 6 +#define MDIO_CTRL2 7 /* 10G control 2 */ +#define MDIO_STAT2 8 /* 10G status 2 */ +#define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */ +#define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */ +#define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */ +#define MDIO_PKGID1 14 /* Package identifier */ +#define MDIO_PKGID2 15 +#define MDIO_AN_ADVERTISE 16 /* AN advertising (base page) */ +#define MDIO_AN_LPA 19 /* AN LP abilities (base page) */ +#define MDIO_PCS_EEE_ABLE 20 /* EEE Capability register */ +#define MDIO_PCS_EEE_ABLE2 21 /* EEE Capability register 2 */ +#define MDIO_PMA_NG_EXTABLE 21 /* 2.5G/5G PMA/PMD extended ability */ +#define MDIO_PCS_EEE_WK_ERR 22 /* EEE wake error counter */ +#define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */ +#define MDIO_AN_EEE_ADV 60 /* EEE advertisement */ +#define MDIO_AN_EEE_LPABLE 61 /* EEE link partner ability */ +#define MDIO_AN_EEE_ADV2 62 /* EEE advertisement 2 */ +#define MDIO_AN_EEE_LPABLE2 63 /* EEE link partner ability 2 */ + +/* Media-dependent registers. */ +#define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */ +#define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */ +#define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A. + * Lanes B-D are numbered 134-136. */ +#define MDIO_PMA_10GBR_FECABLE 170 /* 10GBASE-R FEC ability */ +#define MDIO_PCS_10GBX_STAT1 24 /* 10GBASE-X PCS status 1 */ +#define MDIO_PCS_10GBRT_STAT1 32 /* 10GBASE-R/-T PCS status 1 */ +#define MDIO_PCS_10GBRT_STAT2 33 /* 10GBASE-R/-T PCS status 2 */ +#define MDIO_AN_10GBT_CTRL 32 /* 10GBASE-T auto-negotiation control */ +#define MDIO_AN_10GBT_STAT 33 /* 10GBASE-T auto-negotiation status */ + +/* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */ +#define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */ +#define MDIO_PMA_LASI_TXCTRL 0x9001 /* TX_ALARM control */ +#define MDIO_PMA_LASI_CTRL 0x9002 /* LASI control */ +#define MDIO_PMA_LASI_RXSTAT 0x9003 /* RX_ALARM status */ +#define MDIO_PMA_LASI_TXSTAT 0x9004 /* TX_ALARM status */ +#define MDIO_PMA_LASI_STAT 0x9005 /* LASI status */ + +/* Control register 1. */ +/* Enable extended speed selection */ +#define MDIO_CTRL1_SPEEDSELEXT (BMCR_SPEED1000 | BMCR_SPEED100) +/* All speed selection bits */ +#define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x003c) +#define MDIO_CTRL1_FULLDPLX BMCR_FULLDPLX +#define MDIO_CTRL1_LPOWER BMCR_PDOWN +#define MDIO_CTRL1_RESET BMCR_RESET +#define MDIO_PMA_CTRL1_LOOPBACK 0x0001 +#define MDIO_PMA_CTRL1_SPEED1000 BMCR_SPEED1000 +#define MDIO_PMA_CTRL1_SPEED100 BMCR_SPEED100 +#define MDIO_PCS_CTRL1_LOOPBACK BMCR_LOOPBACK +#define MDIO_PHYXS_CTRL1_LOOPBACK BMCR_LOOPBACK +#define MDIO_AN_CTRL1_RESTART BMCR_ANRESTART +#define MDIO_AN_CTRL1_ENABLE BMCR_ANENABLE +#define MDIO_AN_CTRL1_XNP 0x2000 /* Enable extended next page */ +#define MDIO_PCS_CTRL1_CLKSTOP_EN 0x400 /* Stop the clock during LPI */ + +/* 10 Gb/s */ +#define MDIO_CTRL1_SPEED10G (MDIO_CTRL1_SPEEDSELEXT | 0x00) +/* 10PASS-TS/2BASE-TL */ +#define MDIO_CTRL1_SPEED10P2B (MDIO_CTRL1_SPEEDSELEXT | 0x04) +/* 2.5 Gb/s */ +#define MDIO_CTRL1_SPEED2_5G (MDIO_CTRL1_SPEEDSELEXT | 0x18) +/* 5 Gb/s */ +#define MDIO_CTRL1_SPEED5G (MDIO_CTRL1_SPEEDSELEXT | 0x1c) + +/* Status register 1. */ +#define MDIO_STAT1_LPOWERABLE 0x0002 /* Low-power ability */ +#define MDIO_STAT1_LSTATUS BMSR_LSTATUS +#define MDIO_STAT1_FAULT 0x0080 /* Fault */ +#define MDIO_AN_STAT1_LPABLE 0x0001 /* Link partner AN ability */ +#define MDIO_AN_STAT1_ABLE BMSR_ANEGCAPABLE +#define MDIO_AN_STAT1_RFAULT BMSR_RFAULT +#define MDIO_AN_STAT1_COMPLETE BMSR_ANEGCOMPLETE +#define MDIO_AN_STAT1_PAGE 0x0040 /* Page received */ +#define MDIO_AN_STAT1_XNP 0x0080 /* Extended next page status */ + +/* Speed register. */ +#define MDIO_SPEED_10G 0x0001 /* 10G capable */ +#define MDIO_PMA_SPEED_2B 0x0002 /* 2BASE-TL capable */ +#define MDIO_PMA_SPEED_10P 0x0004 /* 10PASS-TS capable */ +#define MDIO_PMA_SPEED_1000 0x0010 /* 1000M capable */ +#define MDIO_PMA_SPEED_100 0x0020 /* 100M capable */ +#define MDIO_PMA_SPEED_10 0x0040 /* 10M capable */ +#define MDIO_PCS_SPEED_10P2B 0x0002 /* 10PASS-TS/2BASE-TL capable */ + +/* Device present registers. */ +#define MDIO_DEVS_PRESENT(devad) (1 << (devad)) +#define MDIO_DEVS_C22PRESENT MDIO_DEVS_PRESENT(0) +#define MDIO_DEVS_PMAPMD MDIO_DEVS_PRESENT(MDIO_MMD_PMAPMD) +#define MDIO_DEVS_WIS MDIO_DEVS_PRESENT(MDIO_MMD_WIS) +#define MDIO_DEVS_PCS MDIO_DEVS_PRESENT(MDIO_MMD_PCS) +#define MDIO_DEVS_PHYXS MDIO_DEVS_PRESENT(MDIO_MMD_PHYXS) +#define MDIO_DEVS_DTEXS MDIO_DEVS_PRESENT(MDIO_MMD_DTEXS) +#define MDIO_DEVS_TC MDIO_DEVS_PRESENT(MDIO_MMD_TC) +#define MDIO_DEVS_AN MDIO_DEVS_PRESENT(MDIO_MMD_AN) +#define MDIO_DEVS_C22EXT MDIO_DEVS_PRESENT(MDIO_MMD_C22EXT) +#define MDIO_DEVS_VEND1 MDIO_DEVS_PRESENT(MDIO_MMD_VEND1) +#define MDIO_DEVS_VEND2 MDIO_DEVS_PRESENT(MDIO_MMD_VEND2) + +/* Control register 2. */ +#define MDIO_PMA_CTRL2_TYPE 0x000f /* PMA/PMD type selection */ +#define MDIO_PMA_CTRL2_10GBCX4 0x0000 /* 10GBASE-CX4 type */ +#define MDIO_PMA_CTRL2_10GBEW 0x0001 /* 10GBASE-EW type */ +#define MDIO_PMA_CTRL2_10GBLW 0x0002 /* 10GBASE-LW type */ +#define MDIO_PMA_CTRL2_10GBSW 0x0003 /* 10GBASE-SW type */ +#define MDIO_PMA_CTRL2_10GBLX4 0x0004 /* 10GBASE-LX4 type */ +#define MDIO_PMA_CTRL2_10GBER 0x0005 /* 10GBASE-ER type */ +#define MDIO_PMA_CTRL2_10GBLR 0x0006 /* 10GBASE-LR type */ +#define MDIO_PMA_CTRL2_10GBSR 0x0007 /* 10GBASE-SR type */ +#define MDIO_PMA_CTRL2_10GBLRM 0x0008 /* 10GBASE-LRM type */ +#define MDIO_PMA_CTRL2_10GBT 0x0009 /* 10GBASE-T type */ +#define MDIO_PMA_CTRL2_10GBKX4 0x000a /* 10GBASE-KX4 type */ +#define MDIO_PMA_CTRL2_10GBKR 0x000b /* 10GBASE-KR type */ +#define MDIO_PMA_CTRL2_1000BT 0x000c /* 1000BASE-T type */ +#define MDIO_PMA_CTRL2_1000BKX 0x000d /* 1000BASE-KX type */ +#define MDIO_PMA_CTRL2_100BTX 0x000e /* 100BASE-TX type */ +#define MDIO_PMA_CTRL2_10BT 0x000f /* 10BASE-T type */ +#define MDIO_PMA_CTRL2_2_5GBT 0x0030 /* 2.5GBaseT type */ +#define MDIO_PMA_CTRL2_5GBT 0x0031 /* 5GBaseT type */ +#define MDIO_PCS_CTRL2_TYPE 0x0003 /* PCS type selection */ +#define MDIO_PCS_CTRL2_10GBR 0x0000 /* 10GBASE-R type */ +#define MDIO_PCS_CTRL2_10GBX 0x0001 /* 10GBASE-X type */ +#define MDIO_PCS_CTRL2_10GBW 0x0002 /* 10GBASE-W type */ +#define MDIO_PCS_CTRL2_10GBT 0x0003 /* 10GBASE-T type */ + +/* Status register 2. */ +#define MDIO_STAT2_RXFAULT 0x0400 /* Receive fault */ +#define MDIO_STAT2_TXFAULT 0x0800 /* Transmit fault */ +#define MDIO_STAT2_DEVPRST 0xc000 /* Device present */ +#define MDIO_STAT2_DEVPRST_VAL 0x8000 /* Device present value */ +#define MDIO_PMA_STAT2_LBABLE 0x0001 /* PMA loopback ability */ +#define MDIO_PMA_STAT2_10GBEW 0x0002 /* 10GBASE-EW ability */ +#define MDIO_PMA_STAT2_10GBLW 0x0004 /* 10GBASE-LW ability */ +#define MDIO_PMA_STAT2_10GBSW 0x0008 /* 10GBASE-SW ability */ +#define MDIO_PMA_STAT2_10GBLX4 0x0010 /* 10GBASE-LX4 ability */ +#define MDIO_PMA_STAT2_10GBER 0x0020 /* 10GBASE-ER ability */ +#define MDIO_PMA_STAT2_10GBLR 0x0040 /* 10GBASE-LR ability */ +#define MDIO_PMA_STAT2_10GBSR 0x0080 /* 10GBASE-SR ability */ +#define MDIO_PMD_STAT2_TXDISAB 0x0100 /* PMD TX disable ability */ +#define MDIO_PMA_STAT2_EXTABLE 0x0200 /* Extended abilities */ +#define MDIO_PMA_STAT2_RXFLTABLE 0x1000 /* Receive fault ability */ +#define MDIO_PMA_STAT2_TXFLTABLE 0x2000 /* Transmit fault ability */ +#define MDIO_PCS_STAT2_10GBR 0x0001 /* 10GBASE-R capable */ +#define MDIO_PCS_STAT2_10GBX 0x0002 /* 10GBASE-X capable */ +#define MDIO_PCS_STAT2_10GBW 0x0004 /* 10GBASE-W capable */ +#define MDIO_PCS_STAT2_RXFLTABLE 0x1000 /* Receive fault ability */ +#define MDIO_PCS_STAT2_TXFLTABLE 0x2000 /* Transmit fault ability */ + +/* Transmit disable register. */ +#define MDIO_PMD_TXDIS_GLOBAL 0x0001 /* Global PMD TX disable */ +#define MDIO_PMD_TXDIS_0 0x0002 /* PMD TX disable 0 */ +#define MDIO_PMD_TXDIS_1 0x0004 /* PMD TX disable 1 */ +#define MDIO_PMD_TXDIS_2 0x0008 /* PMD TX disable 2 */ +#define MDIO_PMD_TXDIS_3 0x0010 /* PMD TX disable 3 */ + +/* Receive signal detect register. */ +#define MDIO_PMD_RXDET_GLOBAL 0x0001 /* Global PMD RX signal detect */ +#define MDIO_PMD_RXDET_0 0x0002 /* PMD RX signal detect 0 */ +#define MDIO_PMD_RXDET_1 0x0004 /* PMD RX signal detect 1 */ +#define MDIO_PMD_RXDET_2 0x0008 /* PMD RX signal detect 2 */ +#define MDIO_PMD_RXDET_3 0x0010 /* PMD RX signal detect 3 */ + +/* Extended abilities register. */ +#define MDIO_PMA_EXTABLE_10GCX4 0x0001 /* 10GBASE-CX4 ability */ +#define MDIO_PMA_EXTABLE_10GBLRM 0x0002 /* 10GBASE-LRM ability */ +#define MDIO_PMA_EXTABLE_10GBT 0x0004 /* 10GBASE-T ability */ +#define MDIO_PMA_EXTABLE_10GBKX4 0x0008 /* 10GBASE-KX4 ability */ +#define MDIO_PMA_EXTABLE_10GBKR 0x0010 /* 10GBASE-KR ability */ +#define MDIO_PMA_EXTABLE_1000BT 0x0020 /* 1000BASE-T ability */ +#define MDIO_PMA_EXTABLE_1000BKX 0x0040 /* 1000BASE-KX ability */ +#define MDIO_PMA_EXTABLE_100BTX 0x0080 /* 100BASE-TX ability */ +#define MDIO_PMA_EXTABLE_10BT 0x0100 /* 10BASE-T ability */ +#define MDIO_PMA_EXTABLE_NBT 0x4000 /* 2.5/5GBASE-T ability */ + +/* PHY XGXS lane state register. */ +#define MDIO_PHYXS_LNSTAT_SYNC0 0x0001 +#define MDIO_PHYXS_LNSTAT_SYNC1 0x0002 +#define MDIO_PHYXS_LNSTAT_SYNC2 0x0004 +#define MDIO_PHYXS_LNSTAT_SYNC3 0x0008 +#define MDIO_PHYXS_LNSTAT_ALIGN 0x1000 + +/* PMA 10GBASE-T pair swap & polarity */ +#define MDIO_PMA_10GBT_SWAPPOL_ABNX 0x0001 /* Pair A/B uncrossed */ +#define MDIO_PMA_10GBT_SWAPPOL_CDNX 0x0002 /* Pair C/D uncrossed */ +#define MDIO_PMA_10GBT_SWAPPOL_AREV 0x0100 /* Pair A polarity reversed */ +#define MDIO_PMA_10GBT_SWAPPOL_BREV 0x0200 /* Pair B polarity reversed */ +#define MDIO_PMA_10GBT_SWAPPOL_CREV 0x0400 /* Pair C polarity reversed */ +#define MDIO_PMA_10GBT_SWAPPOL_DREV 0x0800 /* Pair D polarity reversed */ + +/* PMA 10GBASE-T TX power register. */ +#define MDIO_PMA_10GBT_TXPWR_SHORT 0x0001 /* Short-reach mode */ + +/* PMA 10GBASE-T SNR registers. */ +/* Value is SNR margin in dB, clamped to range [-127, 127], plus 0x8000. */ +#define MDIO_PMA_10GBT_SNR_BIAS 0x8000 +#define MDIO_PMA_10GBT_SNR_MAX 127 + +/* PMA 10GBASE-R FEC ability register. */ +#define MDIO_PMA_10GBR_FECABLE_ABLE 0x0001 /* FEC ability */ +#define MDIO_PMA_10GBR_FECABLE_ERRABLE 0x0002 /* FEC error indic. ability */ + +/* PCS 10GBASE-R/-T status register 1. */ +#define MDIO_PCS_10GBRT_STAT1_BLKLK 0x0001 /* Block lock attained */ + +/* PCS 10GBASE-R/-T status register 2. */ +#define MDIO_PCS_10GBRT_STAT2_ERR 0x00ff +#define MDIO_PCS_10GBRT_STAT2_BER 0x3f00 + +/* AN 10GBASE-T control register. */ +#define MDIO_AN_10GBT_CTRL_ADV2_5G 0x0080 /* Advertise 2.5GBASE-T */ +#define MDIO_AN_10GBT_CTRL_ADV5G 0x0100 /* Advertise 5GBASE-T */ +#define MDIO_AN_10GBT_CTRL_ADV10G 0x1000 /* Advertise 10GBASE-T */ + +/* AN 10GBASE-T status register. */ +#define MDIO_AN_10GBT_STAT_LP2_5G 0x0020 /* LP is 2.5GBT capable */ +#define MDIO_AN_10GBT_STAT_LP5G 0x0040 /* LP is 5GBT capable */ +#define MDIO_AN_10GBT_STAT_LPTRR 0x0200 /* LP training reset req. */ +#define MDIO_AN_10GBT_STAT_LPLTABLE 0x0400 /* LP loop timing ability */ +#define MDIO_AN_10GBT_STAT_LP10G 0x0800 /* LP is 10GBT capable */ +#define MDIO_AN_10GBT_STAT_REMOK 0x1000 /* Remote OK */ +#define MDIO_AN_10GBT_STAT_LOCOK 0x2000 /* Local OK */ +#define MDIO_AN_10GBT_STAT_MS 0x4000 /* Master/slave config */ +#define MDIO_AN_10GBT_STAT_MSFLT 0x8000 /* Master/slave config fault */ + +/* EEE Supported/Advertisement/LP Advertisement registers. + * + * EEE capability Register (3.20), Advertisement (7.60) and + * Link partner ability (7.61) registers have and can use the same identical + * bit masks. + */ +#define MDIO_AN_EEE_ADV_100TX 0x0002 /* Advertise 100TX EEE cap */ +#define MDIO_AN_EEE_ADV_1000T 0x0004 /* Advertise 1000T EEE cap */ +/* Note: the two defines above can be potentially used by the user-land + * and cannot remove them now. + * So, we define the new generic MDIO_EEE_100TX and MDIO_EEE_1000T macros + * using the previous ones (that can be considered obsolete). + */ +#define MDIO_EEE_100TX MDIO_AN_EEE_ADV_100TX /* 100TX EEE cap */ +#define MDIO_EEE_1000T MDIO_AN_EEE_ADV_1000T /* 1000T EEE cap */ +#define MDIO_EEE_10GT 0x0008 /* 10GT EEE cap */ +#define MDIO_EEE_1000KX 0x0010 /* 1000KX EEE cap */ +#define MDIO_EEE_10GKX4 0x0020 /* 10G KX4 EEE cap */ +#define MDIO_EEE_10GKR 0x0040 /* 10G KR EEE cap */ +#define MDIO_EEE_40GR_FW 0x0100 /* 40G R fast wake */ +#define MDIO_EEE_40GR_DS 0x0200 /* 40G R deep sleep */ +#define MDIO_EEE_100GR_FW 0x1000 /* 100G R fast wake */ +#define MDIO_EEE_100GR_DS 0x2000 /* 100G R deep sleep */ + +#define MDIO_EEE_2_5GT 0x0001 /* 2.5GT EEE cap */ +#define MDIO_EEE_5GT 0x0002 /* 5GT EEE cap */ + +/* 2.5G/5G Extended abilities register. */ +#define MDIO_PMA_NG_EXTABLE_2_5GBT 0x0001 /* 2.5GBASET ability */ +#define MDIO_PMA_NG_EXTABLE_5GBT 0x0002 /* 5GBASET ability */ + +/* LASI RX_ALARM control/status registers. */ +#define MDIO_PMA_LASI_RX_PHYXSLFLT 0x0001 /* PHY XS RX local fault */ +#define MDIO_PMA_LASI_RX_PCSLFLT 0x0008 /* PCS RX local fault */ +#define MDIO_PMA_LASI_RX_PMALFLT 0x0010 /* PMA/PMD RX local fault */ +#define MDIO_PMA_LASI_RX_OPTICPOWERFLT 0x0020 /* RX optical power fault */ +#define MDIO_PMA_LASI_RX_WISLFLT 0x0200 /* WIS local fault */ + +/* LASI TX_ALARM control/status registers. */ +#define MDIO_PMA_LASI_TX_PHYXSLFLT 0x0001 /* PHY XS TX local fault */ +#define MDIO_PMA_LASI_TX_PCSLFLT 0x0008 /* PCS TX local fault */ +#define MDIO_PMA_LASI_TX_PMALFLT 0x0010 /* PMA/PMD TX local fault */ +#define MDIO_PMA_LASI_TX_LASERPOWERFLT 0x0080 /* Laser output power fault */ +#define MDIO_PMA_LASI_TX_LASERTEMPFLT 0x0100 /* Laser temperature fault */ +#define MDIO_PMA_LASI_TX_LASERBICURRFLT 0x0200 /* Laser bias current fault */ + +/* LASI control/status registers. */ +#define MDIO_PMA_LASI_LSALARM 0x0001 /* LS_ALARM enable/status */ +#define MDIO_PMA_LASI_TXALARM 0x0002 /* TX_ALARM enable/status */ +#define MDIO_PMA_LASI_RXALARM 0x0004 /* RX_ALARM enable/status */ + +/* Mapping between MDIO PRTAD/DEVAD and mii_ioctl_data::phy_id */ + +#define MDIO_PHY_ID_C45 0x8000 +#define MDIO_PHY_ID_PRTAD 0x03e0 +#define MDIO_PHY_ID_DEVAD 0x001f +#define MDIO_PHY_ID_C45_MASK \ + (MDIO_PHY_ID_C45 | MDIO_PHY_ID_PRTAD | MDIO_PHY_ID_DEVAD) + +static inline __u16 mdio_phy_id_c45(int prtad, int devad) +{ + return MDIO_PHY_ID_C45 | (prtad << 5) | devad; +} + +#endif /* _UAPI__LINUX_MDIO_H__ */ -- cgit v1.2.3 From f7ea95b4f71ce6b7d5b86537e0a9b771a12fec1a Mon Sep 17 00:00:00 2001 From: Michael Grzeschik Date: Tue, 30 Jun 2020 13:06:03 +0200 Subject: drivers: net: phy: at803x: add phy clk setup via dts There are dt-bindings for the setup of the clk configuration in the phy. This patch adds support for these bindings in the driver. Reviewed-by: Ahmad Fatoum Signed-off-by: Michael Grzeschik Signed-off-by: Sascha Hauer --- drivers/net/phy/at803x.c | 178 +++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 171 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index b43cb0d23e..de053a36fb 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -11,6 +11,9 @@ #include #include #include +#include +#include +#include #define AT803X_INTR_ENABLE 0x12 #define AT803X_INTR_STATUS 0x13 @@ -27,6 +30,164 @@ #define AT803X_DEBUG_SYSTEM_MODE_CTRL 0x05 #define AT803X_DEBUG_RGMII_TX_CLK_DLY (1 << 8) +/* AT803x supports either the XTAL input pad, an internal PLL or the + * DSP as clock reference for the clock output pad. The XTAL reference + * is only used for 25 MHz output, all other frequencies need the PLL. + * The DSP as a clock reference is used in synchronous ethernet + * applications. + * + * By default the PLL is only enabled if there is a link. Otherwise + * the PHY will go into low power state and disabled the PLL. You can + * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always + * enabled. + */ +#define AT803X_MMD7_CLK25M 0x8016 +#define AT803X_CLK_OUT_MASK GENMASK(4, 2) +#define AT803X_CLK_OUT_25MHZ_XTAL 0 +#define AT803X_CLK_OUT_25MHZ_DSP 1 +#define AT803X_CLK_OUT_50MHZ_PLL 2 +#define AT803X_CLK_OUT_50MHZ_DSP 3 +#define AT803X_CLK_OUT_62_5MHZ_PLL 4 +#define AT803X_CLK_OUT_62_5MHZ_DSP 5 +#define AT803X_CLK_OUT_125MHZ_PLL 6 +#define AT803X_CLK_OUT_125MHZ_DSP 7 + +/* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask + * but doesn't support choosing between XTAL/PLL and DSP. + */ +#define AT8035_CLK_OUT_MASK GENMASK(4, 3) + +#define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7) +#define AT803X_CLK_OUT_STRENGTH_FULL 0 +#define AT803X_CLK_OUT_STRENGTH_HALF 1 +#define AT803X_CLK_OUT_STRENGTH_QUARTER 2 + +#define ATH9331_PHY_ID 0x004dd041 +#define ATH8030_PHY_ID 0x004dd076 +#define ATH8031_PHY_ID 0x004dd074 +#define ATH8032_PHY_ID 0x004dd023 +#define ATH8035_PHY_ID 0x004dd072 +#define AT8030_PHY_ID_MASK 0xffffffef + +struct at803x_priv { + u16 clk_25m_reg; + u16 clk_25m_mask; +}; + +static bool at803x_match_phy_id(struct phy_device *phydev, u32 phy_id) +{ + struct phy_driver *drv = to_phy_driver(phydev->dev.driver); + + return (phydev->phy_id & drv->phy_id_mask) + == (phy_id & drv->phy_id_mask); +} + +static int at803x_parse_dt(struct phy_device *phydev) +{ + const struct device_d *dev = &phydev->dev; + const struct device_node *node = dev->device_node; + struct at803x_priv *priv = phydev->priv; + unsigned int sel, mask; + u32 freq, strength; + int ret; + + ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq); + if (!ret) { + mask = AT803X_CLK_OUT_MASK; + switch (freq) { + case 25000000: + sel = AT803X_CLK_OUT_25MHZ_XTAL; + break; + case 50000000: + sel = AT803X_CLK_OUT_50MHZ_PLL; + break; + case 62500000: + sel = AT803X_CLK_OUT_62_5MHZ_PLL; + break; + case 125000000: + sel = AT803X_CLK_OUT_125MHZ_PLL; + break; + default: + dev_err(dev, "invalid qca,clk-out-frequency\n"); + return -EINVAL; + } + + priv->clk_25m_reg |= FIELD_PREP(mask, sel); + priv->clk_25m_mask |= mask; + + /* Fixup for the AR8030/AR8035. This chip has another mask and + * doesn't support the DSP reference. Eg. the lowest bit of the + * mask. The upper two bits select the same frequencies. Mask + * the lowest bit here. + * + * Warning: + * There was no datasheet for the AR8030 available so this is + * just a guess. But the AR8035 is listed as pin compatible + * to the AR8030 so there might be a good chance it works on + * the AR8030 too. + */ + if (at803x_match_phy_id(phydev, ATH8030_PHY_ID) || + at803x_match_phy_id(phydev, ATH8035_PHY_ID)) { + priv->clk_25m_reg &= AT8035_CLK_OUT_MASK; + priv->clk_25m_mask &= AT8035_CLK_OUT_MASK; + } + } + + ret = of_property_read_u32(node, "qca,clk-out-strength", &strength); + if (!ret) { + priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK; + switch (strength) { + case AR803X_STRENGTH_FULL: + priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL; + break; + case AR803X_STRENGTH_HALF: + priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF; + break; + case AR803X_STRENGTH_QUARTER: + priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER; + break; + default: + dev_err(dev, "invalid qca,clk-out-strength\n"); + return -EINVAL; + } + } + + return 0; +} + +static int at803x_probe(struct phy_device *phydev) +{ + struct at803x_priv *priv; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + phydev->priv = priv; + + return at803x_parse_dt(phydev); +} + +static int at803x_clk_out_config(struct phy_device *phydev) +{ + struct at803x_priv *priv = phydev->priv; + int val; + + if (!priv->clk_25m_mask) + return 0; + + val = phy_read_mmd_indirect(phydev, AT803X_MMD7_CLK25M, MDIO_MMD_AN); + if (val < 0) + return val; + + val &= ~priv->clk_25m_mask; + val |= priv->clk_25m_reg; + + phy_write_mmd_indirect(phydev, AT803X_MMD7_CLK25M, MDIO_MMD_AN, val); + + return 0; +} + static int at803x_config_init(struct phy_device *phydev) { int ret; @@ -46,33 +207,36 @@ static int at803x_config_init(struct phy_device *phydev) return ret; } - return 0; + return at803x_clk_out_config(phydev); } static struct phy_driver at803x_driver[] = { { /* ATHEROS 8035 */ - .phy_id = 0x004dd072, - .phy_id_mask = 0xffffffef, + .phy_id = ATH8035_PHY_ID, + .phy_id_mask = AT8030_PHY_ID_MASK, .drv.name = "Atheros 8035 ethernet", + .probe = at803x_probe, .config_init = at803x_config_init, .features = PHY_GBIT_FEATURES, .config_aneg = &genphy_config_aneg, .read_status = &genphy_read_status, }, { /* ATHEROS 8030 */ - .phy_id = 0x004dd076, - .phy_id_mask = 0xffffffef, + .phy_id = ATH8030_PHY_ID, + .phy_id_mask = AT8030_PHY_ID_MASK, .drv.name = "Atheros 8030 ethernet", .config_init = at803x_config_init, + .probe = at803x_probe, .features = PHY_GBIT_FEATURES, .config_aneg = &genphy_config_aneg, .read_status = &genphy_read_status, }, { /* ATHEROS 8031 */ - .phy_id = 0x004dd074, - .phy_id_mask = 0xffffffef, + .phy_id = ATH8031_PHY_ID, + .phy_id_mask = AT8030_PHY_ID_MASK, .drv.name = "Atheros 8031 ethernet", + .probe = at803x_probe, .config_init = at803x_config_init, .features = PHY_GBIT_FEATURES, .config_aneg = &genphy_config_aneg, -- cgit v1.2.3 From 5fe4c6d8a9463ff72c84bf41c564e3d3cbcb4e8f Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Thu, 2 Jul 2020 17:37:30 +0200 Subject: ARM: stm32mp: depend on ARCH_STM32MP for SoC drivers The i2c, MCI and reset controller peripherals are STM32-specific. There is no reason to ask uses on oldconfig about it, thus make them depend on ARCH_STM32MP || COMPILE_TEST. Signed-off-by: Ahmad Fatoum Signed-off-by: Sascha Hauer --- drivers/i2c/busses/Kconfig | 1 + drivers/mci/Kconfig | 1 + drivers/reset/Kconfig | 1 + 3 files changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 21d2cb21cf..3bc8d1b8d2 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -59,5 +59,6 @@ config I2C_STM32 bool "STM32 I2C master driver" select RESET_CONTROLLER depends on HAVE_CLK + depends on ARCH_STM32MP || COMPILE_TEST endmenu diff --git a/drivers/mci/Kconfig b/drivers/mci/Kconfig index 6ae1e81252..d1695c678c 100644 --- a/drivers/mci/Kconfig +++ b/drivers/mci/Kconfig @@ -177,6 +177,7 @@ config MCI_STM32_SDMMC2 bool "STMicroelectronics STM32H7 SD/MMC Host Controller support" depends on ARM_AMBA depends on RESET_CONTROLLER + depends on ARCH_STM32MP || COMPILE_TEST help This selects support for the SD/MMC controller on STM32H7 SoCs. If you have a board based on such a SoC and with a SD/MMC slot, diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 9befc5e55f..316ece9e71 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -23,6 +23,7 @@ config RESET_IMX7 config RESET_STM32 bool "STM32 Reset Driver" + depends on ARCH_STM32MP || COMPILE_TEST help This enables the reset controller driver for STM32MP and STM32 MCUs. -- cgit v1.2.3 From 309788aa64c083b8294f083e286cba9334d42744 Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Thu, 2 Jul 2020 16:17:47 +0200 Subject: mci: dw_mmc: remove unused local variable data_start is assigned once and never used. Drop it. Signed-off-by: Ahmad Fatoum Signed-off-by: Sascha Hauer --- drivers/mci/dw_mmc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/mci/dw_mmc.c b/drivers/mci/dw_mmc.c index ab8270814b..0ada65e90e 100644 --- a/drivers/mci/dw_mmc.c +++ b/drivers/mci/dw_mmc.c @@ -124,7 +124,7 @@ static int dwmci_prepare_data_dma(struct dwmci_host *host, { unsigned long ctrl; unsigned int i = 0, flags, cnt, blk_cnt; - unsigned long data_start, start_addr; + unsigned start_addr; struct dwmci_idmac *desc = host->idmac; blk_cnt = data->blocks; @@ -134,7 +134,6 @@ static int dwmci_prepare_data_dma(struct dwmci_host *host, dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); - data_start = (uint32_t)desc; dwmci_writel(host, DWMCI_DBADDR, (uint32_t)desc); if (data->flags & MMC_DATA_READ) -- cgit v1.2.3 From 25d283e53880072cc4d3398ff72ff8b2efb2b079 Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Thu, 2 Jul 2020 15:29:18 +0200 Subject: mfd: superio: smsc: fix C99ism initial declaration in for loop Codebase is meant to be gnu89, but was only enforced starting with bc4840e98b94 ("kbuild: add -Wmissing-prototypes and -std=gnu89 to KBUILD_HOSTCFLAGS"). Since then, this driver no longer compiles. Fix this. Fixes: eaf020f1bb52 ("mfd: superio: add base SMSC MFD driver") Signed-off-by: Ahmad Fatoum Signed-off-by: Sascha Hauer --- drivers/mfd/smsc-superio.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mfd/smsc-superio.c b/drivers/mfd/smsc-superio.c index 349c878cef..ff83aa1a44 100644 --- a/drivers/mfd/smsc-superio.c +++ b/drivers/mfd/smsc-superio.c @@ -106,8 +106,9 @@ static void smsc_superio_find(u16 sioaddr, u16 id_reg) static int smsc_superio_detect(void) { u16 ports[] = { 0x2e, 0x4e, 0x162e, 0x164e, 0x3f0, 0x370 }; + int i; - for (int i = 0; i < ARRAY_SIZE(ports); i++) + for (i = 0; i < ARRAY_SIZE(ports); i++) smsc_superio_find(ports[i], SIO_REG_DEVID); return 0; -- cgit v1.2.3 From aa60c3fa739dd9ddacc0b4fb7b0823a7f6bdb380 Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Thu, 2 Jul 2020 15:29:19 +0200 Subject: mfd: superio: depend on X86 || COMPILE_TEST Super I/O chips are usually found x86 PCs. Make them depend on it, so users of other arches aren't prompted for it, when they oldconfig. Signed-off-by: Ahmad Fatoum Signed-off-by: Sascha Hauer --- drivers/mfd/Kconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 42346154e6..d03d481898 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -73,12 +73,14 @@ config MFD_SUPERIO config FINTEK_SUPERIO bool "Fintek Super I/O chip" select MFD_SUPERIO + depends on X86 || COMPILE_TEST help Select this to probe for IO-port connected Fintek Super I/O chips. config SMSC_SUPERIO bool "SMSC Super I/O chip" select MFD_SUPERIO + depends on X86 || COMPILE_TEST help Select this to probe for IO-port connected SMSC Super I/O chips. -- cgit v1.2.3 From 5e57f52c6a36f1cdc5d9ee1ec7cd8e2f149f9578 Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Mon, 6 Jul 2020 08:26:43 +0200 Subject: i2c: designware: use proper type for writel argument We need to write DW_IC_ENABLE_ENABLE (1 << 0) to the register to enable, but instead we were writing true. This happens to work, but is quite unusual. Make the code more readable. Signed-off-by: Ahmad Fatoum Signed-off-by: Sascha Hauer --- drivers/i2c/busses/i2c-designware.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/busses/i2c-designware.c b/drivers/i2c/busses/i2c-designware.c index 33f89148f0..bb9a0b7c4a 100644 --- a/drivers/i2c/busses/i2c-designware.c +++ b/drivers/i2c/busses/i2c-designware.c @@ -121,6 +121,8 @@ static inline struct dw_i2c_dev *to_dw_i2c_dev(struct i2c_adapter *a) static void i2c_dw_enable(struct dw_i2c_dev *dw, bool enable) { + u32 reg = 0; + /* * This subrotine is an implementation of an algorithm * described in "Cyclone V Hard Processor System Technical @@ -128,12 +130,13 @@ static void i2c_dw_enable(struct dw_i2c_dev *dw, bool enable) */ int timeout = MAX_T_POLL_COUNT; - enable = enable ? DW_IC_ENABLE_ENABLE : 0; + if (enable) + reg |= DW_IC_ENABLE_ENABLE; do { uint32_t ic_enable_status; - writel(enable, dw->base + DW_IC_ENABLE); + writel(reg, dw->base + DW_IC_ENABLE); ic_enable_status = readl(dw->base + DW_IC_ENABLE_STATUS); if ((ic_enable_status & DW_IC_ENABLE_STATUS_IC_EN) == enable) -- cgit v1.2.3 From f5c5f8ae51342c8954fc500d1f47199021d827da Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Sat, 11 Jul 2020 06:47:01 +0200 Subject: treewide: Convert files covered by ARM copyright to SPDX MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to Marc Zyngier, former employee at ARM, the company owns the copyright for code created by its employees. Convert accordingly to SPDX with the usual rearrangements. Also dropped Marc's email address which doesn't work any more. Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/include/asm/esr.h | 6 ++---- arch/arm/include/asm/psci.h | 6 ++---- arch/arm/lib64/copy_template.S | 20 ++++-------------- arch/arm/lib64/memcpy.S | 19 ++++------------- arch/arm/lib64/memset.S | 19 ++++------------- arch/arm/mach-versatile/include/mach/platform.h | 18 +++-------------- drivers/clk/vexpress/clk-sp810.c | 4 +--- drivers/i2c/busses/i2c-versatile.c | 13 ++++++------ drivers/serial/serial_pl010.c | 27 ++++++------------------- drivers/serial/serial_pl010.h | 23 +++++---------------- include/linux/amba/serial.h | 19 +++++------------ include/linux/clk.h | 9 ++++----- 12 files changed, 46 insertions(+), 137 deletions(-) (limited to 'drivers') diff --git a/arch/arm/include/asm/esr.h b/arch/arm/include/asm/esr.h index 7c3341bce7..52347b6862 100644 --- a/arch/arm/include/asm/esr.h +++ b/arch/arm/include/asm/esr.h @@ -1,9 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-FileCopyrightText: 2013 ARM Ltd */ -/* - * Copyright (C) 2013 - ARM Ltd - * Author: Marc Zyngier - */ +/* Author: Marc Zyngier */ #ifndef __ASM_ESR_H #define __ASM_ESR_H diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h index 4bfac3a17e..3c1d046eb9 100644 --- a/arch/arm/include/asm/psci.h +++ b/arch/arm/include/asm/psci.h @@ -1,9 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-FileCopyrightText: 2013 ARM Ltd */ -/* - * Copyright (C) 2013 - ARM Ltd - * Author: Marc Zyngier - */ +/* Author: Marc Zyngier */ #ifndef __ARM_PSCI_H__ #define __ARM_PSCI_H__ diff --git a/arch/arm/lib64/copy_template.S b/arch/arm/lib64/copy_template.S index cc9a84260d..8e4ff059d1 100644 --- a/arch/arm/lib64/copy_template.S +++ b/arch/arm/lib64/copy_template.S @@ -1,28 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-FileCopyrightText: 2013 ARM Ltd. */ +/* SPDX-FileCopyrightText: 2013 Linaro */ + /* - * Copyright (C) 2013 ARM Ltd. - * Copyright (C) 2013 Linaro. - * * This code is based on glibc cortex strings work originally authored by Linaro * and re-licensed under GPLv2 for the Linux kernel. The original code can * be found @ * * http://bazaar.launchpad.net/~linaro-toolchain-dev/cortex-strings/trunk/ * files/head:/src/aarch64/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . */ - /* * Copy a buffer from src to dest (alignment handled by the hardware) * diff --git a/arch/arm/lib64/memcpy.S b/arch/arm/lib64/memcpy.S index a70e96ca29..92845b25a6 100644 --- a/arch/arm/lib64/memcpy.S +++ b/arch/arm/lib64/memcpy.S @@ -1,25 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-FileCopyrightText: 2013 ARM Ltd. */ +/* SPDX-FileCopyrightText: 2013 Linaro */ + /* - * Copyright (C) 2013 ARM Ltd. - * Copyright (C) 2013 Linaro. - * * This code is based on glibc cortex strings work originally authored by Linaro * and re-licensed under GPLv2 for the Linux kernel. The original code can * be found @ * * http://bazaar.launchpad.net/~linaro-toolchain-dev/cortex-strings/trunk/ * files/head:/src/aarch64/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . */ #include diff --git a/arch/arm/lib64/memset.S b/arch/arm/lib64/memset.S index d17bcc6125..ff201750f1 100644 --- a/arch/arm/lib64/memset.S +++ b/arch/arm/lib64/memset.S @@ -1,25 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-FileCopyrightText: 2013 ARM Ltd. */ +/* SPDX-FileCopyrightText: 2013 Linaro */ + /* - * Copyright (C) 2013 ARM Ltd. - * Copyright (C) 2013 Linaro. - * * This code is based on glibc cortex strings work originally authored by Linaro * and re-licensed under GPLv2 for the Linux kernel. The original code can * be found @ * * http://bazaar.launchpad.net/~linaro-toolchain-dev/cortex-strings/trunk/ * files/head:/src/aarch64/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . */ #include diff --git a/arch/arm/mach-versatile/include/mach/platform.h b/arch/arm/mach-versatile/include/mach/platform.h index 29c4d922b0..6f4b00360f 100644 --- a/arch/arm/mach-versatile/include/mach/platform.h +++ b/arch/arm/mach-versatile/include/mach/platform.h @@ -1,21 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2003 ARM Limited */ + /* - * ach-arm926ejs/include/mach/platform.h - * * Borrowed from Linux v2.6.35 * arch/arm/mach-versatile/include/mach/platform.h - * - * Copyright (c) ARM Limited 2003. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #ifndef __address_h diff --git a/drivers/clk/vexpress/clk-sp810.c b/drivers/clk/vexpress/clk-sp810.c index 78ec67fd15..968921203b 100644 --- a/drivers/clk/vexpress/clk-sp810.c +++ b/drivers/clk/vexpress/clk-sp810.c @@ -1,7 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 ARM Limited - */ +// SPDX-FileCopyrightText: 2013 ARM Limited #include #include diff --git a/drivers/i2c/busses/i2c-versatile.c b/drivers/i2c/busses/i2c-versatile.c index 6a00c2a2eb..ece483f6f5 100644 --- a/drivers/i2c/busses/i2c-versatile.c +++ b/drivers/i2c/busses/i2c-versatile.c @@ -1,13 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2006 ARM Ltd. + /* - * i2c-versatile.c - * - * Copyright (C) 2006 ARM Ltd. - * written by Russell King, Deep Blue Solutions Ltd. + * i2c-versatile.c * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * written by Russell King, Deep Blue Solutions Ltd. */ + #include #include #include diff --git a/drivers/serial/serial_pl010.c b/drivers/serial/serial_pl010.c index 74a0c81d3e..f2cf944e8f 100644 --- a/drivers/serial/serial_pl010.c +++ b/drivers/serial/serial_pl010.c @@ -1,24 +1,9 @@ -/* - * Copyright (C) 2010 Matthias Kaehlcke - * - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * (C) Copyright 2004 - * ARM Ltd. - * Philippe Robin, - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2000 Rob Taylor , Flying Pig Systems +// SPDX-FileCopyrightText: 2004 ARM Ltd. +// SPDX-FileCopyrightText: 2010 Matthias Kaehlcke + +/* Contributor: Philippe Robin */ /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */ diff --git a/drivers/serial/serial_pl010.h b/drivers/serial/serial_pl010.h index f442339ea3..ba81a66da0 100644 --- a/drivers/serial/serial_pl010.h +++ b/drivers/serial/serial_pl010.h @@ -1,21 +1,8 @@ -/* - * Copyright (C) 2010 Matthias Kaehlcke - * - * (C) Copyright 2003, 2004 - * ARM Ltd. - * Philippe Robin, - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2003, 2004 ARM Ltd. */ +/* SPDX-FileCopyrightText: 2010 Matthias Kaehlcke */ + +/* Contributor: Philippe Robin */ struct hldc_struct { uint32_t ctrl; diff --git a/include/linux/amba/serial.h b/include/linux/amba/serial.h index 8ff22d5c8c..88ca17c2c3 100644 --- a/include/linux/amba/serial.h +++ b/include/linux/amba/serial.h @@ -1,22 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: ARM Limited */ +/* SPDX-FileCopyrightText: 2000 Deep Blue Solutions Ltd. */ + /* * linux/include/linux/amba/serial.h * * Internal header file for AMBA serial ports - * - * Copyright (C) ARM Limited - * Copyright (C) 2000 Deep Blue Solutions Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ + #ifndef ASM_ARM_HARDWARE_SERIAL_AMBA_H #define ASM_ARM_HARDWARE_SERIAL_AMBA_H diff --git a/include/linux/clk.h b/include/linux/clk.h index a005e7233d..c53019405b 100644 --- a/include/linux/clk.h +++ b/include/linux/clk.h @@ -1,13 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-FileCopyrightText: 2004 ARM Limited */ + /* * linux/include/linux/clk.h * - * Copyright (C) 2004 ARM Limited. * Written by Deep Blue Solutions Limited. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ + #ifndef __LINUX_CLK_H #define __LINUX_CLK_H -- cgit v1.2.3