From f484dc791a3932537213c43c654cc1295c64b84c Mon Sep 17 00:00:00 2001 From: Nick Spence Date: Thu, 7 Sep 2006 07:39:46 -0700 Subject: Added RGMII support to the TSECs and Marvell 881111 Phy Added a phy initialization to adjust the RGMII RX and TX timing Always set the R100 bit in 100 BaseT mode regardless of the TSEC mode Signed-off-by: Nick Spence --- drivers/tsec.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/tsec.c b/drivers/tsec.c index 400e593adf..6815c153d8 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -610,11 +610,10 @@ static void adjust_link(struct eth_device *dev) regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) | MACCFG2_MII); - /* If We're in reduced mode, we need - * to say whether we're 10 or 100 MB. + /* Set R100 bit in all modes although + * it is only used in RGMII mode */ - if ((priv->speed == 100) - && (priv->flags & TSEC_REDUCED)) + if (priv->speed == 100) regs->ecntrl |= ECNTRL_R100; else regs->ecntrl &= ~(ECNTRL_R100); @@ -816,6 +815,7 @@ struct phy_info phy_info_M88E1111S = { {0x1d, 0x5, NULL}, {0x1e, 0x0, NULL}, {0x1e, 0x100, NULL}, + {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */ {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, -- cgit v1.2.3 From 04f899fc465c3e44f2b55ecc70618f5696fc0ddf Mon Sep 17 00:00:00 2001 From: Nick Spence Date: Sat, 30 Sep 2006 00:32:59 -0700 Subject: NAND Flash verify across block boundaries This patch addresses a problem when CONFIG_MTD_NAND_VERIFY_WRITE is defined and the write crosses a block boundary. The pointer to the verification buffer (bufstart) is not being updated to reflect the starting of the new block so the verification of the second block fails. CHANGELOG: * Fix NAND FLASH page verification across block boundaries --- drivers/nand/nand_base.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/nand/nand_base.c b/drivers/nand/nand_base.c index b7a5d32fb3..6b13c4e0e3 100644 --- a/drivers/nand/nand_base.c +++ b/drivers/nand/nand_base.c @@ -1713,6 +1713,7 @@ static int nand_write_ecc (struct mtd_info *mtd, loff_t to, size_t len, goto out; } *retlen = written; + bufstart = (u_char*) &buf[written]; ofs = autoplace ? mtd->oobavail : mtd->oobsize; if (eccbuf) -- cgit v1.2.3 From 2ad6b513b31070bd0c003792ed1c3e7f5d740357 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Tue, 31 Oct 2006 18:44:42 -0600 Subject: mpc83xx: Add support for the MPC8349E-mITX PREREQUISITE PATCHES: * This patch can only be applied after the following patches have been applied: 1) DNX#2006090742000024 "Add support for multiple I2C buses" 2) DNX#2006090742000033 "Multi-bus I2C implementation of MPC834x" 3) DNX#2006091242000041 "Additional MPC8349 support for multibus i2c" 4) DNX#2006091242000078 "Add support for variable flash memory sizes on 83xx systems" 5) DNX#2006091242000069 "Add support for Errata DDR6 on MPC 834x systems" CHANGELOG: * Add support for the Freescale MPC8349E-mITX reference design platform. The second TSEC (Vitesse 7385 switch) is not supported at this time. Signed-off-by: Timur Tabi --- CREDITS | 5 + MAINTAINERS | 4 + MAKEALL | 2 +- Makefile | 3 + README | 8 + board/mpc8349emds/pci.c | 12 +- board/mpc8349itx/Makefile | 48 +++ board/mpc8349itx/config.mk | 33 ++ board/mpc8349itx/mpc8349itx.c | 461 ++++++++++++++++++++++++++ board/mpc8349itx/pci.c | 337 +++++++++++++++++++ board/mpc8349itx/u-boot.lds | 120 +++++++ cpu/mpc83xx/cpu.c | 81 ++++- cpu/mpc83xx/cpu_init.c | 31 ++ cpu/mpc83xx/spd_sdram.c | 21 ++ drivers/tsec.c | 4 +- include/asm-ppc/immap_83xx.h | 16 + include/configs/MPC8349ITX.h | 753 ++++++++++++++++++++++++++++++++++++++++++ 17 files changed, 1926 insertions(+), 13 deletions(-) create mode 100644 board/mpc8349itx/Makefile create mode 100644 board/mpc8349itx/config.mk create mode 100644 board/mpc8349itx/mpc8349itx.c create mode 100644 board/mpc8349itx/pci.c create mode 100644 board/mpc8349itx/u-boot.lds create mode 100644 include/configs/MPC8349ITX.h (limited to 'drivers') diff --git a/CREDITS b/CREDITS index 3f7b510556..802158879f 100644 --- a/CREDITS +++ b/CREDITS @@ -465,3 +465,8 @@ N: James MacAulay E: james.macaulay@amirix.com D: Suppport for Amirix AP1000 W: www.amirix.com + +N: Timur Tabi +E: timur@freescale.com +D: Support for MPC8349E-mITX +W: www.freescale.com diff --git a/MAINTAINERS b/MAINTAINERS index 8bb38b5f2e..aaa0825090 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -339,6 +339,10 @@ John Zhan svm_sc8xx MPC8xx +Timur Tabi + + MPC8349E-mITX MPC8349 + ------------------------------------------------------------------------- Unknown / orphaned boards: diff --git a/MAKEALL b/MAKEALL index 879a17f9cc..c29dd54f93 100755 --- a/MAKEALL +++ b/MAKEALL @@ -130,7 +130,7 @@ LIST_8260=" \ ######################################################################### LIST_83xx=" \ - TQM834x MPC8349EMDS \ + TQM834x MPC8349EMDS MPC8349ITX \ " diff --git a/Makefile b/Makefile index 782893b75f..ac7ca4a561 100644 --- a/Makefile +++ b/Makefile @@ -1591,6 +1591,9 @@ TQM834x_config: unconfig MPC8349EMDS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349emds +MPC8349ITX_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349itx + ######################################################################### ## MPC85xx Systems ######################################################################### diff --git a/README b/README index 6b94f8482c..5c907c8f07 100644 --- a/README +++ b/README @@ -2249,6 +2249,14 @@ Low Level (hardware related) configuration options: If SPD EEPROM is on an I2C bus other than the first one, specify here. Note that the value must resolve to something your driver can deal with. +- CFG_83XX_DDR_USES_CS0 + Only for 83xx systems. If specified, then DDR should be configured + using CS0 and CS1 instead of CS2 and CS3. + +- CFG_83XX_DDR_USES_CS0 + Only for 83xx systems. If specified, then DDR should be configured + using CS0 and CS1 instead of CS2 and CS3. + - CONFIG_ETHER_ON_FEC[12] Define to enable FEC[12] on a 8xx series processor. diff --git a/board/mpc8349emds/pci.c b/board/mpc8349emds/pci.c index a4d6508bb0..a916245aea 100644 --- a/board/mpc8349emds/pci.c +++ b/board/mpc8349emds/pci.c @@ -138,18 +138,18 @@ void pci_init_board(void) { volatile immap_t * immr; - volatile clk8349_t * clk; - volatile law8349_t * pci_law; - volatile pot8349_t * pci_pot; - volatile pcictrl8349_t * pci_ctrl; - volatile pciconf8349_t * pci_conf; + volatile clk83xx_t * clk; + volatile law83xx_t * pci_law; + volatile pot83xx_t * pci_pot; + volatile pcictrl83xx_t * pci_ctrl; + volatile pciconf83xx_t * pci_conf; u16 reg16; u32 reg32; u32 dev; struct pci_controller * hose; immr = (immap_t *)CFG_IMMRBAR; - clk = (clk8349_t *)&immr->clk; + clk = (clk83xx_t *)&immr->clk; pci_law = immr->sysconf.pcilaw; pci_pot = immr->ios.pot; pci_ctrl = immr->pci_ctrl; diff --git a/board/mpc8349itx/Makefile b/board/mpc8349itx/Makefile new file mode 100644 index 0000000000..31bcdb8642 --- /dev/null +++ b/board/mpc8349itx/Makefile @@ -0,0 +1,48 @@ +# +# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o pci.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/mpc8349itx/config.mk b/board/mpc8349itx/config.mk new file mode 100644 index 0000000000..2e113118bd --- /dev/null +++ b/board/mpc8349itx/config.mk @@ -0,0 +1,33 @@ +# +# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MPC8349ITX +# + +TEXT_BASE = 0xFEF00000 + +ifneq ($(OBJTREE),$(SRCTREE)) +# We are building u-boot in a separate directory, use generated +# .lds script from OBJTREE directory. +LDSCRIPT := $(OBJTREE)/board/$(BOARDDIR)/u-boot.lds +endif diff --git a/board/mpc8349itx/mpc8349itx.c b/board/mpc8349itx/mpc8349itx.c new file mode 100644 index 0000000000..9a5cbec858 --- /dev/null +++ b/board/mpc8349itx/mpc8349itx.c @@ -0,0 +1,461 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_PCI +#include +#include +#endif + +#ifdef CONFIG_SPD_EEPROM +#include +#else +#include +#endif + +#ifndef CONFIG_SPD_EEPROM +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +int fixed_sdram(void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMRBAR; + u32 ddr_size; /* The size of RAM, in bytes */ + u32 ddr_size_log2 = 0; + + for (ddr_size = CFG_DDR_SIZE * 0x100000; ddr_size > 1; ddr_size >>= 1) { + if (ddr_size & 1) { + return -1; + } + ddr_size_log2++; + } + + im->sysconf.ddrlaw[0].ar = + LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); + im->sysconf.ddrlaw[0].bar = (CFG_DDR_SDRAM_BASE >> 12) & 0xfffff; + + /* Only one CS0 for DDR */ + im->ddr.csbnds[0].csbnds = 0x0000000f; + im->ddr.cs_config[0] = CFG_DDR_CONFIG; + + debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds); + debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]); + + debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar); + debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar); + + im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */ + im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR; + im->ddr.sdram_mode = + (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT); + im->ddr.sdram_interval = + (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 << + SDRAM_INTERVAL_BSTOPRE_SHIFT); + im->ddr.sdram_clk_cntl = + DDR_SDRAM_CLK_CNTL_SS_EN | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05; + + udelay(200); + + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + + debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1); + debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2); + debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode); + debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval); + debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg); + + return CFG_DDR_SIZE; +} +#endif + +#ifdef CONFIG_PCI +/* + * Initialize PCI Devices, report devices found + */ +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc83xxmitx_config_table[] = { + { + PCI_ANY_ID, + PCI_ANY_ID, + PCI_ANY_ID, + PCI_ANY_ID, + 0x0f, + PCI_ANY_ID, + pci_cfgfunc_config_device, + { + PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} + }, + {} +} +#endif + +volatile static struct pci_controller hose[] = { + { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc83xxmitx_config_table, +#endif + }, + { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc83xxmitx_config_table, +#endif + } +}; +#endif /* CONFIG_PCI */ + +/* If MPC8349E-mITX is soldered with SDRAM, then initialize it. +*/ + +void sdram_init(void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMRBAR; + volatile lbus83xx_t *lbc = &immap->lbus; + +#if defined(CFG_BR2_PRELIM) \ + && defined(CFG_OR2_PRELIM) \ + && defined(CFG_LBLAWBAR2_PRELIM) \ + && defined(CFG_LBLAWAR2_PRELIM) \ + && !defined(CONFIG_COMPACT_FLASH) + + uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE; + + puts("\n SDRAM on Local Bus: "); + print_size(CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + + /* + * Setup SDRAM Base and Option Registers, already done in cpu_init.c + */ + + /*setup mtrpt, lsrt and lbcr for LB bus */ + lbc->lbcr = CFG_LBC_LBCR; + lbc->mrtpr = CFG_LBC_MRTPR; + lbc->lsrt = CFG_LBC_LSRT; + asm("sync"); + + /* + * Configure the SDRAM controller Machine Mode register. + */ + lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ + + lbc->lsdmr = CFG_LBC_LSDMR_1; /*0x68636733; precharge all the banks */ + asm("sync"); + *sdram_addr = 0xff; + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_2; /*0x48636733; auto refresh */ + asm("sync"); + *sdram_addr = 0xff; /*1 time*/ + udelay(100); + *sdram_addr = 0xff; /*2 times*/ + udelay(100); + *sdram_addr = 0xff; /*3 times*/ + udelay(100); + *sdram_addr = 0xff; /*4 times*/ + udelay(100); + *sdram_addr = 0xff; /*5 times*/ + udelay(100); + *sdram_addr = 0xff; /*6 times*/ + udelay(100); + *sdram_addr = 0xff; /*7 times*/ + udelay(100); + *sdram_addr = 0xff; /*8 times*/ + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_4; /*0x58636733;mode register write operation */ + asm("sync"); + *sdram_addr = 0xff; + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_5; /*0x40636733;normal operation */ + asm("sync"); + *sdram_addr = 0xff; + udelay(100); + +#else + puts("SDRAM on Local Bus is NOT available!\n"); + +#ifdef CFG_BR2_PRELIM + lbc->bank[2].br = CFG_BR2_PRELIM; + lbc->bank[2].or = CFG_OR2_PRELIM; +#endif + +#ifdef CFG_BR3_PRELIM + lbc->bank[3].br = CFG_BR3_PRELIM; + lbc->bank[3].or = CFG_OR3_PRELIM; +#endif +#endif +} + +long int initdram(int board_type) +{ + volatile immap_t *im = (immap_t *) CFG_IMMRBAR; + u32 msize = 0; +#ifdef CONFIG_DDR_ECC + volatile ddr83xx_t *ddr = &im->ddr; +#endif + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) + return -1; + + /* DDR SDRAM - Main SODIMM */ + im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; +#ifdef CONFIG_SPD_EEPROM + msize = spd_sdram(); +#else + msize = fixed_sdram(); +#endif + +#ifdef CONFIG_DDR_ECC + if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) + /* Unlike every other board, on the 83xx spd_sdram() returns + megabytes instead of just bytes. That's why we need to + multiple by 1MB when calling ddr_enable_ecc(). */ + ddr_enable_ecc(msize * 1048576); +#endif + + /* + * Initialize SDRAM if it is on local bus. + */ + sdram_init(); + puts(" DDR RAM: "); + /* return total bus SDRAM size(bytes) -- DDR */ + return msize * 1024 * 1024; +} + +int checkboard(void) +{ +#ifdef CONFIG_HARD_I2C + u8 i2c_data; +#endif + + puts("Board: Freescale MPC8349E-mITX"); + +#ifdef CONFIG_HARD_I2C + i2c_set_bus_num(I2C_BUS_2); + if (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == + 0) + printf(" %u.%u (PCF8475A)", (i2c_data & 0x02) >> 1, + i2c_data & 0x01); + else if (i2c_read(CFG_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) + == 0) + printf(" %u.%u (PCF8475)", (i2c_data & 0x02) >> 1, + i2c_data & 0x01); + else + printf(" ?.?"); +#endif + + puts("\n"); + + return 0; +} + +/** + * Implement a work-around for a hardware problem with compact + * flash. + * + * Program the UPM if compact flash is enabled. + */ +int misc_init_f(void) +{ + volatile u32 *vsc7385_cpuctrl; + + /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up + default of VSC7385 L1_IRQ and L2_IRQ requests are active high. That + means it is 0 when the IRQ is not active. This makes the wire-AND + logic always assert IRQ7 to CPU even if there is no request from the + switch. Since the compact flash and the switch share the same IRQ, + the Linux kernel will think that the compact flash is requesting irq + and get stuck when it tries to clear the IRQ. Thus we need to set + the L2_IRQ0 and L2_IRQ1 to active low. + + The following code sets the L1_IRQ and L2_IRQ polarity to active low. + Without this code, compact flash will not work in Linux because + unlike U-Boot, Linux uses the IRQ, so this code is necessary if we + don't enable compact flash for U-Boot. + */ + + vsc7385_cpuctrl = (volatile u32 *)(CFG_VSC7385_BASE + 0x1c0c0); + *vsc7385_cpuctrl |= 0x0c; + +#ifdef CONFIG_COMPACT_FLASH + /* UPM Table Configuration Code */ + static uint UPMATable[] = { + 0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00, + 0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + 0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00, + 0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 + }; + volatile immap_t *immap = (immap_t *) CFG_IMMRBAR; + volatile lbus83xx_t *lbus = &immap->lbus; + + lbus->bank[3].br = CFG_BR3_PRELIM; + lbus->bank[3].or = CFG_OR3_PRELIM; + + /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000, + GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000 + */ + lbus->mamr = 0x08404440; + + upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0])); + + puts("UPMA: Configured for compact flash\n"); +#endif + + return 0; +} + +/** + * Make sure the EEPROM has the HRCW correctly programmed. + * Make sure the RTC is correctly programmed. + * + * The MPC8349E-mITX can be configured to load the HRCW from + * EEPROM instead of flash. This is controlled via jumpers + * LGPL0, 1, and 3. Normally, these jumpers are set to 000 (all + * jumpered), but if they're set to 001 or 010, then the HRCW is + * read from the "I2C EEPROM". + * + * This function makes sure that the I2C EEPROM is programmed + * correctly. + */ +int misc_init_r(void) +{ + int rc = 0; + +#ifdef CONFIG_HARD_I2C + + uchar orig_bus = i2c_get_bus_num();; + +#ifdef CFG_I2C_RTC_ADDR + char ds1339_data[17]; +#endif + +#ifdef CFG_I2C_EEPROM_ADDR + static u8 eeprom_data[] = /* HRCW data */ + { + 0xaa, 0x55, 0xaa, + 0x7c, 0x02, 0x40, 0x05, 0x04, 0x00, 0x00, + 0x7c, 0x02, 0x41, 0xb4, 0x60, 0xa0, 0x00, + }; + + u8 data[sizeof(eeprom_data)]; + + i2c_set_bus_num(I2C_BUS_1); + + if (i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) { + if (memcmp(data, eeprom_data, sizeof(data)) != 0) { + if (i2c_write + (CFG_I2C_EEPROM_ADDR, 0, 2, eeprom_data, + sizeof(eeprom_data)) != 0) { + puts("Failure writing the HRCW to EEPROM via I2C.\n"); + rc = 1; + } + } + } else { + puts("Failure reading the HRCW from EEPROM via I2C.\n"); + rc = 1; + } +#endif + +#ifdef CFG_I2C_RTC_ADDR + i2c_set_bus_num(I2C_BUS_2); + + if (i2c_read(CFG_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data)) + == 0) { + + /* Work-around for MPC8349E-mITX bug #13601. + If the RTC does not contain valid register values, the DS1339 + Linux driver will not work. + */ + + /* Make sure status register bits 6-2 are zero */ + ds1339_data[0x0f] &= ~0x7c; + + /* Check for a valid day register value */ + ds1339_data[0x03] &= ~0xf8; + if (ds1339_data[0x03] == 0) { + ds1339_data[0x03] = 1; + } + + /* Check for a valid date register value */ + ds1339_data[0x04] &= ~0xc0; + if ((ds1339_data[0x04] == 0) || + ((ds1339_data[0x04] & 0x0f) > 9) || + (ds1339_data[0x04] >= 0x32)) { + ds1339_data[0x04] = 1; + } + + /* Check for a valid month register value */ + ds1339_data[0x05] &= ~0x60; + + if ((ds1339_data[0x05] == 0) || + ((ds1339_data[0x05] & 0x0f) > 9) || + ((ds1339_data[0x05] >= 0x13) + && (ds1339_data[0x05] <= 0x19))) { + ds1339_data[0x05] = 1; + } + + /* Enable Oscillator and rate select */ + ds1339_data[0x0e] = 0x1c; + + /* Work-around for MPC8349E-mITX bug #13330. + Ensure that the RTC control register contains the value 0x1c. + This affects SATA performance. + */ + + if (i2c_write + (CFG_I2C_RTC_ADDR, 0, 1, ds1339_data, + sizeof(ds1339_data))) { + puts("Failure writing to the RTC via I2C.\n"); + rc = 1; + } + } else { + puts("Failure reading from the RTC via I2C.\n"); + rc = 1; + } +#endif + + i2c_set_bus_num(orig_bus); +#endif + + return rc; +} diff --git a/board/mpc8349itx/pci.c b/board/mpc8349itx/pci.c new file mode 100644 index 0000000000..247b3a6ecc --- /dev/null +++ b/board/mpc8349itx/pci.c @@ -0,0 +1,337 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CONFIG_PCI + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* System RAM mapped to PCI space */ +#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc8349itx_config_table[] = { + { + PCI_ANY_ID, + PCI_ANY_ID, + PCI_ANY_ID, + PCI_ANY_ID, + PCI_IDSEL_NUMBER, + PCI_ANY_ID, + pci_cfgfunc_config_device, + { + PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} + }, + {} +}; +#endif + +static struct pci_controller pci_hose[] = { + { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc8349itx_config_table, +#endif + }, + { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc8349itx_config_table, +#endif + } +}; + +/************************************************************************** + * pci_init_board() + * + * NOTICE: PCI2 is not currently supported + * + */ +void pci_init_board(void) +{ + volatile immap_t *immr; + volatile clk83xx_t *clk; + volatile law83xx_t *pci_law; + volatile pot83xx_t *pci_pot; + volatile pcictrl83xx_t *pci_ctrl; + volatile pciconf83xx_t *pci_conf; + u8 reg8; + u16 reg16; + u32 reg32; + u32 dev; + struct pci_controller *hose; + + immr = (immap_t *) CFG_IMMRBAR; + clk = (clk83xx_t *) & immr->clk; + pci_law = immr->sysconf.pcilaw; + pci_pot = immr->ios.pot; + pci_ctrl = immr->pci_ctrl; + pci_conf = immr->pci_conf; + + hose = &pci_hose[0]; + + /* + * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode + */ + + reg32 = clk->occr; + udelay(2000); + +#ifdef CONFIG_HARD_I2C + i2c_set_bus_num(I2C_BUS_2); + /* Read the PCI_M66EN jumper setting */ + if ((i2c_read(CFG_I2C_8574_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0) || + (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0)) { + if (reg8 & I2C_8574_PCI66) + clk->occr = 0xff000000; /* 66 MHz PCI */ + else + clk->occr = 0xff600001; /* 33 MHz PCI */ + } else { + clk->occr = 0xff600001; /* 33 MHz PCI */ + } +#else + clk->occr = 0xff000000; /* 66 MHz PCI */ +#endif + + udelay(2000); + + /* + * Release PCI RST Output signal + */ + pci_ctrl[0].gcr = 0; + udelay(2000); + pci_ctrl[0].gcr = 1; + +#ifdef CONFIG_MPC83XX_PCI2 + pci_ctrl[1].gcr = 0; + udelay(2000); + pci_ctrl[1].gcr = 1; +#endif + + /* We need to wait at least a 1sec based on PCI specs */ + { + int i; + + for (i = 0; i < 1000; i++) + udelay(1000); + } + + /* + * Configure PCI Local Access Windows + */ + pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; + + pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; + + /* + * Configure PCI Outbound Translation Windows + */ + + /* PCI1 mem space - prefetch */ + pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[0].pocmr = + POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); + + /* PCI1 IO space */ + pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); + + /* PCI1 mmio - non-prefetch mem space */ + pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); + + /* + * Configure PCI Inbound Translation Windows + */ + + /* we need RAM mapped to PCI space for the devices to + * access main memory */ + pci_ctrl[0].pitar1 = 0x0; + pci_ctrl[0].pibar1 = 0x0; + pci_ctrl[0].piebar1 = 0x0; + pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | + PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); + + hose->first_busno = 0; + hose->last_busno = 0xff; + + /* PCI memory prefetch space */ + pci_set_region(hose->regions + 0, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); + + /* PCI memory space */ + pci_set_region(hose->regions + 1, + CFG_PCI1_MMIO_BASE, + CFG_PCI1_MMIO_PHYS, CFG_PCI1_MMIO_SIZE, PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(hose->regions + 2, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO); + + /* System memory space */ + pci_set_region(hose->regions + 3, + CONFIG_PCI_SYS_MEM_BUS, + CONFIG_PCI_SYS_MEM_PHYS, + gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY); + + hose->region_count = 4; + + pci_setup_indirect(hose, + (CFG_IMMRBAR + 0x8300), (CFG_IMMRBAR + 0x8304)); + + pci_register_hose(hose); + + /* + * Write to Command register + */ + reg16 = 0xff; + dev = PCI_BDF(hose->first_busno, 0, 0); + pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + +#ifdef CONFIG_PCI_SCAN_SHOW + printf("PCI: Bus Dev VenId DevId Class Int\n"); +#endif + /* + * Hose scan. + */ + hose->last_busno = pci_hose_scan(hose); + +#ifdef CONFIG_MPC83XX_PCI2 + hose = &pci_hose[1]; + + /* + * Configure PCI Outbound Translation Windows + */ + + /* PCI2 mem space - prefetch */ + pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[3].pocmr = + POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & + POCMR_CM_MASK); + + /* PCI2 IO space */ + pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[4].pocmr = + POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); + + /* PCI2 mmio - non-prefetch mem space */ + pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[5].pocmr = + POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK); + + /* + * Configure PCI Inbound Translation Windows + */ + + /* we need RAM mapped to PCI space for the devices to + * access main memory */ + pci_ctrl[1].pitar1 = 0x0; + pci_ctrl[1].pibar1 = 0x0; + pci_ctrl[1].piebar1 = 0x0; + pci_ctrl[1].piwar1 = + PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | + (__ilog2(gd->ram_size) - 1); + + hose->first_busno = pci_hose[0].last_busno + 1; + hose->last_busno = 0xff; + + /* PCI memory prefetch space */ + pci_set_region(hose->regions + 0, + CFG_PCI2_MEM_BASE, + CFG_PCI2_MEM_PHYS, + CFG_PCI2_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); + + /* PCI memory space */ + pci_set_region(hose->regions + 1, + CFG_PCI2_MMIO_BASE, + CFG_PCI2_MMIO_PHYS, CFG_PCI2_MMIO_SIZE, PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(hose->regions + 2, + CFG_PCI2_IO_BASE, + CFG_PCI2_IO_PHYS, CFG_PCI2_IO_SIZE, PCI_REGION_IO); + + /* System memory space */ + pci_set_region(hose->regions + 3, + CONFIG_PCI_SYS_MEM_BUS, + CONFIG_PCI_SYS_MEM_PHYS, + gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY); + + hose->region_count = 4; + + pci_setup_indirect(hose, + (CFG_IMMRBAR + 0x8380), (CFG_IMMRBAR + 0x8384)); + + pci_register_hose(hose); + + /* + * Write to Command register + */ + reg16 = 0xff; + dev = PCI_BDF(hose->first_busno, 0, 0); + pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + + /* + * Hose scan. + */ + hose->last_busno = pci_hose_scan(hose); +#endif +} + +#endif /* CONFIG_PCI */ diff --git a/board/mpc8349itx/u-boot.lds b/board/mpc8349itx/u-boot.lds new file mode 100644 index 0000000000..f044c0f00e --- /dev/null +++ b/board/mpc8349itx/u-boot.lds @@ -0,0 +1,120 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc83xx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 8d543d5c99..4e82a8b789 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -69,9 +69,72 @@ int checkcpu(void) } +/** + * Program a UPM with the code supplied in the table. + * + * The 'dummy' variable is used to increment the MAD. 'dummy' is + * supposed to be a pointer to the memory of the device being + * programmed by the UPM. The data in the MDR is written into + * memory and the MAD is incremented every time there's a read + * from 'dummy'. Unfortunately, the current prototype for this + * function doesn't allow for passing the address of this + * device, and changing the prototype will break a number lots + * of other code, so we need to use a round-about way of finding + * the value for 'dummy'. + * + * The value can be extracted from the base address bits of the + * Base Register (BR) associated with the specific UPM. To find + * that BR, we need to scan all 8 BRs until we find the one that + * has its MSEL bits matching the UPM we want. Once we know the + * right BR, we can extract the base address bits from it. + * + * The MxMR and the BR and OR of the chosen bank should all be + * configured before calling this function. + * + * Parameters: + * upm: 0=UPMA, 1=UPMB, 2=UPMC + * table: Pointer to an array of values to program + * size: Number of elements in the array. Must be 64 or less. +*/ void upmconfig (uint upm, uint *table, uint size) { - hang(); /* FIXME: upconfig() needed? */ +#if defined(CONFIG_MPC834X) + volatile immap_t *immap = (immap_t *) CFG_IMMRBAR; + volatile lbus83xx_t *lbus = &immap->lbus; + volatile uchar *dummy = NULL; + const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */ + volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */ + uint i; + + /* Scan all the banks to determine the base address of the device */ + for (i = 0; i < 8; i++) { + if ((lbus->bank[i].br & BR_MSEL) == msel) { + dummy = (uchar *) (lbus->bank[i].br & BR_BA); + break; + } + } + + if (!dummy) { + printf("Error: %s() could not find matching BR\n", __FUNCTION__); + hang(); + } + + /* Set the OP field in the MxMR to "write" and the MAD field to 000000 */ + *mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000; + + for (i = 0; i < size; i++) { + lbus->mdr = table[i]; + __asm__ __volatile__ ("sync"); + *dummy; /* Write the value to memory and increment MAD */ + __asm__ __volatile__ ("sync"); + } + + /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */ + *mxmr &= 0xCFFFFFC0; +#else + printf("Error: %s() not defined for this configuration.\n", __FUNCTION__); + hang(); +#endif } @@ -150,9 +213,21 @@ unsigned long get_tbclk(void) #if defined(CONFIG_WATCHDOG) void watchdog_reset (void) { - hang(); /* FIXME: implement watchdog_reset()? */ +#ifdef CONFIG_MPC834X + int re_enable = disable_interrupts(); + + /* Reset the 83xx watchdog */ + volatile immap_t *immr = (immap_t *) CFG_IMMRBAR; + immr->wdt.swsrr = 0x556c; + immr->wdt.swsrr = 0xaa39; + + if (re_enable) + enable_interrupts (); +#else + hang(); +#endif } -#endif /* CONFIG_WATCHDOG */ +#endif #if defined(CONFIG_OF_FLAT_TREE) void diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index 6ed0992c07..999fe71964 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -46,6 +46,37 @@ void cpu_init_f (volatile immap_t * im) /* Clear initial global data */ memset ((void *) gd, 0, sizeof (gd_t)); + /* system performance tweaking */ + +#ifdef CFG_ACR_PIPE_DEP + /* Arbiter pipeline depth */ + im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | (3 << ACR_PIPE_DEP_SHIFT); +#endif + +#ifdef CFG_SPCR_TSEC1EP + /* TSEC1 Emergency priority */ + im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | (3 << SPCR_TSEC1EP_SHIFT); +#endif + +#ifdef CFG_SPCR_TSEC2EP + /* TSEC2 Emergency priority */ + im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | (3 << SPCR_TSEC2EP_SHIFT); +#endif + +#ifdef CFG_SCCR_TSEC1CM + /* TSEC1 clock mode */ + im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (1 << SCCR_TSEC1CM_SHIFT); +#endif +#ifdef CFG_SCCR_TSEC2CM + /* TSEC2 & I2C1 clock mode */ + im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | (1 << SCCR_TSEC2CM_SHIFT); +#endif + +#ifdef CFG_ACR_RPTCNT + /* Arbiter repeat count */ + im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | (3 << ACR_RPTCNT_SHIFT)); +#endif + /* RSR - Reset Status Register - clear all status (4.6.1.3) */ gd->reset_status = im->reset.rsr; im->reset.rsr = ~(RSR_RES); diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index 8ee4234631..3dfde8ac04 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -133,6 +133,26 @@ long int spd_sdram() /* Read SPD parameters with I2C */ +#ifdef CFG_83XX_DDR_USES_CS0 + ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1; + ddr->cs_config[0] = ( 1 << 31 + | (spd.nrow_addr - 12) << 8 + | (spd.ncol_addr - 8) ); + debug("\n"); + debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds); + debug("cs0_config = 0x%08x\n",ddr->cs_config[0]); + + if (spd.nrows == 2) { + ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8) + | ((banksize(spd.row_dens) >> 23) - 1) ); + ddr->cs_config[1] = ( 1<<31 + | (spd.nrow_addr-12) << 8 + | (spd.ncol_addr-8) ); + debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds); + debug("cs1_config = 0x%08x\n",ddr->cs_config[1]); + } + +#else CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd)); #ifdef SPD_DEBUG spd_debug(&spd); @@ -180,6 +200,7 @@ long int spd_sdram() debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds); debug("cs3_config = 0x%08x\n",ddr->cs_config[3]); } +#endif if (spd.mem_type != 0x07) { puts("No DDR module found!\n"); diff --git a/drivers/tsec.c b/drivers/tsec.c index 6815c153d8..2524e4f6d2 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -1110,10 +1110,8 @@ struct phy_info phy_info_dp83865 = { }; struct phy_info *phy_info[] = { -#if 0 - &phy_info_cis8201, -#endif &phy_info_cis8204, + &phy_info_cis8201, &phy_info_M88E1011S, &phy_info_M88E1111S, &phy_info_M88E1145, diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index 40624e8291..bc6196cc88 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -82,15 +82,25 @@ typedef struct sysconf83xx { u8 res5[0x04]; u32 spcr; /* System Priority Configuration Register */ #define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable. */ +#define SPCR_PCIHPE_SHIFT (31-3) #define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority. */ +#define SPCR_PCIPR_SHIFT (31-7) #define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable. */ +#define SPCR_TBEN_SHIFT (31-9) #define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority. */ +#define SPCR_COREPR_SHIFT (31-11) #define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority. */ +#define SPCR_TSEC1DP_SHIFT (31-19) #define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority. */ +#define SPCR_TSEC1BDP_SHIFT (31-21) #define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority. */ +#define SPCR_TSEC1EP_SHIFT (31-23) #define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority. */ +#define SPCR_TSEC2DP_SHIFT (31-27) #define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority. */ +#define SPCR_TSEC2BDP_SHIFT (31-29) #define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority. */ +#define SPCR_TSEC2EP_SHIFT (31-31) #define SPCR_RES ~(SPCR_PCIHPE | SPCR_PCIPR | SPCR_TBEN | SPCR_COREPR \ | SPCR_TSEC1DP | SPCR_TSEC1BDP | SPCR_TSEC1EP \ | SPCR_TSEC2DP | SPCR_TSEC2BDP | SPCR_TSEC2EP) @@ -416,11 +426,17 @@ typedef struct ipic83xx { typedef struct arbiter83xx { u32 acr; /* Arbiter Configuration Register */ #define ACR_COREDIS 0x10000000 /* Core disable. */ +#define ACR_COREDIS_SHIFT (31-7) #define ACR_PIPE_DEP 0x00070000 /* Pipeline depth (number of outstanding transactions). */ +#define ACR_PIPE_DEP_SHIFT (31-15) #define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count. */ +#define ACR_PCI_RPTCNT_SHIFT (31-19) #define ACR_RPTCNT 0x00000700 /* Repeat count. */ +#define ACR_RPTCNT_SHIFT (31-23) #define ACR_APARK 0x00000030 /* Address parking. */ +#define ACR_APARK_SHIFT (31-27) #define ACR_PARKM 0x0000000F /* Parking master. */ +#define ACR_PARKM_SHIFT (31-31) #define ACR_RES ~(ACR_COREDIS|ACR_PIPE_DEP|ACR_PCI_RPTCNT|ACR_RPTCNT|ACR_APARK|ACR_PARKM) u32 atr; /* Arbiter Timers Register */ #define ATR_DTO 0x00FF0000 /* Data time out. */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h new file mode 100644 index 0000000000..aed350fe09 --- /dev/null +++ b/include/configs/MPC8349ITX.h @@ -0,0 +1,753 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + MPC8349E-mITX board configuration file + + Memory map: + + 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) + 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) + 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) + 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) + 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) + 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) + 0xF000_0000-0xF000_FFFF Compact Flash + 0xF001_0000-0xF001_FFFF Local bus expansion slot + 0xF800_0000-0xF801_FFFF GBE L2 Switch VSC7385 + 0xFF00_0000-0xFF7F_FFFF Alternative bank of Flash memory (8MB) + 0xFF80_0000-0xFFFF_FFFF Boot Flash (8 MB) + + I2C address list: + Align. Board + Bus Addr Part No. Description Length Location + ---------------------------------------------------------------- + I2C1 0x50 M24256-BWMN6P Board EEPROM 2 U64 + + I2C2 0x20 PCF8574 I2C Expander 0 U8 + I2C2 0x21 PCF8574 I2C Expander 0 U10 + I2C2 0x38 PCF8574A I2C Expander 0 U8 + I2C2 0x39 PCF8574A I2C Expander 0 U10 + I2C2 0x51 (DDR) DDR EEPROM 1 U1 + I2C2 0x68 DS1339 RTC 1 U68 + + Note that a given board has *either* a pair of 8574s or a pair of 8574As. +*/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef DEBUG + +/* + * High Level Configuration Options + */ +#define CONFIG_MPC834X /* MPC834x family (8343, 8347, 8349) */ +#define CONFIG_MPC8349 /* MPC8349 specific */ + +#define CONFIG_PCI + +#define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */ +#define CONFIG_RTC_DS1337 + +/* I2C */ +#define CONFIG_HARD_I2C + +#ifdef CONFIG_HARD_I2C + +#define CONFIG_MISC_INIT_F +#define CONFIG_MISC_INIT_R + +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CFG_I2C_OFFSET 0x3000 +#define CFG_I2C2_OFFSET 0x3100 +#define CFG_SPD_BUS_NUM I2C_2 + +#define CFG_I2C_8574_ADDR1 0x20 /* I2C2, PCF8574 */ +#define CFG_I2C_8574_ADDR2 0x21 /* I2C2, PCF8574 */ +#define CFG_I2C_8574A_ADDR1 0x38 /* I2C2, PCF8574A */ +#define CFG_I2C_8574A_ADDR2 0x39 /* I2C2, PCF8574A */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C1, Board EEPROM */ +#define CFG_I2C_RTC_ADDR 0x68 /* I2C2, DS1339 RTC*/ +#define SPD_EEPROM_ADDRESS 0x51 /* I2C2, DDR */ + +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +/* Don't probe these addresses: */ +#define CFG_I2C_NOPROBES {{1, CFG_I2C_8574_ADDR1}, \ + {1, CFG_I2C_8574_ADDR2}, \ + {1, CFG_I2C_8574A_ADDR1}, \ + {1, CFG_I2C_8574A_ADDR2}} +/* Bit definitions for the 8574[A] I2C expander */ +#define I2C_8574_REVISION 0x03 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ +#define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ +#define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ +#define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ +#define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ + +#undef CONFIG_SOFT_I2C + +#endif + +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE + +#define PCI_66M +#ifdef PCI_66M +#define CONFIG_83XX_CLKIN 66666666 /* in Hz */ +#else +#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ +#endif + +#ifndef CONFIG_SYS_CLK_FREQ +#ifdef PCI_66M +#define CONFIG_SYS_CLK_FREQ 66666666 +#else +#define CONFIG_SYS_CLK_FREQ 33333333 +#endif +#endif + +#define CFG_IMMRBAR 0xE0000000 /* The IMMR is relocated to here */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00003000 /* memtest region */ +#define CFG_MEMTEST_END 0x07100000 /* only has 128M */ + +/* + * DDR Setup + */ +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +#undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ +#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ + +/* + * 32-bit data path mode. + * + * Please note that using this mode for devices with the real density of 64-bit + * effectively reduces the amount of available memory due to the effect of + * wrapping around while translating address to row/columns, for example in the + * 256MB module the upper 128MB get aliased with contents of the lower + * 128MB); normally this define should be used for devices with real 32-bit + * data path. + */ +#undef CONFIG_DDR_32BIT + +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE +#undef CONFIG_DDR_2T_TIMING +#define CFG_83XX_DDR_USES_CS0 + +#ifndef CONFIG_SPD_EEPROM +/* + * Manually set up DDR parameters + */ + #define CFG_DDR_SIZE 256 /* Mb */ + #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) + + #define CFG_DDR_TIMING_1 0x26242321 + #define CFG_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ +#endif + +/* FLASH on the Local Bus */ +#define CFG_FLASH_CFI /* use the Common Flash Interface */ +#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ +#define CFG_FLASH_SIZE 16 /* FLASH size in MB */ + +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V) +#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ + OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ + OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ +#define CFG_LBLAWAR0_PRELIM 0x80000017 /* 16Mb window bytes */ + +/* VSC7385 on the Local Bus */ +#define CFG_VSC7385_BASE 0xF8000000 /* start of VSC7385 */ + +#define CFG_BR1_PRELIM (CFG_VSC7385_BASE | BR_PS_8 | BR_V) +#define CFG_OR1_PRELIM (0xFFFE0000 /* 128KB */ | \ + OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ + OR_GPCM_SETA | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) + +#define CFG_LBLAWBAR1_PRELIM CFG_VSC7385_BASE /* Access window base at VSC7385 base */ +#define CFG_LBLAWAR1_PRELIM 0x80000010 /* Access window size 128K */ + +#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ +#define CFG_MAX_FLASH_SECT 135 /* sectors per device */ + +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000} + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_LED_BASE 0xF9000000 /* start of LED and Board ID */ +#define CFG_BR2_PRELIM (CFG_LED_BASE | BR_PS_8 | BR_V) +#define CFG_OR2_PRELIM (0xFFE00000 /* 2MB */ | \ + OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | \ + OR_GPCM_SCY_9 | \ + OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) + +#ifdef CONFIG_COMPACT_FLASH + +#define CFG_CF_BASE 0xF0000000 + +#define CFG_BR3_PRELIM (CFG_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V) +#define CFG_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) + +#define CFG_LBLAWBAR2_PRELIM CFG_CF_BASE /* Window base at flash base + LED & Board ID */ +#define CFG_LBLAWAR2_PRELIM 0x8000000F /* 64K bytes */ + +#undef CONFIG_IDE_RESET +#undef CONFIG_IDE_PREINIT + +#define CFG_IDE_MAXBUS 1 +#define CFG_IDE_MAXDEVICE 1 + +#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CFG_ATA_BASE_ADDR CFG_CF_BASE +#define CFG_ATA_DATA_OFFSET 0x0000 +#define CFG_ATA_REG_OFFSET 0 +#define CFG_ATA_ALT_OFFSET 0x0200 +#define CFG_ATA_STRIDE 2 + +#define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */ + +#endif + +#define CONFIG_DOS_PARTITION + +#define CFG_MID_FLASH_JUMP 0x7F000000 +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK +#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ + +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* + * Local Bus LCRR and LBCR regs + * LCRR: DLL bypass, Clock divider is 4 + * External Local Bus rate is + * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV + */ +#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CFG_LBC_LBCR 0x00000000 + +#undef CFG_LB_SDRAM /* if board has SRDAM on local bus */ + +#ifdef CFG_LB_SDRAM +/*local bus BR2, OR2 definition for SDRAM if soldered on the ADS board*/ +/* + * Base Register 2 and Option Register 2 configure SDRAM. + * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. + * + * For BR2, need: + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 + */ + +#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +#define CFG_LBLAWBAR2_PRELIM 0xF0000000 +#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */ + +#define CFG_BR2_PRELIM (CFG_LBC_SDRAM_BASE | BR_PS_32 | BR_MS_SDRAM | BR_V) +#define CFG_OR2_PRELIM (0xFC000000 /* 64 MB */ | \ + OR_SDRAM_XAM | \ + ((9 - 7) << OR_SDRAM_COLS_SHIFT) | \ + ((13 - 9) << OR_SDRAM_ROWS_SHIFT) | \ + OR_SDRAM_EAD) + +#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ +#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/ + +/* + * LSDMR masks + */ +#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) +#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) +#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) +#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) +#define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) +#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) +#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) +#define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) +#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) +#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) +#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) +#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) +#define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27)) +#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) +#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) +#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) + +#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) + +#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ + | CFG_LBC_LSDMR_BSMA1516 \ + | CFG_LBC_LSDMR_RFCR8 \ + | CFG_LBC_LSDMR_PRETOACT6 \ + | CFG_LBC_LSDMR_ACTTORW3 \ + | CFG_LBC_LSDMR_BL8 \ + | CFG_LBC_LSDMR_WRC3 \ + | CFG_LBC_LSDMR_CL3 \ + ) + +/* + * SDRAM Controller configuration sequence. + */ +#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_PCHALL) +#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_ARFRSH) +#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_ARFRSH) +#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_MRW) +#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_NORMAL) +#endif + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_IMMRBAR + 0x4500) +#define CFG_NS16550_COM2 (CFG_IMMRBAR + 0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + + +#ifdef CONFIG_PCI + +#define CONFIG_MPC83XX_PCI2 + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI1_MMIO_BASE (CFG_PCI1_MEM_BASE + CFG_PCI1_MEM_SIZE) +#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE +#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xE2000000 +#define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */ + +#ifdef CONFIG_MPC83XX_PCI2 +#define CFG_PCI2_MEM_BASE (CFG_PCI1_MMIO_BASE + CFG_PCI1_MMIO_SIZE) +#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE +#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI2_MMIO_BASE (CFG_PCI2_MEM_BASE + CFG_PCI2_MEM_SIZE) +#define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE +#define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS (CFG_PCI1_IO_PHYS + CFG_PCI1_IO_SIZE) +#define CFG_PCI2_IO_SIZE 0x01000000 /* 16M */ +#endif + +#define _IO_BASE 0x00000000 /* points to PCI I/O space */ + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#ifdef CONFIG_RTL8139 +/* This macro is used by RTL8139 but not defined in PPC architecture */ +#define KSEG1ADDR(x) (x) +#endif + +#ifndef CONFIG_PCI_PNP + #define PCI_ENET0_IOADDR 0x00000000 + #define PCI_ENET0_MEMADDR CFG_PCI2_MEM_BASE + #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ +#endif + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +#endif + +/* TSEC */ + +#ifdef CONFIG_TSEC_ENET + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI +#endif + +#define CONFIG_MII +#define CONFIG_PHY_GIGE /* In case CFG_CMD_MII is specified */ + +#define CONFIG_MPC83XX_TSEC1 + +#ifdef CONFIG_MPC83XX_TSEC1 +#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" +#define CFG_TSEC1_OFFSET 0x24000 +#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ +#define TSEC1_PHYIDX 0 +#endif + +#ifdef CONFIG_MPC83XX_TSEC2 +#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" +#define CFG_TSEC2_OFFSET 0x25000 +#define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */ +#define TSEC2_PHY_ADDR 4 +#define TSEC2_PHYIDX 0 +#endif + +#define CONFIG_ETHPRIME "Freescale TSEC" + +#endif + + +/* + * Environment + */ +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 +#else + #define CFG_NO_FLASH /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* CONFIG_COMMANDS */ + +#ifdef CONFIG_COMPACT_FLASH +#define CONFIG_COMMANDS_CF (CFG_CMD_IDE | CFG_CMD_FAT) +#else +#define CONFIG_COMMANDS_CF 0 +#endif + +#ifdef CONFIG_PCI +#define CONFIG_COMMANDS_PCI CFG_CMD_PCI +#else +#define CONFIG_COMMANDS_PCI 0 +#endif + +#ifdef CONFIG_HARD_I2C +#define CONFIG_COMMANDS_I2C CFG_CMD_I2C +#else +#define CONFIG_COMMANDS_I2C 0 +#endif + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CONFIG_COMMANDS_CF | \ + CFG_CMD_NET | \ + CFG_CMD_PING | \ + CONFIG_COMMANDS_I2C | \ + CONFIG_COMMANDS_PCI | \ + CFG_CMD_SDRAM | \ + CFG_CMD_DATE | \ + CFG_CMD_CACHE | \ + CFG_CMD_IRQ) +#include + +/* Watchdog */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#ifdef CONFIG_WATCHDOG +#define CFG_WATCHDOG_VALUE 0xFFFFFFC3 +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log2 of the above value */ +#endif + +#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ + +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN_4X1 |\ + HRCWL_VCO_1X2 |\ + HRCWL_CORE_TO_CSB_2X1) + +#ifdef PCI_64BIT +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_64_BIT_PCI |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_PCI2_ARBITER_DISABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII ) +#else +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_32_BIT_PCI |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_PCI2_ARBITER_DISABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0XFFF00100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII ) +#endif + +/* System performance */ +#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ +#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ +#define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ +#define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ +#define CFG_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ +#define CFG_SCCR_TSEC2CM 1 /* TSEC2 & I2C1 clock mode (0-3) */ +#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count */ + +/* System IO Config */ +#define CFG_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */ +#define CFG_SICRL SICRL_LDP_A + +#define CFG_HID0_INIT 0x000000000 + +#define CFG_HID0_FINAL CFG_HID0_INIT + +#define CFG_HID2 HID2_HBE + +/* DDR @ 0x00000000 */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* PCI @ 0x80000000 */ +#ifdef CONFIG_PCI +#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#else +#define CFG_IBAT1L 0 +#define CFG_IBAT1U 0 +#define CFG_IBAT2L 0 +#define CFG_IBAT2U 0 +#endif + +#ifdef CONFIG_MPC83XX_PCI2 +#define CFG_IBAT3L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT3U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT4L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT4U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#else +#define CFG_IBAT3L 0 +#define CFG_IBAT3U 0 +#define CFG_IBAT4L 0 +#define CFG_IBAT4U 0 +#endif + +/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ +#define CFG_IBAT5L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT5U (CFG_IMMRBAR | BATU_BL_256M | BATU_VS | BATU_VP) + +/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ +#define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT7L 0 +#define CFG_IBAT7U 0 + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U +#define CFG_DBAT4L CFG_IBAT4L +#define CFG_DBAT4U CFG_IBAT4U +#define CFG_DBAT5L CFG_IBAT5L +#define CFG_DBAT5U CFG_IBAT5U +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#ifdef CONFIG_MPC83XX_TSEC1 +#define CONFIG_ETHADDR 00:E0:0C:00:8C:01 +#endif + +#ifdef CONFIG_MPC83XX_TSEC2 +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02 +#endif + +#define CONFIG_IPADDR 10.82.19.159 +#define CONFIG_SERVERIP 10.82.48.106 +#define CONFIG_GATEWAYIP 10.82.19.254 +#define CONFIG_NETMASK 255.255.252.0 + + +#define CONFIG_HOSTNAME mpc8349emitx +#define CONFIG_ROOTPATH /nfsroot0/u/timur/itx-ltib/rootfs +#define CONFIG_BOOTFILE timur/uImage + +#define CONFIG_UBOOTPATH timur/u-boot.bin +#define CONFIG_UBOOTSTART fe700000 +#define CONFIG_UBOOTEND fe77ffff + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +#define CONFIG_BAUDRATE 115200 + +#undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTDELAY 6 +#else +#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ +#endif + +#define CONFIG_BOOTARGS \ + "root=/dev/nfs rw nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=ttyS0,$baudrate $othbootargs" + +#define XMK_STR(x) #x +#define MK_STR(x) XMK_STR(x) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "tftpflash=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \ + "erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \ + "cp.b $loadaddr " MK_STR(CONFIG_UBOOTSTART) " $filesize; " \ + "cmp.b $loadaddr " MK_STR(CONFIG_UBOOTSTART) " $filesize\0" \ + "tftpupdate=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \ + "protect off FEF00000 FEF7FFFF; " \ + "erase FEF00000 FEF7FFFF; " \ + "cp.b $loadaddr FEF00000 $filesize; " \ + "protect on FEF00000 FEF7FFFF; " \ + "cmp.b $loadaddr FEF00000 $filesize\0" \ + "tftplinux=tftpboot $loadaddr $bootfile; bootm\0" \ + "copyuboot=erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \ + "cp.b fef00000 " MK_STR(CONFIG_UBOOTSTART) " 80000\0" + + +#undef MK_STR +#undef XMK_STR + +#endif -- cgit v1.2.3 From 7737d5c658c606f999dfbe3e86b0fed49e5c50ef Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Fri, 3 Nov 2006 12:11:15 -0600 Subject: mpc83xx: add QE ethernet support this patch adds support for the QUICC Engine based UCC gigabit ethernet device. --- Makefile | 3 + board/mpc8360emds/mpc8360emds.c | 56 ++ cpu/mpc83xx/Makefile | 2 +- cpu/mpc83xx/cpu_init.c | 40 +- cpu/mpc83xx/qe_io.c | 85 +++ drivers/qe/Makefile | 43 ++ drivers/qe/qe.c | 254 ++++++++ drivers/qe/qe.h | 237 ++++++++ drivers/qe/uccf.c | 404 +++++++++++++ drivers/qe/uccf.h | 130 ++++ drivers/qe/uec.c | 1266 +++++++++++++++++++++++++++++++++++++++ drivers/qe/uec.h | 716 ++++++++++++++++++++++ drivers/qe/uec_phy.c | 604 +++++++++++++++++++ drivers/qe/uec_phy.h | 256 ++++++++ include/asm-ppc/global_data.h | 2 + include/configs/MPC8360EMDS.h | 29 + include/ioports.h | 11 + net/eth.c | 7 + 18 files changed, 4138 insertions(+), 7 deletions(-) create mode 100644 cpu/mpc83xx/qe_io.c create mode 100644 drivers/qe/Makefile create mode 100644 drivers/qe/qe.c create mode 100644 drivers/qe/qe.h create mode 100644 drivers/qe/uccf.c create mode 100644 drivers/qe/uccf.h create mode 100644 drivers/qe/uec.c create mode 100644 drivers/qe/uec.h create mode 100644 drivers/qe/uec_phy.c create mode 100644 drivers/qe/uec_phy.h (limited to 'drivers') diff --git a/Makefile b/Makefile index 323aafc027..45c1a49e00 100644 --- a/Makefile +++ b/Makefile @@ -203,6 +203,9 @@ LIBS += dtt/libdtt.a LIBS += drivers/libdrivers.a LIBS += drivers/nand/libnand.a LIBS += drivers/nand_legacy/libnand_legacy.a +ifeq ($(CPU),mpc83xx) +LIBS += drivers/qe/qe.a +endif LIBS += drivers/sk98lin/libsk98lin.a LIBS += post/libpost.a post/cpu/libcpu.a LIBS += common/libcommon.a diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c index d70a4c3cbd..5eadcd39eb 100644 --- a/board/mpc8360emds/mpc8360emds.c +++ b/board/mpc8360emds/mpc8360emds.c @@ -29,6 +29,62 @@ #include #endif +const qe_iop_conf_t qe_iop_conf_tab[] = { + /* GETH1 */ + {0, 3, 1, 0, 1}, /* TxD0 */ + {0, 4, 1, 0, 1}, /* TxD1 */ + {0, 5, 1, 0, 1}, /* TxD2 */ + {0, 6, 1, 0, 1}, /* TxD3 */ + {1, 6, 1, 0, 3}, /* TxD4 */ + {1, 7, 1, 0, 1}, /* TxD5 */ + {1, 9, 1, 0, 2}, /* TxD6 */ + {1, 10, 1, 0, 2}, /* TxD7 */ + {0, 9, 2, 0, 1}, /* RxD0 */ + {0, 10, 2, 0, 1}, /* RxD1 */ + {0, 11, 2, 0, 1}, /* RxD2 */ + {0, 12, 2, 0, 1}, /* RxD3 */ + {0, 13, 2, 0, 1}, /* RxD4 */ + {1, 1, 2, 0, 2}, /* RxD5 */ + {1, 0, 2, 0, 2}, /* RxD6 */ + {1, 4, 2, 0, 2}, /* RxD7 */ + {0, 7, 1, 0, 1}, /* TX_EN */ + {0, 8, 1, 0, 1}, /* TX_ER */ + {0, 15, 2, 0, 1}, /* RX_DV */ + {0, 16, 2, 0, 1}, /* RX_ER */ + {0, 0, 2, 0, 1}, /* RX_CLK */ + {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */ + {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */ + /* GETH2 */ + {0, 17, 1, 0, 1}, /* TxD0 */ + {0, 18, 1, 0, 1}, /* TxD1 */ + {0, 19, 1, 0, 1}, /* TxD2 */ + {0, 20, 1, 0, 1}, /* TxD3 */ + {1, 2, 1, 0, 1}, /* TxD4 */ + {1, 3, 1, 0, 2}, /* TxD5 */ + {1, 5, 1, 0, 3}, /* TxD6 */ + {1, 8, 1, 0, 3}, /* TxD7 */ + {0, 23, 2, 0, 1}, /* RxD0 */ + {0, 24, 2, 0, 1}, /* RxD1 */ + {0, 25, 2, 0, 1}, /* RxD2 */ + {0, 26, 2, 0, 1}, /* RxD3 */ + {0, 27, 2, 0, 1}, /* RxD4 */ + {1, 12, 2, 0, 2}, /* RxD5 */ + {1, 13, 2, 0, 3}, /* RxD6 */ + {1, 11, 2, 0, 2}, /* RxD7 */ + {0, 21, 1, 0, 1}, /* TX_EN */ + {0, 22, 1, 0, 1}, /* TX_ER */ + {0, 29, 2, 0, 1}, /* RX_DV */ + {0, 30, 2, 0, 1}, /* RX_ER */ + {0, 31, 2, 0, 1}, /* RX_CLK */ + {2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */ + {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */ + + {0, 1, 3, 0, 2}, /* MDIO */ + {0, 2, 1, 0, 1}, /* MDC */ + + {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ +}; + int board_early_init_f(void) { volatile u8 *bcsr = (volatile u8 *)CFG_BCSR; diff --git a/cpu/mpc83xx/Makefile b/cpu/mpc83xx/Makefile index 1aa0005d4d..e254ef98f6 100644 --- a/cpu/mpc83xx/Makefile +++ b/cpu/mpc83xx/Makefile @@ -29,7 +29,7 @@ LIB = $(obj)lib$(CPU).a START = start.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ - i2c.o spd_sdram.o + i2c.o spd_sdram.o qe_io.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index 999fe71964..eb8f8c042f 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -31,6 +31,30 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_QE +extern qe_iop_conf_t qe_iop_conf_tab[]; +extern void qe_config_iopin(u8 port, u8 pin, int dir, + int open_drain, int assign); +extern void qe_init(uint qe_base); +extern void qe_reset(void); + +static void config_qe_ioports(void) +{ + u8 port, pin; + int dir, open_drain, assign; + int i; + + for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { + port = qe_iop_conf_tab[i].port; + pin = qe_iop_conf_tab[i].pin; + dir = qe_iop_conf_tab[i].dir; + open_drain = qe_iop_conf_tab[i].open_drain; + assign = qe_iop_conf_tab[i].assign; + qe_config_iopin(port, pin, dir, open_drain, assign); + } +} +#endif + /* * Breathe some life into the CPU... * @@ -100,6 +124,10 @@ void cpu_init_f (volatile immap_t * im) #ifdef CFG_SICRL im->sysconf.sicrl = CFG_SICRL; #endif +#ifdef CONFIG_QE + /* Config QE ioports */ + config_qe_ioports(); +#endif /* * Memory Controller: @@ -188,12 +216,12 @@ void cpu_init_f (volatile immap_t * im) #endif } - -/* - * Initialize higher level parts of CPU like time base and timers. - */ - int cpu_init_r (void) { +#ifdef CONFIG_QE + uint qe_base = CFG_IMMRBAR + 0x00100000; /* QE immr base */ + qe_init(qe_base); + qe_reset(); +#endif return 0; } diff --git a/cpu/mpc83xx/qe_io.c b/cpu/mpc83xx/qe_io.c new file mode 100644 index 0000000000..11cf3722bd --- /dev/null +++ b/cpu/mpc83xx/qe_io.c @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * + * Dave Liu + * based on source code of Shlomi Gridish + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "common.h" +#include "asm/errno.h" +#include "asm/io.h" +#include "asm/immap_83xx.h" + +#if defined(CONFIG_QE) +#define NUM_OF_PINS 32 +void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) +{ + u32 pin_2bit_mask; + u32 pin_2bit_dir; + u32 pin_2bit_assign; + u32 pin_1bit_mask; + u32 tmp_val; + volatile immap_t *im = (volatile immap_t *)CFG_IMMRBAR; + volatile gpio83xx_t *par_io =(volatile gpio83xx_t *)&im->gpio; + + /* Caculate pin location and 2bit mask and dir */ + pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2)); + pin_2bit_dir = (u32)(dir << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2)); + + /* Setup the direction */ + tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? \ + in_be32(&par_io->ioport[port].dir2) : + in_be32(&par_io->ioport[port].dir1); + + if (pin > (NUM_OF_PINS/2) -1) { + out_be32(&par_io->ioport[port].dir2, ~pin_2bit_mask & tmp_val); + out_be32(&par_io->ioport[port].dir2, pin_2bit_dir | tmp_val); + } else { + out_be32(&par_io->ioport[port].dir1, ~pin_2bit_mask & tmp_val); + out_be32(&par_io->ioport[port].dir1, pin_2bit_dir | tmp_val); + } + + /* Calculate pin location for 1bit mask */ + pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1))); + + /* Setup the open drain */ + tmp_val = in_be32(&par_io->ioport[port].podr); + if (open_drain) { + out_be32(&par_io->ioport[port].podr, pin_1bit_mask | tmp_val); + } else { + out_be32(&par_io->ioport[port].podr, ~pin_1bit_mask & tmp_val); + } + + /* Setup the assignment */ + tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? + in_be32(&par_io->ioport[port].ppar2): + in_be32(&par_io->ioport[port].ppar1); + pin_2bit_assign = (u32)(assign + << (NUM_OF_PINS - (pin%(NUM_OF_PINS/2)+1)*2)); + + /* Clear and set 2 bits mask */ + if (pin > (NUM_OF_PINS/2) - 1) { + out_be32(&par_io->ioport[port].ppar2, ~pin_2bit_mask & tmp_val); + out_be32(&par_io->ioport[port].ppar2, pin_2bit_assign | tmp_val); + } else { + out_be32(&par_io->ioport[port].ppar1, ~pin_2bit_mask & tmp_val); + out_be32(&par_io->ioport[port].ppar1, pin_2bit_assign | tmp_val); + } +} + +#endif /* CONFIG_QE */ diff --git a/drivers/qe/Makefile b/drivers/qe/Makefile new file mode 100644 index 0000000000..4844181b8e --- /dev/null +++ b/drivers/qe/Makefile @@ -0,0 +1,43 @@ +# +# Copyright (C) 2006 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB := $(obj)qe.a + +COBJS := qe.o uccf.o uec.o uec_phy.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c new file mode 100644 index 0000000000..5f209629f4 --- /dev/null +++ b/drivers/qe/qe.c @@ -0,0 +1,254 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * + * Dave Liu + * based on source code of Shlomi Gridish + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "common.h" +#include "asm/errno.h" +#include "asm/io.h" +#include "asm/immap_qe.h" +#include "qe.h" + +#if defined(CONFIG_QE) +qe_map_t *qe_immr = NULL; +static qe_snum_t snums[QE_NUM_OF_SNUM]; + +void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data) +{ + u32 cecr; + + if (cmd == QE_RESET) { + out_be32(&qe_immr->cp.cecr,(u32) (cmd | QE_CR_FLG)); + } else { + out_be32(&qe_immr->cp.cecdr, cmd_data); + out_be32(&qe_immr->cp.cecr, (sbc | QE_CR_FLG | + ((u32) mcn<cp.cecr); + } while (cecr & QE_CR_FLG); + + return; +} + +uint qe_muram_alloc(uint size, uint align) +{ + DECLARE_GLOBAL_DATA_PTR; + + uint retloc; + uint align_mask, off; + uint savebase; + + align_mask = align - 1; + savebase = gd->mp_alloc_base; + + if ((off = (gd->mp_alloc_base & align_mask)) != 0) + gd->mp_alloc_base += (align - off); + + if ((off = size & align_mask) != 0) + size += (align - off); + + if ((gd->mp_alloc_base + size) >= gd->mp_alloc_top) { + gd->mp_alloc_base = savebase; + printf("%s: ran out of ram.\n", __FUNCTION__); + } + + retloc = gd->mp_alloc_base; + gd->mp_alloc_base += size; + + memset((void *)&qe_immr->muram[retloc], 0, size); + + __asm__ __volatile__("sync"); + + return retloc; +} + +void *qe_muram_addr(uint offset) +{ + return (void *)&qe_immr->muram[offset]; +} + +static void qe_sdma_init(void) +{ + volatile sdma_t *p; + uint sdma_buffer_base; + + p = (volatile sdma_t *)&qe_immr->sdma; + + /* All of DMA transaction in bus 1 */ + out_be32(&p->sdaqr, 0); + out_be32(&p->sdaqmr, 0); + + /* Allocate 2KB temporary buffer for sdma */ + sdma_buffer_base = qe_muram_alloc(2048, 64); + out_be32(&p->sdwbcr, sdma_buffer_base & QE_SDEBCR_BA_MASK); + + /* Clear sdma status */ + out_be32(&p->sdsr, 0x03000000); + + /* Enable global mode on bus 1, and 2KB buffer size */ + out_be32(&p->sdmr, QE_SDMR_GLB_1_MSK | (0x3 << QE_SDMR_CEN_SHIFT)); +} + +static u8 thread_snum[QE_NUM_OF_SNUM] = { + 0x04, 0x05, 0x0c, 0x0d, + 0x14, 0x15, 0x1c, 0x1d, + 0x24, 0x25, 0x2c, 0x2d, + 0x34, 0x35, 0x88, 0x89, + 0x98, 0x99, 0xa8, 0xa9, + 0xb8, 0xb9, 0xc8, 0xc9, + 0xd8, 0xd9, 0xe8, 0xe9 +}; + +static void qe_snums_init(void) +{ + int i; + + for (i = 0; i < QE_NUM_OF_SNUM; i++) { + snums[i].state = QE_SNUM_STATE_FREE; + snums[i].num = thread_snum[i]; + } +} + +int qe_get_snum(void) +{ + int snum = -EBUSY; + int i; + + for (i = 0; i < QE_NUM_OF_SNUM; i++) { + if (snums[i].state == QE_SNUM_STATE_FREE) { + snums[i].state = QE_SNUM_STATE_USED; + snum = snums[i].num; + break; + } + } + + return snum; +} + +void qe_put_snum(u8 snum) +{ + int i; + + for (i = 0; i < QE_NUM_OF_SNUM; i++) { + if (snums[i].num == snum) { + snums[i].state = QE_SNUM_STATE_FREE; + break; + } + } +} + +void qe_init(uint qe_base) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* Init the QE IMMR base */ + qe_immr = (qe_map_t *)qe_base; + + gd->mp_alloc_base = QE_DATAONLY_BASE; + gd->mp_alloc_top = gd->mp_alloc_base + QE_DATAONLY_SIZE; + + qe_sdma_init(); + qe_snums_init(); +} + +void qe_reset(void) +{ + qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID, + (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0); +} + +void qe_assign_page(uint snum, uint para_ram_base) +{ + u32 cecr; + + out_be32(&qe_immr->cp.cecdr, para_ram_base); + out_be32(&qe_immr->cp.cecr, ((u32) snum<cp.cecr); + } while (cecr & QE_CR_FLG ); + + return; +} + +/* + * brg: 0~15 as BRG1~BRG16 + rate: baud rate + * BRG input clock comes from the BRGCLK (internal clock generated from + the QE clock, it is one-half of the QE clock), If need the clock source + from CLKn pin, we have te change the function. + */ + +#define BRG_CLK (gd->brg_clk) + +int qe_set_brg(uint brg, uint rate) +{ + DECLARE_GLOBAL_DATA_PTR; + volatile uint *bp; + u32 divisor; + int div16 = 0; + + if (brg >= QE_NUM_OF_BRGS) + return -EINVAL; + bp = (uint *)&qe_immr->brg.brgc1; + bp += brg; + + divisor = (BRG_CLK / rate); + if (divisor > QE_BRGC_DIVISOR_MAX + 1) { + div16 = 1; + divisor /= 16; + } + + *bp = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE; + __asm__ __volatile__("sync"); + + if (div16) { + *bp |= QE_BRGC_DIV16; + __asm__ __volatile__("sync"); + } + + return 0; +} + +/* Set ethernet MII clock master +*/ +int qe_set_mii_clk_src(int ucc_num) +{ + u32 cmxgcr; + + /* check if the UCC number is in range. */ + if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) { + printf("%s: ucc num not in ranges\n", __FUNCTION__); + return -EINVAL; + } + + cmxgcr = in_be32(&qe_immr->qmx.cmxgcr); + cmxgcr &= ~QE_CMXGCR_MII_ENET_MNG_MASK; + cmxgcr |= (ucc_num <qmx.cmxgcr, cmxgcr); + + return 0; +} + +#endif /* CONFIG_QE */ diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h new file mode 100644 index 0000000000..f7f8ed0a72 --- /dev/null +++ b/drivers/qe/qe.h @@ -0,0 +1,237 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * + * Dave Liu + * based on source code of Shlomi Gridish + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __QE_H__ +#define __QE_H__ + +#include "common.h" + +#define QE_NUM_OF_SNUM 28 +#define QE_NUM_OF_BRGS 16 +#define UCC_MAX_NUM 8 + +#define QE_DATAONLY_BASE (uint)(128) +#define QE_DATAONLY_SIZE ((uint)(0xc000) - QE_DATAONLY_BASE) + +/* QE threads SNUM +*/ +typedef enum qe_snum_state { + QE_SNUM_STATE_USED, /* used */ + QE_SNUM_STATE_FREE /* free */ +} qe_snum_state_e; + +typedef struct qe_snum { + u8 num; /* snum */ + qe_snum_state_e state; /* state */ +} qe_snum_t; + +/* QE RISC allocation +*/ +typedef enum qe_risc_allocation { + QE_RISC_ALLOCATION_RISC1 = 1, /* RISC 1 */ + QE_RISC_ALLOCATION_RISC2 = 2, /* RISC 2 */ + QE_RISC_ALLOCATION_RISC1_AND_RISC2 = 3 /* RISC 1 or RISC 2 */ +} qe_risc_allocation_e; + +/* QE CECR commands for UCC fast. +*/ +#define QE_CR_FLG 0x00010000 +#define QE_RESET 0x80000000 +#define QE_INIT_TX_RX 0x00000000 +#define QE_INIT_RX 0x00000001 +#define QE_INIT_TX 0x00000002 +#define QE_ENTER_HUNT_MODE 0x00000003 +#define QE_STOP_TX 0x00000004 +#define QE_GRACEFUL_STOP_TX 0x00000005 +#define QE_RESTART_TX 0x00000006 +#define QE_SWITCH_COMMAND 0x00000007 +#define QE_SET_GROUP_ADDRESS 0x00000008 +#define QE_INSERT_CELL 0x00000009 +#define QE_ATM_TRANSMIT 0x0000000a +#define QE_CELL_POOL_GET 0x0000000b +#define QE_CELL_POOL_PUT 0x0000000c +#define QE_IMA_HOST_CMD 0x0000000d +#define QE_ATM_MULTI_THREAD_INIT 0x00000011 +#define QE_ASSIGN_PAGE 0x00000012 +#define QE_START_FLOW_CONTROL 0x00000014 +#define QE_STOP_FLOW_CONTROL 0x00000015 +#define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016 +#define QE_GRACEFUL_STOP_RX 0x0000001a +#define QE_RESTART_RX 0x0000001b + +/* QE CECR Sub Block Code - sub block code of QE command. +*/ +#define QE_CR_SUBBLOCK_INVALID 0x00000000 +#define QE_CR_SUBBLOCK_USB 0x03200000 +#define QE_CR_SUBBLOCK_UCCFAST1 0x02000000 +#define QE_CR_SUBBLOCK_UCCFAST2 0x02200000 +#define QE_CR_SUBBLOCK_UCCFAST3 0x02400000 +#define QE_CR_SUBBLOCK_UCCFAST4 0x02600000 +#define QE_CR_SUBBLOCK_UCCFAST5 0x02800000 +#define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000 +#define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000 +#define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000 +#define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000 +#define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000 +#define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000 +#define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000 +#define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000 +#define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000 +#define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000 +#define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000 +#define QE_CR_SUBBLOCK_MCC1 0x03800000 +#define QE_CR_SUBBLOCK_MCC2 0x03a00000 +#define QE_CR_SUBBLOCK_MCC3 0x03000000 +#define QE_CR_SUBBLOCK_IDMA1 0x02800000 +#define QE_CR_SUBBLOCK_IDMA2 0x02a00000 +#define QE_CR_SUBBLOCK_IDMA3 0x02c00000 +#define QE_CR_SUBBLOCK_IDMA4 0x02e00000 +#define QE_CR_SUBBLOCK_HPAC 0x01e00000 +#define QE_CR_SUBBLOCK_SPI1 0x01400000 +#define QE_CR_SUBBLOCK_SPI2 0x01600000 +#define QE_CR_SUBBLOCK_RAND 0x01c00000 +#define QE_CR_SUBBLOCK_TIMER 0x01e00000 +#define QE_CR_SUBBLOCK_GENERAL 0x03c00000 + +/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command. +*/ +#define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */ +#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00 +#define QE_CR_PROTOCOL_ATM_POS 0x0A +#define QE_CR_PROTOCOL_ETHERNET 0x0C +#define QE_CR_PROTOCOL_L2_SWITCH 0x0D +#define QE_CR_PROTOCOL_SHIFT 6 + +/* QE ASSIGN PAGE command +*/ +#define QE_CR_ASSIGN_PAGE_SNUM_SHIFT 17 + +/* Communication Direction. +*/ +typedef enum comm_dir { + COMM_DIR_NONE = 0, + COMM_DIR_RX = 1, + COMM_DIR_TX = 2, + COMM_DIR_RX_AND_TX = 3 +} comm_dir_e; + +/* Clocks and BRG's +*/ +typedef enum qe_clock { + QE_CLK_NONE = 0, + QE_BRG1, /* Baud Rate Generator 1 */ + QE_BRG2, /* Baud Rate Generator 2 */ + QE_BRG3, /* Baud Rate Generator 3 */ + QE_BRG4, /* Baud Rate Generator 4 */ + QE_BRG5, /* Baud Rate Generator 5 */ + QE_BRG6, /* Baud Rate Generator 6 */ + QE_BRG7, /* Baud Rate Generator 7 */ + QE_BRG8, /* Baud Rate Generator 8 */ + QE_BRG9, /* Baud Rate Generator 9 */ + QE_BRG10, /* Baud Rate Generator 10 */ + QE_BRG11, /* Baud Rate Generator 11 */ + QE_BRG12, /* Baud Rate Generator 12 */ + QE_BRG13, /* Baud Rate Generator 13 */ + QE_BRG14, /* Baud Rate Generator 14 */ + QE_BRG15, /* Baud Rate Generator 15 */ + QE_BRG16, /* Baud Rate Generator 16 */ + QE_CLK1, /* Clock 1 */ + QE_CLK2, /* Clock 2 */ + QE_CLK3, /* Clock 3 */ + QE_CLK4, /* Clock 4 */ + QE_CLK5, /* Clock 5 */ + QE_CLK6, /* Clock 6 */ + QE_CLK7, /* Clock 7 */ + QE_CLK8, /* Clock 8 */ + QE_CLK9, /* Clock 9 */ + QE_CLK10, /* Clock 10 */ + QE_CLK11, /* Clock 11 */ + QE_CLK12, /* Clock 12 */ + QE_CLK13, /* Clock 13 */ + QE_CLK14, /* Clock 14 */ + QE_CLK15, /* Clock 15 */ + QE_CLK16, /* Clock 16 */ + QE_CLK17, /* Clock 17 */ + QE_CLK18, /* Clock 18 */ + QE_CLK19, /* Clock 19 */ + QE_CLK20, /* Clock 20 */ + QE_CLK21, /* Clock 21 */ + QE_CLK22, /* Clock 22 */ + QE_CLK23, /* Clock 23 */ + QE_CLK24, /* Clock 24 */ + QE_CLK_DUMMY +} qe_clock_e; + +/* QE CMXGCR register +*/ +#define QE_CMXGCR_MII_ENET_MNG_MASK 0x00007000 +#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12 + +/* QE CMXUCR registers + */ +#define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F + +/* QE BRG configuration register +*/ +#define QE_BRGC_ENABLE 0x00010000 +#define QE_BRGC_DIVISOR_SHIFT 1 +#define QE_BRGC_DIVISOR_MAX 0xFFF +#define QE_BRGC_DIV16 1 + +/* QE SDMA registers +*/ +#define QE_SDSR_BER1 0x02000000 +#define QE_SDSR_BER2 0x01000000 + +#define QE_SDMR_GLB_1_MSK 0x80000000 +#define QE_SDMR_ADR_SEL 0x20000000 +#define QE_SDMR_BER1_MSK 0x02000000 +#define QE_SDMR_BER2_MSK 0x01000000 +#define QE_SDMR_EB1_MSK 0x00800000 +#define QE_SDMR_ER1_MSK 0x00080000 +#define QE_SDMR_ER2_MSK 0x00040000 +#define QE_SDMR_CEN_MASK 0x0000E000 +#define QE_SDMR_SBER_1 0x00000200 +#define QE_SDMR_SBER_2 0x00000200 +#define QE_SDMR_EB1_PR_MASK 0x000000C0 +#define QE_SDMR_ER1_PR 0x00000008 + +#define QE_SDMR_CEN_SHIFT 13 +#define QE_SDMR_EB1_PR_SHIFT 6 + +#define QE_SDTM_MSNUM_SHIFT 24 + +#define QE_SDEBCR_BA_MASK 0x01FFFFFF + +void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign); +void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data); +uint qe_muram_alloc(uint size, uint align); +void *qe_muram_addr(uint offset); +int qe_get_snum(void); +void qe_put_snum(u8 snum); +void qe_init(uint qe_base); +void qe_reset(void); +void qe_assign_page(uint snum, uint para_ram_base); +int qe_set_brg(uint brg, uint rate); +int qe_set_mii_clk_src(int ucc_num); + +#endif /* __QE_H__ */ diff --git a/drivers/qe/uccf.c b/drivers/qe/uccf.c new file mode 100644 index 0000000000..25f74826c0 --- /dev/null +++ b/drivers/qe/uccf.c @@ -0,0 +1,404 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * + * Dave Liu + * based on source code of Shlomi Gridish + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "common.h" +#include "malloc.h" +#include "asm/errno.h" +#include "asm/io.h" +#include "asm/immap_qe.h" +#include "qe.h" +#include "uccf.h" + +#if defined(CONFIG_QE) +void ucc_fast_transmit_on_demand(ucc_fast_private_t *uccf) +{ + out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD); +} + +u32 ucc_fast_get_qe_cr_subblock(int ucc_num) +{ + switch (ucc_num) { + case 0: return QE_CR_SUBBLOCK_UCCFAST1; + case 1: return QE_CR_SUBBLOCK_UCCFAST2; + case 2: return QE_CR_SUBBLOCK_UCCFAST3; + case 3: return QE_CR_SUBBLOCK_UCCFAST4; + case 4: return QE_CR_SUBBLOCK_UCCFAST5; + case 5: return QE_CR_SUBBLOCK_UCCFAST6; + case 6: return QE_CR_SUBBLOCK_UCCFAST7; + case 7: return QE_CR_SUBBLOCK_UCCFAST8; + default: return QE_CR_SUBBLOCK_INVALID; + } +} + +static void ucc_get_cmxucr_reg(int ucc_num, volatile u32 **p_cmxucr, + u8 *reg_num, u8 *shift) +{ + switch (ucc_num) { + case 0: /* UCC1 */ + *p_cmxucr = &(qe_immr->qmx.cmxucr1); + *reg_num = 1; + *shift = 16; + break; + case 2: /* UCC3 */ + *p_cmxucr = &(qe_immr->qmx.cmxucr1); + *reg_num = 1; + *shift = 0; + break; + case 4: /* UCC5 */ + *p_cmxucr = &(qe_immr->qmx.cmxucr2); + *reg_num = 2; + *shift = 16; + break; + case 6: /* UCC7 */ + *p_cmxucr = &(qe_immr->qmx.cmxucr2); + *reg_num = 2; + *shift = 0; + break; + case 1: /* UCC2 */ + *p_cmxucr = &(qe_immr->qmx.cmxucr3); + *reg_num = 3; + *shift = 16; + break; + case 3: /* UCC4 */ + *p_cmxucr = &(qe_immr->qmx.cmxucr3); + *reg_num = 3; + *shift = 0; + break; + case 5: /* UCC6 */ + *p_cmxucr = &(qe_immr->qmx.cmxucr4); + *reg_num = 4; + *shift = 16; + break; + case 7: /* UCC8 */ + *p_cmxucr = &(qe_immr->qmx.cmxucr4); + *reg_num = 4; + *shift = 0; + break; + default: + break; + } +} + +static int ucc_set_clk_src(int ucc_num, qe_clock_e clock, comm_dir_e mode) +{ + volatile u32 *p_cmxucr; + u8 reg_num; + u8 shift; + u32 clockBits; + u32 clockMask; + int source = -1; + + /* check if the UCC number is in range. */ + if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) + return -EINVAL; + + if (! ((mode == COMM_DIR_RX) || (mode == COMM_DIR_TX))) { + printf("%s: bad comm mode type passed\n", __FUNCTION__); + return -EINVAL; + } + + ucc_get_cmxucr_reg(ucc_num, &p_cmxucr, ®_num, &shift); + + switch (reg_num) { + case 1: + switch (clock) { + case QE_BRG1: source = 1; break; + case QE_BRG2: source = 2; break; + case QE_BRG7: source = 3; break; + case QE_BRG8: source = 4; break; + case QE_CLK9: source = 5; break; + case QE_CLK10: source = 6; break; + case QE_CLK11: source = 7; break; + case QE_CLK12: source = 8; break; + case QE_CLK15: source = 9; break; + case QE_CLK16: source = 10; break; + default: source = -1; break; + } + break; + case 2: + switch (clock) { + case QE_BRG5: source = 1; break; + case QE_BRG6: source = 2; break; + case QE_BRG7: source = 3; break; + case QE_BRG8: source = 4; break; + case QE_CLK13: source = 5; break; + case QE_CLK14: source = 6; break; + case QE_CLK19: source = 7; break; + case QE_CLK20: source = 8; break; + case QE_CLK15: source = 9; break; + case QE_CLK16: source = 10; break; + default: source = -1; break; + } + break; + case 3: + switch (clock) { + case QE_BRG9: source = 1; break; + case QE_BRG10: source = 2; break; + case QE_BRG15: source = 3; break; + case QE_BRG16: source = 4; break; + case QE_CLK3: source = 5; break; + case QE_CLK4: source = 6; break; + case QE_CLK17: source = 7; break; + case QE_CLK18: source = 8; break; + case QE_CLK7: source = 9; break; + case QE_CLK8: source = 10; break; + case QE_CLK16: source = 11; break; + default: source = -1; break; + } + break; + case 4: + switch (clock) { + case QE_BRG13: source = 1; break; + case QE_BRG14: source = 2; break; + case QE_BRG15: source = 3; break; + case QE_BRG16: source = 4; break; + case QE_CLK5: source = 5; break; + case QE_CLK6: source = 6; break; + case QE_CLK21: source = 7; break; + case QE_CLK22: source = 8; break; + case QE_CLK7: source = 9; break; + case QE_CLK8: source = 10; break; + case QE_CLK16: source = 11; break; + default: source = -1; break; + } + break; + default: + source = -1; + break; + } + + if (source == -1) { + printf("%s: Bad combination of clock and UCC\n", __FUNCTION__); + return -ENOENT; + } + + clockBits = (u32) source; + clockMask = QE_CMXUCR_TX_CLK_SRC_MASK; + if (mode == COMM_DIR_RX) { + clockBits <<= 4; /* Rx field is 4 bits to left of Tx field */ + clockMask <<= 4; /* Rx field is 4 bits to left of Tx field */ + } + clockBits <<= shift; + clockMask <<= shift; + + out_be32(p_cmxucr, (in_be32(p_cmxucr) & ~clockMask) | clockBits); + + return 0; +} + +static uint ucc_get_reg_baseaddr(int ucc_num) +{ + uint base = 0; + + /* check if the UCC number is in range */ + if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) { + printf("%s: the UCC num not in ranges\n", __FUNCTION__); + return 0; + } + + switch (ucc_num) { + case 0: base = 0x00002000; break; + case 1: base = 0x00003000; break; + case 2: base = 0x00002200; break; + case 3: base = 0x00003200; break; + case 4: base = 0x00002400; break; + case 5: base = 0x00003400; break; + case 6: base = 0x00002600; break; + case 7: base = 0x00003600; break; + default: break; + } + + base = (uint)qe_immr + base; + return base; +} + +void ucc_fast_enable(ucc_fast_private_t *uccf, comm_dir_e mode) +{ + ucc_fast_t *uf_regs; + u32 gumr; + + uf_regs = uccf->uf_regs; + + /* Enable reception and/or transmission on this UCC. */ + gumr = in_be32(&uf_regs->gumr); + if (mode & COMM_DIR_TX) { + gumr |= UCC_FAST_GUMR_ENT; + uccf->enabled_tx = 1; + } + if (mode & COMM_DIR_RX) { + gumr |= UCC_FAST_GUMR_ENR; + uccf->enabled_rx = 1; + } + out_be32(&uf_regs->gumr, gumr); +} + +void ucc_fast_disable(ucc_fast_private_t *uccf, comm_dir_e mode) +{ + ucc_fast_t *uf_regs; + u32 gumr; + + uf_regs = uccf->uf_regs; + + /* Disable reception and/or transmission on this UCC. */ + gumr = in_be32(&uf_regs->gumr); + if (mode & COMM_DIR_TX) { + gumr &= ~UCC_FAST_GUMR_ENT; + uccf->enabled_tx = 0; + } + if (mode & COMM_DIR_RX) { + gumr &= ~UCC_FAST_GUMR_ENR; + uccf->enabled_rx = 0; + } + out_be32(&uf_regs->gumr, gumr); +} + +int ucc_fast_init(ucc_fast_info_t *uf_info, ucc_fast_private_t **uccf_ret) +{ + ucc_fast_private_t *uccf; + ucc_fast_t *uf_regs; + + if (!uf_info) + return -EINVAL; + + if ((uf_info->ucc_num < 0) || (uf_info->ucc_num > UCC_MAX_NUM - 1)) { + printf("%s: Illagal UCC number!\n", __FUNCTION__); + return -EINVAL; + } + + uccf = (ucc_fast_private_t *)malloc(sizeof(ucc_fast_private_t)); + if (!uccf) { + printf("%s: No memory for UCC fast data structure!\n", + __FUNCTION__); + return -ENOMEM; + } + memset(uccf, 0, sizeof(ucc_fast_private_t)); + + /* Save fast UCC structure */ + uccf->uf_info = uf_info; + uccf->uf_regs = (ucc_fast_t *)ucc_get_reg_baseaddr(uf_info->ucc_num); + + if (uccf->uf_regs == NULL) { + printf("%s: No memory map for UCC fast controller!\n", + __FUNCTION__); + return -ENOMEM; + } + + uccf->enabled_tx = 0; + uccf->enabled_rx = 0; + + uf_regs = uccf->uf_regs; + uccf->p_ucce = (u32 *) &(uf_regs->ucce); + uccf->p_uccm = (u32 *) &(uf_regs->uccm); + + /* Init GUEMR register, UCC both Rx and Tx is Fast protocol */ + out_8(&uf_regs->guemr, UCC_GUEMR_SET_RESERVED3 | UCC_GUEMR_MODE_FAST_RX + | UCC_GUEMR_MODE_FAST_TX); + + /* Set GUMR, disable UCC both Rx and Tx, Ethernet protocol */ + out_be32(&uf_regs->gumr, UCC_FAST_GUMR_ETH); + + /* Set the Giga ethernet VFIFO stuff */ + if (uf_info->eth_type == GIGA_ETH) { + /* Allocate memory for Tx Virtual Fifo */ + uccf->ucc_fast_tx_virtual_fifo_base_offset = + qe_muram_alloc(UCC_GETH_UTFS_GIGA_INIT, + UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT); + + /* Allocate memory for Rx Virtual Fifo */ + uccf->ucc_fast_rx_virtual_fifo_base_offset = + qe_muram_alloc(UCC_GETH_URFS_GIGA_INIT + + UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD, + UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT); + + /* utfb, urfb are offsets from MURAM base */ + out_be32(&uf_regs->utfb, + uccf->ucc_fast_tx_virtual_fifo_base_offset); + out_be32(&uf_regs->urfb, + uccf->ucc_fast_rx_virtual_fifo_base_offset); + + /* Set Virtual Fifo registers */ + out_be16(&uf_regs->urfs, UCC_GETH_URFS_GIGA_INIT); + out_be16(&uf_regs->urfet, UCC_GETH_URFET_GIGA_INIT); + out_be16(&uf_regs->urfset, UCC_GETH_URFSET_GIGA_INIT); + out_be16(&uf_regs->utfs, UCC_GETH_UTFS_GIGA_INIT); + out_be16(&uf_regs->utfet, UCC_GETH_UTFET_GIGA_INIT); + out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_GIGA_INIT); + } + + /* Set the Fast ethernet VFIFO stuff */ + if (uf_info->eth_type == FAST_ETH) { + /* Allocate memory for Tx Virtual Fifo */ + uccf->ucc_fast_tx_virtual_fifo_base_offset = + qe_muram_alloc(UCC_GETH_UTFS_INIT, + UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT); + + /* Allocate memory for Rx Virtual Fifo */ + uccf->ucc_fast_rx_virtual_fifo_base_offset = + qe_muram_alloc(UCC_GETH_URFS_INIT + + UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD, + UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT); + + /* utfb, urfb are offsets from MURAM base */ + out_be32(&uf_regs->utfb, + uccf->ucc_fast_tx_virtual_fifo_base_offset); + out_be32(&uf_regs->urfb, + uccf->ucc_fast_rx_virtual_fifo_base_offset); + + /* Set Virtual Fifo registers */ + out_be16(&uf_regs->urfs, UCC_GETH_URFS_INIT); + out_be16(&uf_regs->urfet, UCC_GETH_URFET_INIT); + out_be16(&uf_regs->urfset, UCC_GETH_URFSET_INIT); + out_be16(&uf_regs->utfs, UCC_GETH_UTFS_INIT); + out_be16(&uf_regs->utfet, UCC_GETH_UTFET_INIT); + out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_INIT); + } + + /* Rx clock routing */ + if (uf_info->rx_clock != QE_CLK_NONE) { + if (ucc_set_clk_src(uf_info->ucc_num, + uf_info->rx_clock, COMM_DIR_RX)) { + printf("%s: Illegal value for parameter 'RxClock'.\n", + __FUNCTION__); + return -EINVAL; + } + } + + /* Tx clock routing */ + if (uf_info->tx_clock != QE_CLK_NONE) { + if (ucc_set_clk_src(uf_info->ucc_num, + uf_info->tx_clock, COMM_DIR_TX)) { + printf("%s: Illegal value for parameter 'TxClock'.\n", + __FUNCTION__); + return -EINVAL; + } + } + + /* Clear interrupt mask register to disable all of interrupts */ + out_be32(&uf_regs->uccm, 0x0); + + /* Writing '1' to clear all of envents */ + out_be32(&uf_regs->ucce, 0xffffffff); + + *uccf_ret = uccf; + return 0; +} +#endif /* CONFIG_QE */ diff --git a/drivers/qe/uccf.h b/drivers/qe/uccf.h new file mode 100644 index 0000000000..1ff9e1daf5 --- /dev/null +++ b/drivers/qe/uccf.h @@ -0,0 +1,130 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * + * Dave Liu + * based on source code of Shlomi Gridish + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __UCCF_H__ +#define __UCCF_H__ + +#include "common.h" +#include "qe.h" + +/* Fast or Giga ethernet +*/ +typedef enum enet_type { + FAST_ETH, + GIGA_ETH, +} enet_type_e; + +/* General UCC Extended Mode Register +*/ +#define UCC_GUEMR_MODE_MASK_RX 0x02 +#define UCC_GUEMR_MODE_MASK_TX 0x01 +#define UCC_GUEMR_MODE_FAST_RX 0x02 +#define UCC_GUEMR_MODE_FAST_TX 0x01 +#define UCC_GUEMR_MODE_SLOW_RX 0x00 +#define UCC_GUEMR_MODE_SLOW_TX 0x00 +#define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 must be set 1 */ + +/* General UCC FAST Mode Register +*/ +#define UCC_FAST_GUMR_TCI 0x20000000 +#define UCC_FAST_GUMR_TRX 0x10000000 +#define UCC_FAST_GUMR_TTX 0x08000000 +#define UCC_FAST_GUMR_CDP 0x04000000 +#define UCC_FAST_GUMR_CTSP 0x02000000 +#define UCC_FAST_GUMR_CDS 0x01000000 +#define UCC_FAST_GUMR_CTSS 0x00800000 +#define UCC_FAST_GUMR_TXSY 0x00020000 +#define UCC_FAST_GUMR_RSYN 0x00010000 +#define UCC_FAST_GUMR_RTSM 0x00002000 +#define UCC_FAST_GUMR_REVD 0x00000400 +#define UCC_FAST_GUMR_ENR 0x00000020 +#define UCC_FAST_GUMR_ENT 0x00000010 + +/* GUMR [MODE] bit maps +*/ +#define UCC_FAST_GUMR_HDLC 0x00000000 +#define UCC_FAST_GUMR_QMC 0x00000002 +#define UCC_FAST_GUMR_UART 0x00000004 +#define UCC_FAST_GUMR_BISYNC 0x00000008 +#define UCC_FAST_GUMR_ATM 0x0000000a +#define UCC_FAST_GUMR_ETH 0x0000000c + +/* Transmit On Demand (UTORD) +*/ +#define UCC_SLOW_TOD 0x8000 +#define UCC_FAST_TOD 0x8000 + +/* Fast Ethernet (10/100 Mbps) +*/ +#define UCC_GETH_URFS_INIT 512 /* Rx virtual FIFO size */ +#define UCC_GETH_URFET_INIT 256 /* 1/2 urfs */ +#define UCC_GETH_URFSET_INIT 384 /* 3/4 urfs */ +#define UCC_GETH_UTFS_INIT 512 /* Tx virtual FIFO size */ +#define UCC_GETH_UTFET_INIT 256 /* 1/2 utfs */ +#define UCC_GETH_UTFTT_INIT 128 + +/* Gigabit Ethernet (1000 Mbps) +*/ +#define UCC_GETH_URFS_GIGA_INIT 4096/*2048*/ /* Rx virtual FIFO size */ +#define UCC_GETH_URFET_GIGA_INIT 2048/*1024*/ /* 1/2 urfs */ +#define UCC_GETH_URFSET_GIGA_INIT 3072/*1536*/ /* 3/4 urfs */ +#define UCC_GETH_UTFS_GIGA_INIT 8192/*2048*/ /* Tx virtual FIFO size */ +#define UCC_GETH_UTFET_GIGA_INIT 4096/*1024*/ /* 1/2 utfs */ +#define UCC_GETH_UTFTT_GIGA_INIT 0x400/*0x40*/ /* */ + +/* UCC fast alignment +*/ +#define UCC_FAST_RX_ALIGN 4 +#define UCC_FAST_MRBLR_ALIGNMENT 4 +#define UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT 8 + +/* Sizes +*/ +#define UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD 8 + +/* UCC fast structure. +*/ +typedef struct ucc_fast_info { + int ucc_num; + qe_clock_e rx_clock; + qe_clock_e tx_clock; + enet_type_e eth_type; +} ucc_fast_info_t; + +typedef struct ucc_fast_private { + ucc_fast_info_t *uf_info; + ucc_fast_t *uf_regs; /* a pointer to memory map of UCC regs */ + u32 *p_ucce; /* a pointer to the event register */ + u32 *p_uccm; /* a pointer to the mask register */ + int enabled_tx; /* whether UCC is enabled for Tx (ENT) */ + int enabled_rx; /* whether UCC is enabled for Rx (ENR) */ + u32 ucc_fast_tx_virtual_fifo_base_offset; + u32 ucc_fast_rx_virtual_fifo_base_offset; +} ucc_fast_private_t; + +void ucc_fast_transmit_on_demand(ucc_fast_private_t *uccf); +u32 ucc_fast_get_qe_cr_subblock(int ucc_num); +void ucc_fast_enable(ucc_fast_private_t *uccf, comm_dir_e mode); +void ucc_fast_disable(ucc_fast_private_t *uccf, comm_dir_e mode); +int ucc_fast_init(ucc_fast_info_t *uf_info, ucc_fast_private_t **uccf_ret); + +#endif /* __UCCF_H__ */ diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c new file mode 100644 index 0000000000..f640c81916 --- /dev/null +++ b/drivers/qe/uec.c @@ -0,0 +1,1266 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * + * Dave Liu + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "common.h" +#include "net.h" +#include "malloc.h" +#include "asm/errno.h" +#include "asm/io.h" +#include "asm/immap_qe.h" +#include "qe.h" +#include "uccf.h" +#include "uec.h" +#include "uec_phy.h" + +#if defined(CONFIG_QE) + +#ifdef CONFIG_UEC_ETH1 +static uec_info_t eth1_uec_info = { + .uf_info = { + .ucc_num = CFG_UEC1_UCC_NUM, + .rx_clock = CFG_UEC1_RX_CLK, + .tx_clock = CFG_UEC1_TX_CLK, + .eth_type = CFG_UEC1_ETH_TYPE, + }, + .num_threads_tx = UEC_NUM_OF_THREADS_4, + .num_threads_rx = UEC_NUM_OF_THREADS_4, + .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, + .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, + .tx_bd_ring_len = 16, + .rx_bd_ring_len = 16, + .phy_address = CFG_UEC1_PHY_ADDR, + .enet_interface = CFG_UEC1_INTERFACE_MODE, +}; +#endif +#ifdef CONFIG_UEC_ETH2 +static uec_info_t eth2_uec_info = { + .uf_info = { + .ucc_num = CFG_UEC2_UCC_NUM, + .rx_clock = CFG_UEC2_RX_CLK, + .tx_clock = CFG_UEC2_TX_CLK, + .eth_type = CFG_UEC2_ETH_TYPE, + }, + .num_threads_tx = UEC_NUM_OF_THREADS_4, + .num_threads_rx = UEC_NUM_OF_THREADS_4, + .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, + .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, + .tx_bd_ring_len = 16, + .rx_bd_ring_len = 16, + .phy_address = CFG_UEC2_PHY_ADDR, + .enet_interface = CFG_UEC2_INTERFACE_MODE, +}; +#endif + +static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode) +{ + uec_t *uec_regs; + u32 maccfg1; + + if (!uec) { + printf("%s: uec not initial\n", __FUNCTION__); + return -EINVAL; + } + uec_regs = uec->uec_regs; + + maccfg1 = in_be32(&uec_regs->maccfg1); + + if (mode & COMM_DIR_TX) { + maccfg1 |= MACCFG1_ENABLE_TX; + out_be32(&uec_regs->maccfg1, maccfg1); + uec->mac_tx_enabled = 1; + } + + if (mode & COMM_DIR_RX) { + maccfg1 |= MACCFG1_ENABLE_RX; + out_be32(&uec_regs->maccfg1, maccfg1); + uec->mac_rx_enabled = 1; + } + + return 0; +} + +static int uec_mac_disable(uec_private_t *uec, comm_dir_e mode) +{ + uec_t *uec_regs; + u32 maccfg1; + + if (!uec) { + printf("%s: uec not initial\n", __FUNCTION__); + return -EINVAL; + } + uec_regs = uec->uec_regs; + + maccfg1 = in_be32(&uec_regs->maccfg1); + + if (mode & COMM_DIR_TX) { + maccfg1 &= ~MACCFG1_ENABLE_TX; + out_be32(&uec_regs->maccfg1, maccfg1); + uec->mac_tx_enabled = 0; + } + + if (mode & COMM_DIR_RX) { + maccfg1 &= ~MACCFG1_ENABLE_RX; + out_be32(&uec_regs->maccfg1, maccfg1); + uec->mac_rx_enabled = 0; + } + + return 0; +} + +static int uec_graceful_stop_tx(uec_private_t *uec) +{ + ucc_fast_t *uf_regs; + u32 cecr_subblock; + u32 ucce; + + if (!uec || !uec->uccf) { + printf("%s: No handle passed.\n", __FUNCTION__); + return -EINVAL; + } + + uf_regs = uec->uccf->uf_regs; + + /* Clear the grace stop event */ + out_be32(&uf_regs->ucce, UCCE_GRA); + + /* Issue host command */ + cecr_subblock = + ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num); + qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock, + (u8)QE_CR_PROTOCOL_ETHERNET, 0); + + /* Wait for command to complete */ + do { + ucce = in_be32(&uf_regs->ucce); + } while (! (ucce & UCCE_GRA)); + + uec->grace_stopped_tx = 1; + + return 0; +} + +static int uec_graceful_stop_rx(uec_private_t *uec) +{ + u32 cecr_subblock; + u8 ack; + + if (!uec) { + printf("%s: No handle passed.\n", __FUNCTION__); + return -EINVAL; + } + + if (!uec->p_rx_glbl_pram) { + printf("%s: No init rx global parameter\n", __FUNCTION__); + return -EINVAL; + } + + /* Clear acknowledge bit */ + ack = uec->p_rx_glbl_pram->rxgstpack; + ack &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX; + uec->p_rx_glbl_pram->rxgstpack = ack; + + /* Keep issuing cmd and checking ack bit until it is asserted */ + do { + /* Issue host command */ + cecr_subblock = + ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num); + qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock, + (u8)QE_CR_PROTOCOL_ETHERNET, 0); + ack = uec->p_rx_glbl_pram->rxgstpack; + } while (! (ack & GRACEFUL_STOP_ACKNOWLEDGE_RX )); + + uec->grace_stopped_rx = 1; + + return 0; +} + +static int uec_restart_tx(uec_private_t *uec) +{ + u32 cecr_subblock; + + if (!uec || !uec->uec_info) { + printf("%s: No handle passed.\n", __FUNCTION__); + return -EINVAL; + } + + cecr_subblock = + ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num); + qe_issue_cmd(QE_RESTART_TX, cecr_subblock, + (u8)QE_CR_PROTOCOL_ETHERNET, 0); + + uec->grace_stopped_tx = 0; + + return 0; +} + +static int uec_restart_rx(uec_private_t *uec) +{ + u32 cecr_subblock; + + if (!uec || !uec->uec_info) { + printf("%s: No handle passed.\n", __FUNCTION__); + return -EINVAL; + } + + cecr_subblock = + ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num); + qe_issue_cmd(QE_RESTART_RX, cecr_subblock, + (u8)QE_CR_PROTOCOL_ETHERNET, 0); + + uec->grace_stopped_rx = 0; + + return 0; +} + +static int uec_open(uec_private_t *uec, comm_dir_e mode) +{ + ucc_fast_private_t *uccf; + + if (!uec || !uec->uccf) { + printf("%s: No handle passed.\n", __FUNCTION__); + return -EINVAL; + } + uccf = uec->uccf; + + /* check if the UCC number is in range. */ + if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) { + printf("%s: ucc_num out of range.\n", __FUNCTION__); + return -EINVAL; + } + + /* Enable MAC */ + uec_mac_enable(uec, mode); + + /* Enable UCC fast */ + ucc_fast_enable(uccf, mode); + + /* RISC microcode start */ + if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx) { + uec_restart_tx(uec); + } + if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx) { + uec_restart_rx(uec); + } + + return 0; +} + +static int uec_stop(uec_private_t *uec, comm_dir_e mode) +{ + ucc_fast_private_t *uccf; + + if (!uec || !uec->uccf) { + printf("%s: No handle passed.\n", __FUNCTION__); + return -EINVAL; + } + uccf = uec->uccf; + + /* check if the UCC number is in range. */ + if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) { + printf("%s: ucc_num out of range.\n", __FUNCTION__); + return -EINVAL; + } + /* Stop any transmissions */ + if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx) { + uec_graceful_stop_tx(uec); + } + /* Stop any receptions */ + if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx) { + uec_graceful_stop_rx(uec); + } + + /* Disable the UCC fast */ + ucc_fast_disable(uec->uccf, mode); + + /* Disable the MAC */ + uec_mac_disable(uec, mode); + + return 0; +} + +static int uec_set_mac_duplex(uec_private_t *uec, int duplex) +{ + uec_t *uec_regs; + u32 maccfg2; + + if (!uec) { + printf("%s: uec not initial\n", __FUNCTION__); + return -EINVAL; + } + uec_regs = uec->uec_regs; + + if (duplex == DUPLEX_HALF) { + maccfg2 = in_be32(&uec_regs->maccfg2); + maccfg2 &= ~MACCFG2_FDX; + out_be32(&uec_regs->maccfg2, maccfg2); + } + + if (duplex == DUPLEX_FULL) { + maccfg2 = in_be32(&uec_regs->maccfg2); + maccfg2 |= MACCFG2_FDX; + out_be32(&uec_regs->maccfg2, maccfg2); + } + + return 0; +} + +static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode) +{ + enet_interface_e enet_if_mode; + uec_info_t *uec_info; + uec_t *uec_regs; + u32 upsmr; + u32 maccfg2; + + if (!uec) { + printf("%s: uec not initial\n", __FUNCTION__); + return -EINVAL; + } + + uec_info = uec->uec_info; + uec_regs = uec->uec_regs; + enet_if_mode = if_mode; + + maccfg2 = in_be32(&uec_regs->maccfg2); + maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK; + + upsmr = in_be32(&uec->uccf->uf_regs->upsmr); + upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM); + + switch (enet_if_mode) { + case ENET_100_MII: + case ENET_10_MII: + maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; + break; + case ENET_1000_GMII: + maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE; + break; + case ENET_1000_TBI: + maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE; + upsmr |= UPSMR_TBIM; + break; + case ENET_1000_RTBI: + maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE; + upsmr |= (UPSMR_RPM | UPSMR_TBIM); + break; + case ENET_1000_RGMII: + maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE; + upsmr |= UPSMR_RPM; + break; + case ENET_100_RGMII: + maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; + upsmr |= UPSMR_RPM; + break; + case ENET_10_RGMII: + maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; + upsmr |= (UPSMR_RPM | UPSMR_R10M); + break; + case ENET_100_RMII: + maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; + upsmr |= UPSMR_RMM; + break; + case ENET_10_RMII: + maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; + upsmr |= (UPSMR_R10M | UPSMR_RMM); + break; + default: + return -EINVAL; + break; + } + out_be32(&uec_regs->maccfg2, maccfg2); + out_be32(&uec->uccf->uf_regs->upsmr, upsmr); + + return 0; +} + +static int init_mii_management_configuration(uec_t *uec_regs) +{ + uint timeout = 0x1000; + u32 miimcfg = 0; + + miimcfg = in_be32(&uec_regs->miimcfg); + miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE; + out_be32(&uec_regs->miimcfg, miimcfg); + + /* Wait until the bus is free */ + while ((in_be32(&uec_regs->miimcfg) & MIIMIND_BUSY) && timeout--); + if (timeout <= 0) { + printf("%s: The MII Bus is stuck!", __FUNCTION__); + return -ETIMEDOUT; + } + + return 0; +} + +static int init_phy(struct eth_device *dev) +{ + uec_private_t *uec; + uec_t *uec_regs; + struct uec_mii_info *mii_info; + struct phy_info *curphy; + int err; + + uec = (uec_private_t *)dev->priv; + uec_regs = uec->uec_regs; + + uec->oldlink = 0; + uec->oldspeed = 0; + uec->oldduplex = -1; + + mii_info = malloc(sizeof(*mii_info)); + if (!mii_info) { + printf("%s: Could not allocate mii_info", dev->name); + return -ENOMEM; + } + memset(mii_info, 0, sizeof(*mii_info)); + + mii_info->speed = SPEED_1000; + mii_info->duplex = DUPLEX_FULL; + mii_info->pause = 0; + mii_info->link = 1; + + mii_info->advertising = (ADVERTISED_10baseT_Half | + ADVERTISED_10baseT_Full | + ADVERTISED_100baseT_Half | + ADVERTISED_100baseT_Full | + ADVERTISED_1000baseT_Full); + mii_info->autoneg = 1; + mii_info->mii_id = uec->uec_info->phy_address; + mii_info->dev = dev; + + mii_info->mdio_read = &read_phy_reg; + mii_info->mdio_write = &write_phy_reg; + + uec->mii_info = mii_info; + + if (init_mii_management_configuration(uec_regs)) { + printf("%s: The MII Bus is stuck!", dev->name); + err = -1; + goto bus_fail; + } + + /* get info for this PHY */ + curphy = get_phy_info(uec->mii_info); + if (!curphy) { + printf("%s: No PHY found", dev->name); + err = -1; + goto no_phy; + } + + mii_info->phyinfo = curphy; + + /* Run the commands which initialize the PHY */ + if (curphy->init) { + err = curphy->init(uec->mii_info); + if (err) + goto phy_init_fail; + } + + return 0; + +phy_init_fail: +no_phy: +bus_fail: + free(mii_info); + return err; +} + +static void adjust_link(struct eth_device *dev) +{ + uec_private_t *uec = (uec_private_t *)dev->priv; + uec_t *uec_regs; + struct uec_mii_info *mii_info = uec->mii_info; + + extern void change_phy_interface_mode(struct eth_device *dev, + enet_interface_e mode); + uec_regs = uec->uec_regs; + + if (mii_info->link) { + /* Now we make sure that we can be in full duplex mode. + * If not, we operate in half-duplex mode. */ + if (mii_info->duplex != uec->oldduplex) { + if (!(mii_info->duplex)) { + uec_set_mac_duplex(uec, DUPLEX_HALF); + printf("%s: Half Duplex\n", dev->name); + } else { + uec_set_mac_duplex(uec, DUPLEX_FULL); + printf("%s: Full Duplex\n", dev->name); + } + uec->oldduplex = mii_info->duplex; + } + + if (mii_info->speed != uec->oldspeed) { + switch (mii_info->speed) { + case 1000: + break; + case 100: + printf ("switching to rgmii 100\n"); + /* change phy to rgmii 100 */ + change_phy_interface_mode(dev, + ENET_100_RGMII); + /* change the MAC interface mode */ + uec_set_mac_if_mode(uec,ENET_100_RGMII); + break; + case 10: + printf ("switching to rgmii 10\n"); + /* change phy to rgmii 10 */ + change_phy_interface_mode(dev, + ENET_10_RGMII); + /* change the MAC interface mode */ + uec_set_mac_if_mode(uec,ENET_10_RGMII); + break; + default: + printf("%s: Ack,Speed(%d)is illegal\n", + dev->name, mii_info->speed); + break; + } + + printf("%s: Speed %dBT\n", dev->name, mii_info->speed); + uec->oldspeed = mii_info->speed; + } + + if (!uec->oldlink) { + printf("%s: Link is up\n", dev->name); + uec->oldlink = 1; + } + + } else { /* if (mii_info->link) */ + if (uec->oldlink) { + printf("%s: Link is down\n", dev->name); + uec->oldlink = 0; + uec->oldspeed = 0; + uec->oldduplex = -1; + } + } +} + +static void phy_change(struct eth_device *dev) +{ + uec_private_t *uec = (uec_private_t *)dev->priv; + uec_t *uec_regs; + int result = 0; + + uec_regs = uec->uec_regs; + + /* Delay 5s to give the PHY a chance to change the register state */ + udelay(5000000); + + /* Update the link, speed, duplex */ + result = uec->mii_info->phyinfo->read_status(uec->mii_info); + + /* Adjust the interface according to speed */ + if ((0 == result) || (uec->mii_info->link == 0)) { + adjust_link(dev); + } +} + +static int uec_set_mac_address(uec_private_t *uec, u8 *mac_addr) +{ + uec_t *uec_regs; + u32 mac_addr1; + u32 mac_addr2; + + if (!uec) { + printf("%s: uec not initial\n", __FUNCTION__); + return -EINVAL; + } + + uec_regs = uec->uec_regs; + + /* if a station address of 0x12345678ABCD, perform a write to + MACSTNADDR1 of 0xCDAB7856, + MACSTNADDR2 of 0x34120000 */ + + mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) | \ + (mac_addr[3] << 8) | (mac_addr[2]); + out_be32(&uec_regs->macstnaddr1, mac_addr1); + + mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0xffff0000; + out_be32(&uec_regs->macstnaddr2, mac_addr2); + + return 0; +} + +static int uec_convert_threads_num(uec_num_of_threads_e threads_num, + int *threads_num_ret) +{ + int num_threads_numerica; + + switch (threads_num) { + case UEC_NUM_OF_THREADS_1: + num_threads_numerica = 1; + break; + case UEC_NUM_OF_THREADS_2: + num_threads_numerica = 2; + break; + case UEC_NUM_OF_THREADS_4: + num_threads_numerica = 4; + break; + case UEC_NUM_OF_THREADS_6: + num_threads_numerica = 6; + break; + case UEC_NUM_OF_THREADS_8: + num_threads_numerica = 8; + break; + default: + printf("%s: Bad number of threads value.", + __FUNCTION__); + return -EINVAL; + } + + *threads_num_ret = num_threads_numerica; + + return 0; +} + +static void uec_init_tx_parameter(uec_private_t *uec, int num_threads_tx) +{ + uec_info_t *uec_info; + u32 end_bd; + u8 bmrx = 0; + int i; + + uec_info = uec->uec_info; + + /* Alloc global Tx parameter RAM page */ + uec->tx_glbl_pram_offset = qe_muram_alloc( + sizeof(uec_tx_global_pram_t), + UEC_TX_GLOBAL_PRAM_ALIGNMENT); + uec->p_tx_glbl_pram = (uec_tx_global_pram_t *) + qe_muram_addr(uec->tx_glbl_pram_offset); + + /* Zero the global Tx prameter RAM */ + memset(uec->p_tx_glbl_pram, 0, sizeof(uec_tx_global_pram_t)); + + /* Init global Tx parameter RAM */ + + /* TEMODER, RMON statistics disable, one Tx queue */ + out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE); + + /* SQPTR */ + uec->send_q_mem_reg_offset = qe_muram_alloc( + sizeof(uec_send_queue_qd_t), + UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT); + uec->p_send_q_mem_reg = (uec_send_queue_mem_region_t *) + qe_muram_addr(uec->send_q_mem_reg_offset); + out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset); + + /* Setup the table with TxBDs ring */ + end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1) + * SIZEOFBD; + out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base, + (u32)(uec->p_tx_bd_ring)); + out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address, + end_bd); + + /* Scheduler Base Pointer, we have only one Tx queue, no need it */ + out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0); + + /* TxRMON Base Pointer, TxRMON disable, we don't need it */ + out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0); + + /* TSTATE, global snooping, big endian, the CSB bus selected */ + bmrx = BMR_INIT_VALUE; + out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT)); + + /* IPH_Offset */ + for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++) { + out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0); + } + + /* VTAG table */ + for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++) { + out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0); + } + + /* TQPTR */ + uec->thread_dat_tx_offset = qe_muram_alloc( + num_threads_tx * sizeof(uec_thread_data_tx_t) + + 32 *(num_threads_tx == 1), UEC_THREAD_DATA_ALIGNMENT); + + uec->p_thread_data_tx = (uec_thread_data_tx_t *) + qe_muram_addr(uec->thread_dat_tx_offset); + out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset); +} + +static void uec_init_rx_parameter(uec_private_t *uec, int num_threads_rx) +{ + u8 bmrx = 0; + int i; + uec_82xx_address_filtering_pram_t *p_af_pram; + + /* Allocate global Rx parameter RAM page */ + uec->rx_glbl_pram_offset = qe_muram_alloc( + sizeof(uec_rx_global_pram_t), UEC_RX_GLOBAL_PRAM_ALIGNMENT); + uec->p_rx_glbl_pram = (uec_rx_global_pram_t *) + qe_muram_addr(uec->rx_glbl_pram_offset); + + /* Zero Global Rx parameter RAM */ + memset(uec->p_rx_glbl_pram, 0, sizeof(uec_rx_global_pram_t)); + + /* Init global Rx parameter RAM */ + /* REMODER, Extended feature mode disable, VLAN disable, + LossLess flow control disable, Receive firmware statisic disable, + Extended address parsing mode disable, One Rx queues, + Dynamic maximum/minimum frame length disable, IP checksum check + disable, IP address alignment disable + */ + out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE); + + /* RQPTR */ + uec->thread_dat_rx_offset = qe_muram_alloc( + num_threads_rx * sizeof(uec_thread_data_rx_t), + UEC_THREAD_DATA_ALIGNMENT); + uec->p_thread_data_rx = (uec_thread_data_rx_t *) + qe_muram_addr(uec->thread_dat_rx_offset); + out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset); + + /* Type_or_Len */ + out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072); + + /* RxRMON base pointer, we don't need it */ + out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0); + + /* IntCoalescingPTR, we don't need it, no interrupt */ + out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0); + + /* RSTATE, global snooping, big endian, the CSB bus selected */ + bmrx = BMR_INIT_VALUE; + out_8(&uec->p_rx_glbl_pram->rstate, bmrx); + + /* MRBLR */ + out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN); + + /* RBDQPTR */ + uec->rx_bd_qs_tbl_offset = qe_muram_alloc( + sizeof(uec_rx_bd_queues_entry_t) + \ + sizeof(uec_rx_prefetched_bds_t), + UEC_RX_BD_QUEUES_ALIGNMENT); + uec->p_rx_bd_qs_tbl = (uec_rx_bd_queues_entry_t *) + qe_muram_addr(uec->rx_bd_qs_tbl_offset); + + /* Zero it */ + memset(uec->p_rx_bd_qs_tbl, 0, sizeof(uec_rx_bd_queues_entry_t) + \ + sizeof(uec_rx_prefetched_bds_t)); + out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset); + out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr, + (u32)uec->p_rx_bd_ring); + + /* MFLR */ + out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN); + /* MINFLR */ + out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN); + /* MAXD1 */ + out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN); + /* MAXD2 */ + out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN); + /* ECAM_PTR */ + out_be32(&uec->p_rx_glbl_pram->ecamptr, 0); + /* L2QT */ + out_be32(&uec->p_rx_glbl_pram->l2qt, 0); + /* L3QT */ + for (i = 0; i < 8; i++) { + out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0); + } + + /* VLAN_TYPE */ + out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100); + /* TCI */ + out_be16(&uec->p_rx_glbl_pram->vlantci, 0); + + /* Clear PQ2 style address filtering hash table */ + p_af_pram = (uec_82xx_address_filtering_pram_t *) \ + uec->p_rx_glbl_pram->addressfiltering; + + p_af_pram->iaddr_h = 0; + p_af_pram->iaddr_l = 0; + p_af_pram->gaddr_h = 0; + p_af_pram->gaddr_l = 0; +} + +static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec, + int thread_tx, int thread_rx) +{ + uec_init_cmd_pram_t *p_init_enet_param; + u32 init_enet_param_offset; + uec_info_t *uec_info; + int i; + int snum; + u32 init_enet_offset; + u32 entry_val; + u32 command; + u32 cecr_subblock; + + uec_info = uec->uec_info; + + /* Allocate init enet command parameter */ + uec->init_enet_param_offset = qe_muram_alloc( + sizeof(uec_init_cmd_pram_t), 4); + init_enet_param_offset = uec->init_enet_param_offset; + uec->p_init_enet_param = (uec_init_cmd_pram_t *) + qe_muram_addr(uec->init_enet_param_offset); + + /* Zero init enet command struct */ + memset((void *)uec->p_init_enet_param, 0, sizeof(uec_init_cmd_pram_t)); + + /* Init the command struct */ + p_init_enet_param = uec->p_init_enet_param; + p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0; + p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1; + p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2; + p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3; + p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4; + p_init_enet_param->largestexternallookupkeysize = 0; + + p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx) + << ENET_INIT_PARAM_RGF_SHIFT; + p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx) + << ENET_INIT_PARAM_TGF_SHIFT; + + /* Init Rx global parameter pointer */ + p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset | + (u32)uec_info->riscRx; + + /* Init Rx threads */ + for (i = 0; i < (thread_rx + 1); i++) { + if ((snum = qe_get_snum()) < 0) { + printf("%s can not get snum\n", __FUNCTION__); + return -ENOMEM; + } + + if (i==0) { + init_enet_offset = 0; + } else { + init_enet_offset = qe_muram_alloc( + sizeof(uec_thread_rx_pram_t), + UEC_THREAD_RX_PRAM_ALIGNMENT); + } + + entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) | + init_enet_offset | (u32)uec_info->riscRx; + p_init_enet_param->rxthread[i] = entry_val; + } + + /* Init Tx global parameter pointer */ + p_init_enet_param->txglobal = uec->tx_glbl_pram_offset | + (u32)uec_info->riscTx; + + /* Init Tx threads */ + for (i = 0; i < thread_tx; i++) { + if ((snum = qe_get_snum()) < 0) { + printf("%s can not get snum\n", __FUNCTION__); + return -ENOMEM; + } + + init_enet_offset = qe_muram_alloc(sizeof(uec_thread_tx_pram_t), + UEC_THREAD_TX_PRAM_ALIGNMENT); + + entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) | + init_enet_offset | (u32)uec_info->riscTx; + p_init_enet_param->txthread[i] = entry_val; + } + + __asm__ __volatile__("sync"); + + /* Issue QE command */ + command = QE_INIT_TX_RX; + cecr_subblock = ucc_fast_get_qe_cr_subblock( + uec->uec_info->uf_info.ucc_num); + qe_issue_cmd(command, cecr_subblock, (u8) QE_CR_PROTOCOL_ETHERNET, + init_enet_param_offset); + + return 0; +} + +static int uec_startup(uec_private_t *uec) +{ + uec_info_t *uec_info; + ucc_fast_info_t *uf_info; + ucc_fast_private_t *uccf; + ucc_fast_t *uf_regs; + uec_t *uec_regs; + int num_threads_tx; + int num_threads_rx; + u32 utbipar; + enet_interface_e enet_interface; + u32 length; + u32 align; + qe_bd_t *bd; + u8 *buf; + int i; + + if (!uec || !uec->uec_info) { + printf("%s: uec or uec_info not initial\n", __FUNCTION__); + return -EINVAL; + } + + uec_info = uec->uec_info; + uf_info = &(uec_info->uf_info); + + /* Check if Rx BD ring len is illegal */ + if ((uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN) || \ + (uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT)) { + printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n", + __FUNCTION__); + return -EINVAL; + } + + /* Check if Tx BD ring len is illegal */ + if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) { + printf("%s: Tx BD ring length must not be smaller than 2.\n", + __FUNCTION__); + return -EINVAL; + } + + /* Check if MRBLR is illegal */ + if ((MAX_RXBUF_LEN == 0) || (MAX_RXBUF_LEN % UEC_MRBLR_ALIGNMENT)) { + printf("%s: max rx buffer length must be mutliple of 128.\n", + __FUNCTION__); + return -EINVAL; + } + + /* Both Rx and Tx are stopped */ + uec->grace_stopped_rx = 1; + uec->grace_stopped_tx = 1; + + /* Init UCC fast */ + if (ucc_fast_init(uf_info, &uccf)) { + printf("%s: failed to init ucc fast\n", __FUNCTION__); + return -ENOMEM; + } + + /* Save uccf */ + uec->uccf = uccf; + + /* Convert the Tx threads number */ + if (uec_convert_threads_num(uec_info->num_threads_tx, + &num_threads_tx)) { + return -EINVAL; + } + + /* Convert the Rx threads number */ + if (uec_convert_threads_num(uec_info->num_threads_rx, + &num_threads_rx)) { + return -EINVAL; + } + + uf_regs = uccf->uf_regs; + + /* UEC register is following UCC fast registers */ + uec_regs = (uec_t *)(&uf_regs->ucc_eth); + + /* Save the UEC register pointer to UEC private struct */ + uec->uec_regs = uec_regs; + + /* Init UPSMR, enable hardware statistics (UCC) */ + out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE); + + /* Init MACCFG1, flow control disable, disable Tx and Rx */ + out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE); + + /* Init MACCFG2, length check, MAC PAD and CRC enable */ + out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE); + + /* Setup MAC interface mode */ + uec_set_mac_if_mode(uec, uec_info->enet_interface); + + /* Setup MII master clock source */ + qe_set_mii_clk_src(uec_info->uf_info.ucc_num); + + /* Setup UTBIPAR */ + utbipar = in_be32(&uec_regs->utbipar); + utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK; + enet_interface = uec->uec_info->enet_interface; + if (enet_interface == ENET_1000_TBI || + enet_interface == ENET_1000_RTBI) { + utbipar |= (uec_info->phy_address + uec_info->uf_info.ucc_num) + << UTBIPAR_PHY_ADDRESS_SHIFT; + } else { + utbipar |= (0x10 + uec_info->uf_info.ucc_num) + << UTBIPAR_PHY_ADDRESS_SHIFT; + } + + out_be32(&uec_regs->utbipar, utbipar); + + /* Allocate Tx BDs */ + length = ((uec_info->tx_bd_ring_len * SIZEOFBD) / + UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) * + UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT; + if ((uec_info->tx_bd_ring_len * SIZEOFBD) % + UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) { + length += UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT; + } + + align = UEC_TX_BD_RING_ALIGNMENT; + uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align)); + if (uec->tx_bd_ring_offset != 0) { + uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align) + & ~(align - 1)); + } + + /* Zero all of Tx BDs */ + memset((void *)(uec->tx_bd_ring_offset), 0, length + align); + + /* Allocate Rx BDs */ + length = uec_info->rx_bd_ring_len * SIZEOFBD; + align = UEC_RX_BD_RING_ALIGNMENT; + uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align))); + if (uec->rx_bd_ring_offset != 0) { + uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align) + & ~(align - 1)); + } + + /* Zero all of Rx BDs */ + memset((void *)(uec->rx_bd_ring_offset), 0, length + align); + + /* Allocate Rx buffer */ + length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN; + align = UEC_RX_DATA_BUF_ALIGNMENT; + uec->rx_buf_offset = (u32)malloc(length + align); + if (uec->rx_buf_offset != 0) { + uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align) + & ~(align - 1)); + } + + /* Zero all of the Rx buffer */ + memset((void *)(uec->rx_buf_offset), 0, length + align); + + /* Init TxBD ring */ + bd = (qe_bd_t *)uec->p_tx_bd_ring; + uec->txBd = bd; + + for (i = 0; i < uec_info->tx_bd_ring_len; i++) { + BD_DATA_CLEAR(bd); + BD_STATUS_SET(bd, 0); + BD_LENGTH_SET(bd, 0); + bd ++; + } + BD_STATUS_SET((--bd), TxBD_WRAP); + + /* Init RxBD ring */ + bd = (qe_bd_t *)uec->p_rx_bd_ring; + uec->rxBd = bd; + buf = uec->p_rx_buf; + for (i = 0; i < uec_info->rx_bd_ring_len; i++) { + BD_DATA_SET(bd, buf); + BD_LENGTH_SET(bd, 0); + BD_STATUS_SET(bd, RxBD_EMPTY); + buf += MAX_RXBUF_LEN; + bd ++; + } + BD_STATUS_SET((--bd), RxBD_WRAP | RxBD_EMPTY); + + /* Init global Tx parameter RAM */ + uec_init_tx_parameter(uec, num_threads_tx); + + /* Init global Rx parameter RAM */ + uec_init_rx_parameter(uec, num_threads_rx); + + /* Init ethernet Tx and Rx parameter command */ + if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx, + num_threads_rx)) { + printf("%s issue init enet cmd failed\n", __FUNCTION__); + return -ENOMEM; + } + + return 0; +} + +static int uec_init(struct eth_device* dev, bd_t *bd) +{ + uec_private_t *uec; + int err; + + uec = (uec_private_t *)dev->priv; + + if (uec->the_first_run == 0) { + /* Set up the MAC address */ + if (dev->enetaddr[0] & 0x01) { + printf("%s: MacAddress is multcast address\n", + __FUNCTION__); + return -EINVAL; + } + uec_set_mac_address(uec, dev->enetaddr); + uec->the_first_run = 1; + } + + err = uec_open(uec, COMM_DIR_RX_AND_TX); + if (err) { + printf("%s: cannot enable UEC device\n", dev->name); + return err; + } + + return 0; +} + +static void uec_halt(struct eth_device* dev) +{ + uec_private_t *uec = (uec_private_t *)dev->priv; + uec_stop(uec, COMM_DIR_RX_AND_TX); +} + +static int uec_send(struct eth_device* dev, volatile void *buf, int len) +{ + uec_private_t *uec; + ucc_fast_private_t *uccf; + volatile qe_bd_t *bd; + volatile u16 status; + int i; + int result = 0; + + uec = (uec_private_t *)dev->priv; + uccf = uec->uccf; + bd = uec->txBd; + + /* Find an empty TxBD */ + for (i = 0; BD_STATUS(bd) & TxBD_READY; i++) { + if (i > 0x100000) { + printf("%s: tx buffer not ready\n", dev->name); + return result; + } + } + + /* Init TxBD */ + BD_DATA_SET(bd, buf); + BD_LENGTH_SET(bd, len); + status = BD_STATUS(bd); + status &= BD_WRAP; + status |= (TxBD_READY | TxBD_LAST); + BD_STATUS_SET(bd, status); + + /* Tell UCC to transmit the buffer */ + ucc_fast_transmit_on_demand(uccf); + + /* Wait for buffer to be transmitted */ + status = BD_STATUS(bd); + for (i = 0; status & TxBD_READY; i++) { + if (i > 0x100000) { + printf("%s: tx error\n", dev->name); + return result; + } + status = BD_STATUS(bd); + } + + /* Ok, the buffer be transimitted */ + BD_ADVANCE(bd, status, uec->p_tx_bd_ring); + uec->txBd = bd; + result = 1; + + return result; +} + +static int uec_recv(struct eth_device* dev) +{ + uec_private_t *uec = dev->priv; + volatile qe_bd_t *bd; + volatile u16 status; + u16 len; + u8 *data; + + bd = uec->rxBd; + status = BD_STATUS(bd); + + while (!(status & RxBD_EMPTY)) { + if (!(status & RxBD_ERROR)) { + data = BD_DATA(bd); + len = BD_LENGTH(bd); + NetReceive(data, len); + } else { + printf("%s: Rx error\n", dev->name); + } + status &= BD_CLEAN; + BD_LENGTH_SET(bd, 0); + BD_STATUS_SET(bd, status | RxBD_EMPTY); + BD_ADVANCE(bd, status, uec->p_rx_bd_ring); + status = BD_STATUS(bd); + } + uec->rxBd = bd; + + return 1; +} + +int uec_initialize(int index) +{ + struct eth_device *dev; + int i; + uec_private_t *uec; + uec_info_t *uec_info; + int err; + + dev = (struct eth_device *)malloc(sizeof(struct eth_device)); + if (!dev) + return 0; + memset(dev, 0, sizeof(struct eth_device)); + + /* Allocate the UEC private struct */ + uec = (uec_private_t *)malloc(sizeof(uec_private_t)); + if (!uec) { + return -ENOMEM; + } + memset(uec, 0, sizeof(uec_private_t)); + + /* Init UEC private struct, they come from board.h */ + if (index == 0) { +#ifdef CONFIG_UEC_ETH1 + uec_info = ð1_uec_info; +#endif + } else if (index == 1) { +#ifdef CONFIG_UEC_ETH2 + uec_info = ð2_uec_info; +#endif + } else { + printf("%s: index is illegal.\n", __FUNCTION__); + return -EINVAL; + } + + uec->uec_info = uec_info; + + sprintf(dev->name, "FSL UEC%d", index); + dev->iobase = 0; + dev->priv = (void *)uec; + dev->init = uec_init; + dev->halt = uec_halt; + dev->send = uec_send; + dev->recv = uec_recv; + + /* Clear the ethnet address */ + for (i = 0; i < 6; i++) + dev->enetaddr[i] = 0; + + eth_register(dev); + + err = uec_startup(uec); + if (err) { + printf("%s: Cannot configure net device, aborting.",dev->name); + return err; + } + + err = init_phy(dev); + if (err) { + printf("%s: Cannot initialize PHY, aborting.\n", dev->name); + return err; + } + + phy_change(dev); + + return 1; +} +#endif /* CONFIG_QE */ diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h new file mode 100644 index 0000000000..04950264b8 --- /dev/null +++ b/drivers/qe/uec.h @@ -0,0 +1,716 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * + * Dave Liu + * based on source code of Shlomi Gridish + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __UEC_H__ +#define __UEC_H__ + +#define MAX_TX_THREADS 8 +#define MAX_RX_THREADS 8 +#define MAX_TX_QUEUES 8 +#define MAX_RX_QUEUES 8 +#define MAX_PREFETCHED_BDS 4 +#define MAX_IPH_OFFSET_ENTRY 8 +#define MAX_ENET_INIT_PARAM_ENTRIES_RX 9 +#define MAX_ENET_INIT_PARAM_ENTRIES_TX 8 + +/* UEC UPSMR (Protocol Specific Mode Register) + */ +#define UPSMR_ECM 0x04000000 /* Enable CAM Miss */ +#define UPSMR_HSE 0x02000000 /* Hardware Statistics Enable */ +#define UPSMR_PRO 0x00400000 /* Promiscuous */ +#define UPSMR_CAP 0x00200000 /* CAM polarity */ +#define UPSMR_RSH 0x00100000 /* Receive Short Frames */ +#define UPSMR_RPM 0x00080000 /* Reduced Pin Mode interfaces */ +#define UPSMR_R10M 0x00040000 /* RGMII/RMII 10 Mode */ +#define UPSMR_RLPB 0x00020000 /* RMII Loopback Mode */ +#define UPSMR_TBIM 0x00010000 /* Ten-bit Interface Mode */ +#define UPSMR_RMM 0x00001000 /* RMII/RGMII Mode */ +#define UPSMR_CAM 0x00000400 /* CAM Address Matching */ +#define UPSMR_BRO 0x00000200 /* Broadcast Address */ +#define UPSMR_RES1 0x00002000 /* Reserved feild - must be 1 */ + +#define UPSMR_INIT_VALUE (UPSMR_HSE | UPSMR_RES1) + +/* UEC MACCFG1 (MAC Configuration 1 Register) + */ +#define MACCFG1_FLOW_RX 0x00000020 /* Flow Control Rx */ +#define MACCFG1_FLOW_TX 0x00000010 /* Flow Control Tx */ +#define MACCFG1_ENABLE_SYNCHED_RX 0x00000008 /* Enable Rx Sync */ +#define MACCFG1_ENABLE_RX 0x00000004 /* Enable Rx */ +#define MACCFG1_ENABLE_SYNCHED_TX 0x00000002 /* Enable Tx Sync */ +#define MACCFG1_ENABLE_TX 0x00000001 /* Enable Tx */ + +#define MACCFG1_INIT_VALUE (0) + +/* UEC MACCFG2 (MAC Configuration 2 Register) + */ +#define MACCFG2_PREL 0x00007000 +#define MACCFG2_PREL_SHIFT (31 - 19) +#define MACCFG2_PREL_MASK 0x0000f000 +#define MACCFG2_SRP 0x00000080 +#define MACCFG2_STP 0x00000040 +#define MACCFG2_RESERVED_1 0x00000020 /* must be set */ +#define MACCFG2_LC 0x00000010 /* Length Check */ +#define MACCFG2_MPE 0x00000008 +#define MACCFG2_FDX 0x00000001 /* Full Duplex */ +#define MACCFG2_FDX_MASK 0x00000001 +#define MACCFG2_PAD_CRC 0x00000004 +#define MACCFG2_CRC_EN 0x00000002 +#define MACCFG2_PAD_AND_CRC_MODE_NONE 0x00000000 +#define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY 0x00000002 +#define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC 0x00000004 +#define MACCFG2_INTERFACE_MODE_NIBBLE 0x00000100 +#define MACCFG2_INTERFACE_MODE_BYTE 0x00000200 +#define MACCFG2_INTERFACE_MODE_MASK 0x00000300 + +#define MACCFG2_INIT_VALUE (MACCFG2_PREL | MACCFG2_RESERVED_1 | \ + MACCFG2_LC | MACCFG2_PAD_CRC | MACCFG2_FDX) + +/* UEC Event Register +*/ +#define UCCE_MPD 0x80000000 +#define UCCE_SCAR 0x40000000 +#define UCCE_GRA 0x20000000 +#define UCCE_CBPR 0x10000000 +#define UCCE_BSY 0x08000000 +#define UCCE_RXC 0x04000000 +#define UCCE_TXC 0x02000000 +#define UCCE_TXE 0x01000000 +#define UCCE_TXB7 0x00800000 +#define UCCE_TXB6 0x00400000 +#define UCCE_TXB5 0x00200000 +#define UCCE_TXB4 0x00100000 +#define UCCE_TXB3 0x00080000 +#define UCCE_TXB2 0x00040000 +#define UCCE_TXB1 0x00020000 +#define UCCE_TXB0 0x00010000 +#define UCCE_RXB7 0x00008000 +#define UCCE_RXB6 0x00004000 +#define UCCE_RXB5 0x00002000 +#define UCCE_RXB4 0x00001000 +#define UCCE_RXB3 0x00000800 +#define UCCE_RXB2 0x00000400 +#define UCCE_RXB1 0x00000200 +#define UCCE_RXB0 0x00000100 +#define UCCE_RXF7 0x00000080 +#define UCCE_RXF6 0x00000040 +#define UCCE_RXF5 0x00000020 +#define UCCE_RXF4 0x00000010 +#define UCCE_RXF3 0x00000008 +#define UCCE_RXF2 0x00000004 +#define UCCE_RXF1 0x00000002 +#define UCCE_RXF0 0x00000001 + +#define UCCE_TXB (UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 | \ + UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0) +#define UCCE_RXB (UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 | \ + UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0) +#define UCCE_RXF (UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 | \ + UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0) +#define UCCE_OTHER (UCCE_SCAR | UCCE_GRA | UCCE_CBPR | UCCE_BSY | \ + UCCE_RXC | UCCE_TXC | UCCE_TXE) + +/* UEC TEMODR Register +*/ +#define TEMODER_SCHEDULER_ENABLE 0x2000 +#define TEMODER_IP_CHECKSUM_GENERATE 0x0400 +#define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1 0x0200 +#define TEMODER_RMON_STATISTICS 0x0100 +#define TEMODER_NUM_OF_QUEUES_SHIFT (15-15) + +#define TEMODER_INIT_VALUE 0xc000 + +/* UEC REMODR Register +*/ +#define REMODER_RX_RMON_STATISTICS_ENABLE 0x00001000 +#define REMODER_RX_EXTENDED_FEATURES 0x80000000 +#define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31-9 ) +#define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10) +#define REMODER_RX_QOS_MODE_SHIFT (31-15) +#define REMODER_RMON_STATISTICS 0x00001000 +#define REMODER_RX_EXTENDED_FILTERING 0x00000800 +#define REMODER_NUM_OF_QUEUES_SHIFT (31-23) +#define REMODER_DYNAMIC_MAX_FRAME_LENGTH 0x00000008 +#define REMODER_DYNAMIC_MIN_FRAME_LENGTH 0x00000004 +#define REMODER_IP_CHECKSUM_CHECK 0x00000002 +#define REMODER_IP_ADDRESS_ALIGNMENT 0x00000001 + +#define REMODER_INIT_VALUE 0 + +/* BMRx - Bus Mode Register */ +#define BMR_GLB 0x20 +#define BMR_BO_BE 0x10 +#define BMR_DTB_SECONDARY_BUS 0x02 +#define BMR_BDB_SECONDARY_BUS 0x01 + +#define BMR_SHIFT 24 +#define BMR_INIT_VALUE (BMR_GLB | BMR_BO_BE) + +/* UEC UCCS (Ethernet Status Register) + */ +#define UCCS_BPR 0x02 +#define UCCS_PAU 0x02 +#define UCCS_MPD 0x01 + +/* UEC MIIMCFG (MII Management Configuration Register) + */ +#define MIIMCFG_RESET_MANAGEMENT 0x80000000 +#define MIIMCFG_NO_PREAMBLE 0x00000010 +#define MIIMCFG_CLOCK_DIVIDE_SHIFT (31 - 31) +#define MIIMCFG_CLOCK_DIVIDE_MASK 0x0000000f +#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_4 0x00000001 +#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_6 0x00000002 +#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_8 0x00000003 +#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10 0x00000004 +#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_14 0x00000005 +#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_20 0x00000006 +#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_28 0x00000007 + +#define MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE \ + MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10 + +/* UEC MIIMCOM (MII Management Command Register) + */ +#define MIIMCOM_SCAN_CYCLE 0x00000002 /* Scan cycle */ +#define MIIMCOM_READ_CYCLE 0x00000001 /* Read cycle */ + +/* UEC MIIMADD (MII Management Address Register) + */ +#define MIIMADD_PHY_ADDRESS_SHIFT (31 - 23) +#define MIIMADD_PHY_REGISTER_SHIFT (31 - 31) + +/* UEC MIIMCON (MII Management Control Register) + */ +#define MIIMCON_PHY_CONTROL_SHIFT (31 - 31) +#define MIIMCON_PHY_STATUS_SHIFT (31 - 31) + +/* UEC MIIMIND (MII Management Indicator Register) + */ +#define MIIMIND_NOT_VALID 0x00000004 +#define MIIMIND_SCAN 0x00000002 +#define MIIMIND_BUSY 0x00000001 + +/* UEC UTBIPAR (Ten Bit Interface Physical Address Register) + */ +#define UTBIPAR_PHY_ADDRESS_SHIFT (31 - 31) +#define UTBIPAR_PHY_ADDRESS_MASK 0x0000001f + +/* UEC UESCR (Ethernet Statistics Control Register) + */ +#define UESCR_AUTOZ 0x8000 +#define UESCR_CLRCNT 0x4000 +#define UESCR_MAXCOV_SHIFT (15 - 7) +#define UESCR_SCOV_SHIFT (15 - 15) + +/****** Tx data struct collection ******/ +/* Tx thread data, each Tx thread has one this struct. +*/ +typedef struct uec_thread_data_tx { + u8 res0[136]; +} __attribute__ ((packed)) uec_thread_data_tx_t; + +/* Tx thread parameter, each Tx thread has one this struct. +*/ +typedef struct uec_thread_tx_pram { + u8 res0[64]; +} __attribute__ ((packed)) uec_thread_tx_pram_t; + +/* Send queue queue-descriptor, each Tx queue has one this QD +*/ +typedef struct uec_send_queue_qd { + u32 bd_ring_base; /* pointer to BD ring base address */ + u8 res0[0x8]; + u32 last_bd_completed_address; /* last entry in BD ring */ + u8 res1[0x30]; +} __attribute__ ((packed)) uec_send_queue_qd_t; + +/* Send queue memory region */ +typedef struct uec_send_queue_mem_region { + uec_send_queue_qd_t sqqd[MAX_TX_QUEUES]; +} __attribute__ ((packed)) uec_send_queue_mem_region_t; + +/* Scheduler struct +*/ +typedef struct uec_scheduler { + u16 cpucount0; /* CPU packet counter */ + u16 cpucount1; /* CPU packet counter */ + u16 cecount0; /* QE packet counter */ + u16 cecount1; /* QE packet counter */ + u16 cpucount2; /* CPU packet counter */ + u16 cpucount3; /* CPU packet counter */ + u16 cecount2; /* QE packet counter */ + u16 cecount3; /* QE packet counter */ + u16 cpucount4; /* CPU packet counter */ + u16 cpucount5; /* CPU packet counter */ + u16 cecount4; /* QE packet counter */ + u16 cecount5; /* QE packet counter */ + u16 cpucount6; /* CPU packet counter */ + u16 cpucount7; /* CPU packet counter */ + u16 cecount6; /* QE packet counter */ + u16 cecount7; /* QE packet counter */ + u32 weightstatus[MAX_TX_QUEUES]; /* accumulated weight factor */ + u32 rtsrshadow; /* temporary variable handled by QE */ + u32 time; /* temporary variable handled by QE */ + u32 ttl; /* temporary variable handled by QE */ + u32 mblinterval; /* max burst length interval */ + u16 nortsrbytetime; /* normalized value of byte time in tsr units */ + u8 fracsiz; + u8 res0[1]; + u8 strictpriorityq; /* Strict Priority Mask register */ + u8 txasap; /* Transmit ASAP register */ + u8 extrabw; /* Extra BandWidth register */ + u8 oldwfqmask; /* temporary variable handled by QE */ + u8 weightfactor[MAX_TX_QUEUES]; /**< weight factor for queues */ + u32 minw; /* temporary variable handled by QE */ + u8 res1[0x70-0x64]; +} __attribute__ ((packed)) uec_scheduler_t; + +/* Tx firmware counters +*/ +typedef struct uec_tx_firmware_statistics_pram { + u32 sicoltx; /* single collision */ + u32 mulcoltx; /* multiple collision */ + u32 latecoltxfr; /* late collision */ + u32 frabortduecol; /* frames aborted due to tx collision */ + u32 frlostinmactxer; /* frames lost due to internal MAC error tx */ + u32 carriersenseertx; /* carrier sense error */ + u32 frtxok; /* frames transmitted OK */ + u32 txfrexcessivedefer; + u32 txpkts256; /* total packets(including bad) 256~511 B */ + u32 txpkts512; /* total packets(including bad) 512~1023B */ + u32 txpkts1024; /* total packets(including bad) 1024~1518B */ + u32 txpktsjumbo; /* total packets(including bad) >1024 */ +} __attribute__ ((packed)) uec_tx_firmware_statistics_pram_t; + +/* Tx global parameter table +*/ +typedef struct uec_tx_global_pram { + u16 temoder; + u8 res0[0x38-0x02]; + u32 sqptr; + u32 schedulerbasepointer; + u32 txrmonbaseptr; + u32 tstate; + u8 iphoffset[MAX_IPH_OFFSET_ENTRY]; + u32 vtagtable[0x8]; + u32 tqptr; + u8 res2[0x80-0x74]; +} __attribute__ ((packed)) uec_tx_global_pram_t; + + +/****** Rx data struct collection ******/ +/* Rx thread data, each Rx thread has one this struct. +*/ +typedef struct uec_thread_data_rx { + u8 res0[40]; +} __attribute__ ((packed)) uec_thread_data_rx_t; + +/* Rx thread parameter, each Rx thread has one this struct. +*/ +typedef struct uec_thread_rx_pram { + u8 res0[128]; +} __attribute__ ((packed)) uec_thread_rx_pram_t; + +/* Rx firmware counters +*/ +typedef struct uec_rx_firmware_statistics_pram { + u32 frrxfcser; /* frames with crc error */ + u32 fraligner; /* frames with alignment error */ + u32 inrangelenrxer; /* in range length error */ + u32 outrangelenrxer; /* out of range length error */ + u32 frtoolong; /* frame too long */ + u32 runt; /* runt */ + u32 verylongevent; /* very long event */ + u32 symbolerror; /* symbol error */ + u32 dropbsy; /* drop because of BD not ready */ + u8 res0[0x8]; + u32 mismatchdrop; /* drop because of MAC filtering */ + u32 underpkts; /* total frames less than 64 octets */ + u32 pkts256; /* total frames(including bad)256~511 B */ + u32 pkts512; /* total frames(including bad)512~1023 B */ + u32 pkts1024; /* total frames(including bad)1024~1518 B */ + u32 pktsjumbo; /* total frames(including bad) >1024 B */ + u32 frlossinmacer; + u32 pausefr; /* pause frames */ + u8 res1[0x4]; + u32 removevlan; + u32 replacevlan; + u32 insertvlan; +} __attribute__ ((packed)) uec_rx_firmware_statistics_pram_t; + +/* Rx interrupt coalescing entry, each Rx queue has one this entry. +*/ +typedef struct uec_rx_interrupt_coalescing_entry { + u32 maxvalue; + u32 counter; +} __attribute__ ((packed)) uec_rx_interrupt_coalescing_entry_t; + +typedef struct uec_rx_interrupt_coalescing_table { + uec_rx_interrupt_coalescing_entry_t entry[MAX_RX_QUEUES]; +} __attribute__ ((packed)) uec_rx_interrupt_coalescing_table_t; + +/* RxBD queue entry, each Rx queue has one this entry. +*/ +typedef struct uec_rx_bd_queues_entry { + u32 bdbaseptr; /* BD base pointer */ + u32 bdptr; /* BD pointer */ + u32 externalbdbaseptr; /* external BD base pointer */ + u32 externalbdptr; /* external BD pointer */ +} __attribute__ ((packed)) uec_rx_bd_queues_entry_t; + +/* Rx global paramter table +*/ +typedef struct uec_rx_global_pram { + u32 remoder; /* ethernet mode reg. */ + u32 rqptr; /* base pointer to the Rx Queues */ + u32 res0[0x1]; + u8 res1[0x20-0xC]; + u16 typeorlen; + u8 res2[0x1]; + u8 rxgstpack; /* ack on GRACEFUL STOP RX command */ + u32 rxrmonbaseptr; /* Rx RMON statistics base */ + u8 res3[0x30-0x28]; + u32 intcoalescingptr; /* Interrupt coalescing table pointer */ + u8 res4[0x36-0x34]; + u8 rstate; + u8 res5[0x46-0x37]; + u16 mrblr; /* max receive buffer length reg. */ + u32 rbdqptr; /* RxBD parameter table description */ + u16 mflr; /* max frame length reg. */ + u16 minflr; /* min frame length reg. */ + u16 maxd1; /* max dma1 length reg. */ + u16 maxd2; /* max dma2 length reg. */ + u32 ecamptr; /* external CAM address */ + u32 l2qt; /* VLAN priority mapping table. */ + u32 l3qt[0x8]; /* IP priority mapping table. */ + u16 vlantype; /* vlan type */ + u16 vlantci; /* default vlan tci */ + u8 addressfiltering[64];/* address filtering data structure */ + u32 exfGlobalParam; /* extended filtering global parameters */ + u8 res6[0x100-0xC4]; /* Initialize to zero */ +} __attribute__ ((packed)) uec_rx_global_pram_t; + +#define GRACEFUL_STOP_ACKNOWLEDGE_RX 0x01 + + +/****** UEC common ******/ +/* UCC statistics - hardware counters +*/ +typedef struct uec_hardware_statistics { + u32 tx64; + u32 tx127; + u32 tx255; + u32 rx64; + u32 rx127; + u32 rx255; + u32 txok; + u16 txcf; + u32 tmca; + u32 tbca; + u32 rxfok; + u32 rxbok; + u32 rbyt; + u32 rmca; + u32 rbca; +} __attribute__ ((packed)) uec_hardware_statistics_t; + +/* InitEnet command parameter +*/ +typedef struct uec_init_cmd_pram { + u8 resinit0; + u8 resinit1; + u8 resinit2; + u8 resinit3; + u16 resinit4; + u8 res1[0x1]; + u8 largestexternallookupkeysize; + u32 rgftgfrxglobal; + u32 rxthread[MAX_ENET_INIT_PARAM_ENTRIES_RX]; /* rx threads */ + u8 res2[0x38 - 0x30]; + u32 txglobal; /* tx global */ + u32 txthread[MAX_ENET_INIT_PARAM_ENTRIES_TX]; /* tx threads */ + u8 res3[0x1]; +} __attribute__ ((packed)) uec_init_cmd_pram_t; + +#define ENET_INIT_PARAM_RGF_SHIFT (32 - 4) +#define ENET_INIT_PARAM_TGF_SHIFT (32 - 8) + +#define ENET_INIT_PARAM_RISC_MASK 0x0000003f +#define ENET_INIT_PARAM_PTR_MASK 0x00ffffc0 +#define ENET_INIT_PARAM_SNUM_MASK 0xff000000 +#define ENET_INIT_PARAM_SNUM_SHIFT 24 + +#define ENET_INIT_PARAM_MAGIC_RES_INIT0 0x06 +#define ENET_INIT_PARAM_MAGIC_RES_INIT1 0x30 +#define ENET_INIT_PARAM_MAGIC_RES_INIT2 0xff +#define ENET_INIT_PARAM_MAGIC_RES_INIT3 0x00 +#define ENET_INIT_PARAM_MAGIC_RES_INIT4 0x0400 + +/* structure representing 82xx Address Filtering Enet Address in PRAM +*/ +typedef struct uec_82xx_enet_address { + u8 res1[0x2]; + u16 h; /* address (MSB) */ + u16 m; /* address */ + u16 l; /* address (LSB) */ +} __attribute__ ((packed)) uec_82xx_enet_address_t; + +/* structure representing 82xx Address Filtering PRAM +*/ +typedef struct uec_82xx_address_filtering_pram { + u32 iaddr_h; /* individual address filter, high */ + u32 iaddr_l; /* individual address filter, low */ + u32 gaddr_h; /* group address filter, high */ + u32 gaddr_l; /* group address filter, low */ + uec_82xx_enet_address_t taddr; + uec_82xx_enet_address_t paddr[4]; + u8 res0[0x40-0x38]; +} __attribute__ ((packed)) uec_82xx_address_filtering_pram_t; + +/* Buffer Descriptor +*/ +typedef struct buffer_descriptor { + u16 status; + u16 len; + u32 data; +} __attribute__ ((packed)) qe_bd_t, *p_bd_t; + +#define SIZEOFBD sizeof(qe_bd_t) + +/* Common BD flags +*/ +#define BD_WRAP 0x2000 +#define BD_INT 0x1000 +#define BD_LAST 0x0800 +#define BD_CLEAN 0x3000 + +/* TxBD status flags +*/ +#define TxBD_READY 0x8000 +#define TxBD_PADCRC 0x4000 +#define TxBD_WRAP BD_WRAP +#define TxBD_INT BD_INT +#define TxBD_LAST BD_LAST +#define TxBD_TXCRC 0x0400 +#define TxBD_DEF 0x0200 +#define TxBD_PP 0x0100 +#define TxBD_LC 0x0080 +#define TxBD_RL 0x0040 +#define TxBD_RC 0x003C +#define TxBD_UNDERRUN 0x0002 +#define TxBD_TRUNC 0x0001 + +#define TxBD_ERROR (TxBD_UNDERRUN | TxBD_TRUNC) + +/* RxBD status flags +*/ +#define RxBD_EMPTY 0x8000 +#define RxBD_OWNER 0x4000 +#define RxBD_WRAP BD_WRAP +#define RxBD_INT BD_INT +#define RxBD_LAST BD_LAST +#define RxBD_FIRST 0x0400 +#define RxBD_CMR 0x0200 +#define RxBD_MISS 0x0100 +#define RxBD_BCAST 0x0080 +#define RxBD_MCAST 0x0040 +#define RxBD_LG 0x0020 +#define RxBD_NO 0x0010 +#define RxBD_SHORT 0x0008 +#define RxBD_CRCERR 0x0004 +#define RxBD_OVERRUN 0x0002 +#define RxBD_IPCH 0x0001 + +#define RxBD_ERROR (RxBD_LG | RxBD_NO | RxBD_SHORT | \ + RxBD_CRCERR | RxBD_OVERRUN) + +/* BD access macros +*/ +#define BD_STATUS(_bd) (((p_bd_t)(_bd))->status) +#define BD_STATUS_SET(_bd, _val) (((p_bd_t)(_bd))->status = _val) +#define BD_LENGTH(_bd) (((p_bd_t)(_bd))->len) +#define BD_LENGTH_SET(_bd, _val) (((p_bd_t)(_bd))->len = _val) +#define BD_DATA_CLEAR(_bd) (((p_bd_t)(_bd))->data = 0) +#define BD_IS_DATA(_bd) (((p_bd_t)(_bd))->data) +#define BD_DATA(_bd) ((u8 *)(((p_bd_t)(_bd))->data)) +#define BD_DATA_SET(_bd, _data) (((p_bd_t)(_bd))->data = (u32)(_data)) +#define BD_ADVANCE(_bd,_status,_base) \ + (((_status) & BD_WRAP) ? (_bd) = ((p_bd_t)(_base)) : ++(_bd)) + +/* Rx Prefetched BDs +*/ +typedef struct uec_rx_prefetched_bds { + qe_bd_t bd[MAX_PREFETCHED_BDS]; /* prefetched bd */ +} __attribute__ ((packed)) uec_rx_prefetched_bds_t; + +/* Alignments + */ +#define UEC_RX_GLOBAL_PRAM_ALIGNMENT 64 +#define UEC_TX_GLOBAL_PRAM_ALIGNMENT 64 +#define UEC_THREAD_RX_PRAM_ALIGNMENT 128 +#define UEC_THREAD_TX_PRAM_ALIGNMENT 64 +#define UEC_THREAD_DATA_ALIGNMENT 256 +#define UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT 32 +#define UEC_SCHEDULER_ALIGNMENT 4 +#define UEC_TX_STATISTICS_ALIGNMENT 4 +#define UEC_RX_STATISTICS_ALIGNMENT 4 +#define UEC_RX_INTERRUPT_COALESCING_ALIGNMENT 4 +#define UEC_RX_BD_QUEUES_ALIGNMENT 8 +#define UEC_RX_PREFETCHED_BDS_ALIGNMENT 128 +#define UEC_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 4 +#define UEC_RX_BD_RING_ALIGNMENT 32 +#define UEC_TX_BD_RING_ALIGNMENT 32 +#define UEC_MRBLR_ALIGNMENT 128 +#define UEC_RX_BD_RING_SIZE_ALIGNMENT 4 +#define UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT 32 +#define UEC_RX_DATA_BUF_ALIGNMENT 64 + +#define UEC_VLAN_PRIORITY_MAX 8 +#define UEC_IP_PRIORITY_MAX 64 +#define UEC_TX_VTAG_TABLE_ENTRY_MAX 8 +#define UEC_RX_BD_RING_SIZE_MIN 8 +#define UEC_TX_BD_RING_SIZE_MIN 2 + +/* Ethernet speed +*/ +typedef enum enet_speed { + ENET_SPEED_10BT, /* 10 Base T */ + ENET_SPEED_100BT, /* 100 Base T */ + ENET_SPEED_1000BT /* 1000 Base T */ +} enet_speed_e; + +/* Ethernet Address Type. +*/ +typedef enum enet_addr_type { + ENET_ADDR_TYPE_INDIVIDUAL, + ENET_ADDR_TYPE_GROUP, + ENET_ADDR_TYPE_BROADCAST +} enet_addr_type_e; + +/* TBI / MII Set Register +*/ +typedef enum enet_tbi_mii_reg { + ENET_TBI_MII_CR = 0x00, + ENET_TBI_MII_SR = 0x01, + ENET_TBI_MII_ANA = 0x04, + ENET_TBI_MII_ANLPBPA = 0x05, + ENET_TBI_MII_ANEX = 0x06, + ENET_TBI_MII_ANNPT = 0x07, + ENET_TBI_MII_ANLPANP = 0x08, + ENET_TBI_MII_EXST = 0x0F, + ENET_TBI_MII_JD = 0x10, + ENET_TBI_MII_TBICON = 0x11 +} enet_tbi_mii_reg_e; + +/* UEC number of threads +*/ +typedef enum uec_num_of_threads { + UEC_NUM_OF_THREADS_1 = 0x1, /* 1 */ + UEC_NUM_OF_THREADS_2 = 0x2, /* 2 */ + UEC_NUM_OF_THREADS_4 = 0x0, /* 4 */ + UEC_NUM_OF_THREADS_6 = 0x3, /* 6 */ + UEC_NUM_OF_THREADS_8 = 0x4 /* 8 */ +} uec_num_of_threads_e; + +/* UEC ethernet interface type +*/ +typedef enum enet_interface { + ENET_10_MII, + ENET_10_RMII, + ENET_10_RGMII, + ENET_100_MII, + ENET_100_RMII, + ENET_100_RGMII, + ENET_1000_GMII, + ENET_1000_RGMII, + ENET_1000_TBI, + ENET_1000_RTBI +} enet_interface_e; + +/* UEC initialization info struct +*/ +typedef struct uec_info { + ucc_fast_info_t uf_info; + uec_num_of_threads_e num_threads_tx; + uec_num_of_threads_e num_threads_rx; + qe_risc_allocation_e riscTx; + qe_risc_allocation_e riscRx; + u16 rx_bd_ring_len; + u16 tx_bd_ring_len; + u8 phy_address; + enet_interface_e enet_interface; +} uec_info_t; + +/* UEC driver initialized info +*/ +#define MAX_RXBUF_LEN 1536 +#define MAX_FRAME_LEN 1518 +#define MIN_FRAME_LEN 64 +#define MAX_DMA1_LEN 1520 +#define MAX_DMA2_LEN 1520 + +/* UEC driver private struct +*/ +typedef struct uec_private { + uec_info_t *uec_info; + ucc_fast_private_t *uccf; + struct eth_device *dev; + uec_t *uec_regs; + /* enet init command parameter */ + uec_init_cmd_pram_t *p_init_enet_param; + u32 init_enet_param_offset; + /* Rx and Tx paramter */ + uec_rx_global_pram_t *p_rx_glbl_pram; + u32 rx_glbl_pram_offset; + uec_tx_global_pram_t *p_tx_glbl_pram; + u32 tx_glbl_pram_offset; + uec_send_queue_mem_region_t *p_send_q_mem_reg; + u32 send_q_mem_reg_offset; + uec_thread_data_tx_t *p_thread_data_tx; + u32 thread_dat_tx_offset; + uec_thread_data_rx_t *p_thread_data_rx; + u32 thread_dat_rx_offset; + uec_rx_bd_queues_entry_t *p_rx_bd_qs_tbl; + u32 rx_bd_qs_tbl_offset; + /* BDs specific */ + u8 *p_tx_bd_ring; + u32 tx_bd_ring_offset; + u8 *p_rx_bd_ring; + u32 rx_bd_ring_offset; + u8 *p_rx_buf; + u32 rx_buf_offset; + volatile qe_bd_t *txBd; + volatile qe_bd_t *rxBd; + /* Status */ + int mac_tx_enabled; + int mac_rx_enabled; + int grace_stopped_tx; + int grace_stopped_rx; + int the_first_run; + /* PHY specific */ + struct uec_mii_info *mii_info; + int oldspeed; + int oldduplex; + int oldlink; +} uec_private_t; + +#endif /* __UEC_H__ */ diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c new file mode 100644 index 0000000000..fedf6361cb --- /dev/null +++ b/drivers/qe/uec_phy.c @@ -0,0 +1,604 @@ +/* + * Copyright (C) 2005 Freescale Semiconductor, Inc. + * + * Author: Shlomi Gridish + * + * Description: UCC GETH Driver -- PHY handling + * Driver for UEC on QE + * Based on 8260_io/fcc_enet.c + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include "common.h" +#include "net.h" +#include "malloc.h" +#include "asm/errno.h" +#include "asm/immap_qe.h" +#include "asm/io.h" +#include "qe.h" +#include "uccf.h" +#include "uec.h" +#include "uec_phy.h" +#include "miiphy.h" + +#if defined(CONFIG_QE) + +#define UEC_VERBOSE_DEBUG +#define ugphy_printk(format, arg...) \ + printf(format "\n", ## arg) + +#define ugphy_dbg(format, arg...) \ + ugphy_printk(format , ## arg) +#define ugphy_err(format, arg...) \ + ugphy_printk(format , ## arg) +#define ugphy_info(format, arg...) \ + ugphy_printk(format , ## arg) +#define ugphy_warn(format, arg...) \ + ugphy_printk(format , ## arg) + +#ifdef UEC_VERBOSE_DEBUG +#define ugphy_vdbg ugphy_dbg +#else +#define ugphy_vdbg(ugeth, fmt, args...) do { } while (0) +#endif /* UEC_VERBOSE_DEBUG */ + +static void config_genmii_advert(struct uec_mii_info *mii_info); +static void genmii_setup_forced(struct uec_mii_info *mii_info); +static void genmii_restart_aneg(struct uec_mii_info *mii_info); +static int gbit_config_aneg(struct uec_mii_info *mii_info); +static int genmii_config_aneg(struct uec_mii_info *mii_info); +static int genmii_update_link(struct uec_mii_info *mii_info); +static int genmii_read_status(struct uec_mii_info *mii_info); +u16 phy_read(struct uec_mii_info *mii_info, u16 regnum); +void phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val); + +/* Write value to the PHY for this device to the register at regnum, */ +/* waiting until the write is done before it returns. All PHY */ +/* configuration has to be done through the TSEC1 MIIM regs */ +void write_phy_reg(struct eth_device *dev, int mii_id, int regnum, int value) +{ + uec_private_t *ugeth = (uec_private_t *)dev->priv; + uec_t *ug_regs; + enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e)regnum; + u32 tmp_reg; + + ug_regs = ugeth->uec_regs; + + /* Stop the MII management read cycle */ + out_be32(&ug_regs->miimcom, 0); + /* Setting up the MII Mangement Address Register */ + tmp_reg = ((u32)mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg; + out_be32(&ug_regs->miimadd, tmp_reg); + + /* Setting up the MII Mangement Control Register with the value */ + out_be32(&ug_regs->miimcon, (u32)value); + + /* Wait till MII management write is complete */ + while((in_be32(&ug_regs->miimind)) & MIIMIND_BUSY); + + udelay(100000); +} + +/* Reads from register regnum in the PHY for device dev, */ +/* returning the value. Clears miimcom first. All PHY */ +/* configuration has to be done through the TSEC1 MIIM regs */ +int read_phy_reg(struct eth_device *dev, int mii_id, int regnum) +{ + uec_private_t *ugeth = (uec_private_t *)dev->priv; + uec_t *ug_regs; + enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e)regnum; + u32 tmp_reg; + u16 value; + + ug_regs = ugeth->uec_regs; + + /* Setting up the MII Mangement Address Register */ + tmp_reg = ((u32)mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg ; + out_be32(&ug_regs->miimadd, tmp_reg); + + /* Perform an MII management read cycle */ + out_be32(&ug_regs->miimcom, 0); + out_be32(&ug_regs->miimcom, MIIMCOM_READ_CYCLE); + + /* Wait till MII management write is complete */ + while((in_be32(&ug_regs->miimind)) & (MIIMIND_NOT_VALID | MIIMIND_BUSY)); + + udelay(100000); + + /* Read MII management status */ + value = (u16)in_be32(&ug_regs->miimstat); + if(value == 0xffff) + ugphy_warn("read wrong value : mii_id %d,mii_reg %d, base %08x", + mii_id, mii_reg, (u32) &(ug_regs->miimcfg)); + + return (value); +} + +void mii_clear_phy_interrupt(struct uec_mii_info *mii_info) +{ + if(mii_info->phyinfo->ack_interrupt) + mii_info->phyinfo->ack_interrupt(mii_info); +} + +void mii_configure_phy_interrupt(struct uec_mii_info *mii_info, u32 interrupts) +{ + mii_info->interrupts = interrupts; + if(mii_info->phyinfo->config_intr) + mii_info->phyinfo->config_intr(mii_info); +} + +/* Writes MII_ADVERTISE with the appropriate values, after + * sanitizing advertise to make sure only supported features + * are advertised + */ +static void config_genmii_advert(struct uec_mii_info *mii_info) +{ + u32 advertise; + u16 adv; + + /* Only allow advertising what this PHY supports */ + mii_info->advertising &= mii_info->phyinfo->features; + advertise = mii_info->advertising; + + /* Setup standard advertisement */ + adv = phy_read(mii_info, PHY_ANAR); + adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4); + if (advertise & ADVERTISED_10baseT_Half) + adv |= ADVERTISE_10HALF; + if (advertise & ADVERTISED_10baseT_Full) + adv |= ADVERTISE_10FULL; + if (advertise & ADVERTISED_100baseT_Half) + adv |= ADVERTISE_100HALF; + if (advertise & ADVERTISED_100baseT_Full) + adv |= ADVERTISE_100FULL; + phy_write(mii_info, PHY_ANAR, adv); +} + +static void genmii_setup_forced(struct uec_mii_info *mii_info) +{ + u16 ctrl; + u32 features = mii_info->phyinfo->features; + + ctrl = phy_read(mii_info, PHY_BMCR); + + ctrl &= ~(PHY_BMCR_DPLX|PHY_BMCR_100_MBPS| + PHY_BMCR_1000_MBPS|PHY_BMCR_AUTON); + ctrl |= PHY_BMCR_RESET; + + switch(mii_info->speed) { + case SPEED_1000: + if(features & (SUPPORTED_1000baseT_Half + | SUPPORTED_1000baseT_Full)) { + ctrl |= PHY_BMCR_1000_MBPS; + break; + } + mii_info->speed = SPEED_100; + case SPEED_100: + if (features & (SUPPORTED_100baseT_Half + | SUPPORTED_100baseT_Full)) { + ctrl |= PHY_BMCR_100_MBPS; + break; + } + mii_info->speed = SPEED_10; + case SPEED_10: + if (features & (SUPPORTED_10baseT_Half + | SUPPORTED_10baseT_Full)) + break; + default: /* Unsupported speed! */ + ugphy_err("%s: Bad speed!", mii_info->dev->name); + break; + } + + phy_write(mii_info, PHY_BMCR, ctrl); +} + +/* Enable and Restart Autonegotiation */ +static void genmii_restart_aneg(struct uec_mii_info *mii_info) +{ + u16 ctl; + + ctl = phy_read(mii_info, PHY_BMCR); + ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + phy_write(mii_info, PHY_BMCR, ctl); +} + +static int gbit_config_aneg(struct uec_mii_info *mii_info) +{ + u16 adv; + u32 advertise; + + if(mii_info->autoneg) { + /* Configure the ADVERTISE register */ + config_genmii_advert(mii_info); + advertise = mii_info->advertising; + + adv = phy_read(mii_info, MII_1000BASETCONTROL); + adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP | + MII_1000BASETCONTROL_HALFDUPLEXCAP); + if (advertise & SUPPORTED_1000baseT_Half) + adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP; + if (advertise & SUPPORTED_1000baseT_Full) + adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP; + phy_write(mii_info, MII_1000BASETCONTROL, adv); + + /* Start/Restart aneg */ + genmii_restart_aneg(mii_info); + } else + genmii_setup_forced(mii_info); + + return 0; +} + +static int marvell_config_aneg(struct uec_mii_info *mii_info) +{ + /* The Marvell PHY has an errata which requires + * that certain registers get written in order + * to restart autonegotiation */ + phy_write(mii_info, PHY_BMCR, PHY_BMCR_RESET); + + phy_write(mii_info, 0x1d, 0x1f); + phy_write(mii_info, 0x1e, 0x200c); + phy_write(mii_info, 0x1d, 0x5); + phy_write(mii_info, 0x1e, 0); + phy_write(mii_info, 0x1e, 0x100); + + gbit_config_aneg(mii_info); + + return 0; +} + +static int genmii_config_aneg(struct uec_mii_info *mii_info) +{ + if (mii_info->autoneg) { + config_genmii_advert(mii_info); + genmii_restart_aneg(mii_info); + } else + genmii_setup_forced(mii_info); + + return 0; +} + +static int genmii_update_link(struct uec_mii_info *mii_info) +{ + u16 status; + + /* Do a fake read */ + phy_read(mii_info, PHY_BMSR); + + /* Read link and autonegotiation status */ + status = phy_read(mii_info, PHY_BMSR); + if ((status & PHY_BMSR_LS) == 0) + mii_info->link = 0; + else + mii_info->link = 1; + + /* If we are autonegotiating, and not done, + * return an error */ + if (mii_info->autoneg && !(status & PHY_BMSR_AUTN_COMP)) + return -EAGAIN; + + return 0; +} + +static int genmii_read_status(struct uec_mii_info *mii_info) +{ + u16 status; + int err; + + /* Update the link, but return if there + * was an error */ + err = genmii_update_link(mii_info); + if (err) + return err; + + if (mii_info->autoneg) { + status = phy_read(mii_info, PHY_ANLPAR); + + if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) + mii_info->duplex = DUPLEX_FULL; + else + mii_info->duplex = DUPLEX_HALF; + if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) + mii_info->speed = SPEED_100; + else + mii_info->speed = SPEED_10; + mii_info->pause = 0; + } + /* On non-aneg, we assume what we put in BMCR is the speed, + * though magic-aneg shouldn't prevent this case from occurring + */ + + return 0; +} + +static int marvell_read_status(struct uec_mii_info *mii_info) +{ + u16 status; + int err; + + /* Update the link, but return if there + * was an error */ + err = genmii_update_link(mii_info); + if (err) + return err; + + /* If the link is up, read the speed and duplex */ + /* If we aren't autonegotiating, assume speeds + * are as set */ + if (mii_info->autoneg && mii_info->link) { + int speed; + status = phy_read(mii_info, MII_M1011_PHY_SPEC_STATUS); + + /* Get the duplexity */ + if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX) + mii_info->duplex = DUPLEX_FULL; + else + mii_info->duplex = DUPLEX_HALF; + + /* Get the speed */ + speed = status & MII_M1011_PHY_SPEC_STATUS_SPD_MASK; + switch(speed) { + case MII_M1011_PHY_SPEC_STATUS_1000: + mii_info->speed = SPEED_1000; + break; + case MII_M1011_PHY_SPEC_STATUS_100: + mii_info->speed = SPEED_100; + break; + default: + mii_info->speed = SPEED_10; + break; + } + mii_info->pause = 0; + } + + return 0; +} + +static int marvell_ack_interrupt(struct uec_mii_info *mii_info) +{ + /* Clear the interrupts by reading the reg */ + phy_read(mii_info, MII_M1011_IEVENT); + + return 0; +} + +static int marvell_config_intr(struct uec_mii_info *mii_info) +{ + if(mii_info->interrupts == MII_INTERRUPT_ENABLED) + phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT); + else + phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR); + + return 0; +} + +static int dm9161_init(struct uec_mii_info *mii_info) +{ + /* Reset the PHY */ + phy_write(mii_info, PHY_BMCR, phy_read(mii_info, PHY_BMCR) | + PHY_BMCR_RESET); + /* PHY and MAC connect*/ + phy_write(mii_info, PHY_BMCR, phy_read(mii_info, PHY_BMCR) & + ~PHY_BMCR_ISO); +#ifdef CONFIG_RMII_MODE + phy_write(mii_info, MII_DM9161_SCR, MII_DM9161_SCR_RMII_INIT); +#else + phy_write(mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT); +#endif + config_genmii_advert(mii_info); + /* Start/restart aneg */ + genmii_config_aneg(mii_info); + /* Delay to wait the aneg compeleted */ + udelay(3000000); + + return 0; +} + +static int dm9161_config_aneg(struct uec_mii_info *mii_info) +{ + return 0; +} + +static int dm9161_read_status(struct uec_mii_info *mii_info) +{ + u16 status; + int err; + + /* Update the link, but return if there was an error*/ + err = genmii_update_link(mii_info); + if (err) + return err; + /* If the link is up, read the speed and duplex + If we aren't autonegotiating assume speeds are as set */ + if (mii_info->autoneg && mii_info->link) { + status = phy_read(mii_info, MII_DM9161_SCSR); + if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H)) + mii_info->speed = SPEED_100; + else + mii_info->speed = SPEED_10; + + if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_10F)) + mii_info->duplex = DUPLEX_FULL; + else + mii_info->duplex = DUPLEX_HALF; + } + + return 0; +} + +static int dm9161_ack_interrupt(struct uec_mii_info *mii_info) +{ + /* Clear the interrupt by reading the reg */ + phy_read(mii_info, MII_DM9161_INTR); + + return 0; +} + +static int dm9161_config_intr(struct uec_mii_info *mii_info) +{ + if (mii_info->interrupts == MII_INTERRUPT_ENABLED) + phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT); + else + phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP); + + return 0; +} + +static void dm9161_close(struct uec_mii_info *mii_info) +{ +} + +static struct phy_info phy_info_dm9161 = { + .phy_id = 0x0181b880, + .phy_id_mask = 0x0ffffff0, + .name = "Davicom DM9161E", + .init = dm9161_init, + .config_aneg = dm9161_config_aneg, + .read_status = dm9161_read_status, + .close = dm9161_close, +}; + +static struct phy_info phy_info_dm9161a = { + .phy_id = 0x0181b8a0, + .phy_id_mask = 0x0ffffff0, + .name = "Davicom DM9161A", + .features = MII_BASIC_FEATURES, + .init = dm9161_init, + .config_aneg = dm9161_config_aneg, + .read_status = dm9161_read_status, + .ack_interrupt = dm9161_ack_interrupt, + .config_intr = dm9161_config_intr, + .close = dm9161_close, +}; + +static struct phy_info phy_info_marvell = { + .phy_id = 0x01410c00, + .phy_id_mask = 0xffffff00, + .name = "Marvell 88E11x1", + .features = MII_GBIT_FEATURES, + .config_aneg = &marvell_config_aneg, + .read_status = &marvell_read_status, + .ack_interrupt = &marvell_ack_interrupt, + .config_intr = &marvell_config_intr, +}; + +static struct phy_info phy_info_genmii= { + .phy_id = 0x00000000, + .phy_id_mask = 0x00000000, + .name = "Generic MII", + .features = MII_BASIC_FEATURES, + .config_aneg = genmii_config_aneg, + .read_status = genmii_read_status, +}; + +static struct phy_info *phy_info[] = { + &phy_info_dm9161, + &phy_info_dm9161a, + &phy_info_marvell, + &phy_info_genmii, + NULL +}; + +u16 phy_read(struct uec_mii_info *mii_info, u16 regnum) +{ + return mii_info->mdio_read(mii_info->dev, mii_info->mii_id, regnum); +} + +void phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val) +{ + mii_info->mdio_write(mii_info->dev, + mii_info->mii_id, + regnum, val); +} + +/* Use the PHY ID registers to determine what type of PHY is attached + * to device dev. return a struct phy_info structure describing that PHY + */ +struct phy_info * get_phy_info(struct uec_mii_info *mii_info) +{ + u16 phy_reg; + u32 phy_ID; + int i; + struct phy_info *theInfo = NULL; + + /* Grab the bits from PHYIR1, and put them in the upper half */ + phy_reg = phy_read(mii_info, PHY_PHYIDR1); + phy_ID = (phy_reg & 0xffff) << 16; + + /* Grab the bits from PHYIR2, and put them in the lower half */ + phy_reg = phy_read(mii_info, PHY_PHYIDR2); + phy_ID |= (phy_reg & 0xffff); + + /* loop through all the known PHY types, and find one that */ + /* matches the ID we read from the PHY. */ + for (i = 0; phy_info[i]; i++) + if (phy_info[i]->phy_id == + (phy_ID & phy_info[i]->phy_id_mask)) { + theInfo = phy_info[i]; + break; + } + + /* This shouldn't happen, as we have generic PHY support */ + if (theInfo == NULL) { + ugphy_info("UEC: PHY id %x is not supported!", phy_ID); + return NULL; + } else { + ugphy_info("UEC: PHY is %s (%x)", theInfo->name, phy_ID); + } + + return theInfo; +} + +void marvell_phy_interface_mode(struct eth_device *dev, enet_interface_e mode) +{ + uec_private_t *uec = (uec_private_t *)dev->priv; + struct uec_mii_info *mii_info; + + if (!uec->mii_info) { + printf("%s: the PHY not intialized\n", __FUNCTION__); + return; + } + mii_info = uec->mii_info; + + if (mode == ENET_100_RGMII) { + phy_write(mii_info, 0x00, 0x9140); + phy_write(mii_info, 0x1d, 0x001f); + phy_write(mii_info, 0x1e, 0x200c); + phy_write(mii_info, 0x1d, 0x0005); + phy_write(mii_info, 0x1e, 0x0000); + phy_write(mii_info, 0x1e, 0x0100); + phy_write(mii_info, 0x09, 0x0e00); + phy_write(mii_info, 0x04, 0x01e1); + phy_write(mii_info, 0x00, 0x9140); + phy_write(mii_info, 0x00, 0x1000); + udelay(100000); + phy_write(mii_info, 0x00, 0x2900); + phy_write(mii_info, 0x14, 0x0cd2); + phy_write(mii_info, 0x00, 0xa100); + phy_write(mii_info, 0x09, 0x0000); + phy_write(mii_info, 0x1b, 0x800b); + phy_write(mii_info, 0x04, 0x05e1); + phy_write(mii_info, 0x00, 0xa100); + phy_write(mii_info, 0x00, 0x2100); + udelay(1000000); + } else if (mode == ENET_10_RGMII) { + phy_write(mii_info, 0x14, 0x8e40); + phy_write(mii_info, 0x1b, 0x800b); + phy_write(mii_info, 0x14, 0x0c82); + phy_write(mii_info, 0x00, 0x8100); + udelay(1000000); + } +} + +void change_phy_interface_mode(struct eth_device *dev, enet_interface_e mode) +{ +#ifdef CONFIG_PHY_MODE_NEED_CHANGE + marvell_phy_interface_mode(dev, mode); +#endif +} +#endif /* CONFIG_QE */ diff --git a/drivers/qe/uec_phy.h b/drivers/qe/uec_phy.h new file mode 100644 index 0000000000..a82f1f5893 --- /dev/null +++ b/drivers/qe/uec_phy.h @@ -0,0 +1,256 @@ +/* + * Copyright (C) 2005 Freescale Semiconductor, Inc. + * + * Author: Shlomi Gridish + * + * Description: UCC ethernet driver -- PHY handling + * Driver for UEC on QE + * Based on 8260_io/fcc_enet.c + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ +#ifndef __UEC_PHY_H__ +#define __UEC_PHY_H__ + +#define MII_end ((u32)-2) +#define MII_read ((u32)-1) + +#define MIIMIND_BUSY 0x00000001 +#define MIIMIND_NOTVALID 0x00000004 + +#define UGETH_AN_TIMEOUT 2000 + +/* 1000BT control (Marvell & BCM54xx at least) */ +#define MII_1000BASETCONTROL 0x09 +#define MII_1000BASETCONTROL_FULLDUPLEXCAP 0x0200 +#define MII_1000BASETCONTROL_HALFDUPLEXCAP 0x0100 + +/* Cicada Extended Control Register 1 */ +#define MII_CIS8201_EXT_CON1 0x17 +#define MII_CIS8201_EXTCON1_INIT 0x0000 + +/* Cicada Interrupt Mask Register */ +#define MII_CIS8201_IMASK 0x19 +#define MII_CIS8201_IMASK_IEN 0x8000 +#define MII_CIS8201_IMASK_SPEED 0x4000 +#define MII_CIS8201_IMASK_LINK 0x2000 +#define MII_CIS8201_IMASK_DUPLEX 0x1000 +#define MII_CIS8201_IMASK_MASK 0xf000 + +/* Cicada Interrupt Status Register */ +#define MII_CIS8201_ISTAT 0x1a +#define MII_CIS8201_ISTAT_STATUS 0x8000 +#define MII_CIS8201_ISTAT_SPEED 0x4000 +#define MII_CIS8201_ISTAT_LINK 0x2000 +#define MII_CIS8201_ISTAT_DUPLEX 0x1000 + +/* Cicada Auxiliary Control/Status Register */ +#define MII_CIS8201_AUX_CONSTAT 0x1c +#define MII_CIS8201_AUXCONSTAT_INIT 0x0004 +#define MII_CIS8201_AUXCONSTAT_DUPLEX 0x0020 +#define MII_CIS8201_AUXCONSTAT_SPEED 0x0018 +#define MII_CIS8201_AUXCONSTAT_GBIT 0x0010 +#define MII_CIS8201_AUXCONSTAT_100 0x0008 + +/* 88E1011 PHY Status Register */ +#define MII_M1011_PHY_SPEC_STATUS 0x11 +#define MII_M1011_PHY_SPEC_STATUS_1000 0x8000 +#define MII_M1011_PHY_SPEC_STATUS_100 0x4000 +#define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000 +#define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000 +#define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800 +#define MII_M1011_PHY_SPEC_STATUS_LINK 0x0400 + +#define MII_M1011_IEVENT 0x13 +#define MII_M1011_IEVENT_CLEAR 0x0000 + +#define MII_M1011_IMASK 0x12 +#define MII_M1011_IMASK_INIT 0x6400 +#define MII_M1011_IMASK_CLEAR 0x0000 + +#define MII_DM9161_SCR 0x10 +#define MII_DM9161_SCR_INIT 0x0610 +#define MII_DM9161_SCR_RMII_INIT 0x0710 + +/* DM9161 Specified Configuration and Status Register */ +#define MII_DM9161_SCSR 0x11 +#define MII_DM9161_SCSR_100F 0x8000 +#define MII_DM9161_SCSR_100H 0x4000 +#define MII_DM9161_SCSR_10F 0x2000 +#define MII_DM9161_SCSR_10H 0x1000 + +/* DM9161 Interrupt Register */ +#define MII_DM9161_INTR 0x15 +#define MII_DM9161_INTR_PEND 0x8000 +#define MII_DM9161_INTR_DPLX_MASK 0x0800 +#define MII_DM9161_INTR_SPD_MASK 0x0400 +#define MII_DM9161_INTR_LINK_MASK 0x0200 +#define MII_DM9161_INTR_MASK 0x0100 +#define MII_DM9161_INTR_DPLX_CHANGE 0x0010 +#define MII_DM9161_INTR_SPD_CHANGE 0x0008 +#define MII_DM9161_INTR_LINK_CHANGE 0x0004 +#define MII_DM9161_INTR_INIT 0x0000 +#define MII_DM9161_INTR_STOP \ +(MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK \ + | MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK) + +/* DM9161 10BT Configuration/Status */ +#define MII_DM9161_10BTCSR 0x12 +#define MII_DM9161_10BTCSR_INIT 0x7800 + +#define MII_BASIC_FEATURES (SUPPORTED_10baseT_Half | \ + SUPPORTED_10baseT_Full | \ + SUPPORTED_100baseT_Half | \ + SUPPORTED_100baseT_Full | \ + SUPPORTED_Autoneg | \ + SUPPORTED_TP | \ + SUPPORTED_MII) + +#define MII_GBIT_FEATURES (MII_BASIC_FEATURES | \ + SUPPORTED_1000baseT_Half | \ + SUPPORTED_1000baseT_Full) + +#define MII_READ_COMMAND 0x00000001 + +#define MII_INTERRUPT_DISABLED 0x0 +#define MII_INTERRUPT_ENABLED 0x1 + +#define SPEED_10 10 +#define SPEED_100 100 +#define SPEED_1000 1000 + +/* Duplex, half or full. */ +#define DUPLEX_HALF 0x00 +#define DUPLEX_FULL 0x01 + +/* Indicates what features are supported by the interface. */ +#define SUPPORTED_10baseT_Half (1 << 0) +#define SUPPORTED_10baseT_Full (1 << 1) +#define SUPPORTED_100baseT_Half (1 << 2) +#define SUPPORTED_100baseT_Full (1 << 3) +#define SUPPORTED_1000baseT_Half (1 << 4) +#define SUPPORTED_1000baseT_Full (1 << 5) +#define SUPPORTED_Autoneg (1 << 6) +#define SUPPORTED_TP (1 << 7) +#define SUPPORTED_AUI (1 << 8) +#define SUPPORTED_MII (1 << 9) +#define SUPPORTED_FIBRE (1 << 10) +#define SUPPORTED_BNC (1 << 11) +#define SUPPORTED_10000baseT_Full (1 << 12) + +#define ADVERTISED_10baseT_Half (1 << 0) +#define ADVERTISED_10baseT_Full (1 << 1) +#define ADVERTISED_100baseT_Half (1 << 2) +#define ADVERTISED_100baseT_Full (1 << 3) +#define ADVERTISED_1000baseT_Half (1 << 4) +#define ADVERTISED_1000baseT_Full (1 << 5) +#define ADVERTISED_Autoneg (1 << 6) +#define ADVERTISED_TP (1 << 7) +#define ADVERTISED_AUI (1 << 8) +#define ADVERTISED_MII (1 << 9) +#define ADVERTISED_FIBRE (1 << 10) +#define ADVERTISED_BNC (1 << 11) +#define ADVERTISED_10000baseT_Full (1 << 12) + +/* Advertisement control register. */ +#define ADVERTISE_SLCT 0x001f /* Selector bits */ +#define ADVERTISE_CSMA 0x0001 /* Only selector supported */ +#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ +#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ +#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ +#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ +#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ +#define ADVERTISE_RESV 0x1c00 /* Unused... */ +#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ +#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ +#define ADVERTISE_NPAGE 0x8000 /* Next page bit */ + +#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ + ADVERTISE_CSMA) +#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ + ADVERTISE_100HALF | ADVERTISE_100FULL) + +/* Taken from mii_if_info and sungem_phy.h */ +struct uec_mii_info { + /* Information about the PHY type */ + /* And management functions */ + struct phy_info *phyinfo; + + struct eth_device *dev; + + /* forced speed & duplex (no autoneg) + * partner speed & duplex & pause (autoneg) + */ + int speed; + int duplex; + int pause; + + /* The most recently read link state */ + int link; + + /* Enabled Interrupts */ + u32 interrupts; + + u32 advertising; + int autoneg; + int mii_id; + + /* private data pointer */ + /* For use by PHYs to maintain extra state */ + void *priv; + + /* Provided by ethernet driver */ + int (*mdio_read) (struct eth_device *dev, int mii_id, int reg); + void (*mdio_write) (struct eth_device *dev, int mii_id, int reg, int val); +}; + +/* struct phy_info: a structure which defines attributes for a PHY + * + * id will contain a number which represents the PHY. During + * startup, the driver will poll the PHY to find out what its + * UID--as defined by registers 2 and 3--is. The 32-bit result + * gotten from the PHY will be ANDed with phy_id_mask to + * discard any bits which may change based on revision numbers + * unimportant to functionality + * + * There are 6 commands which take a ugeth_mii_info structure. + * Each PHY must declare config_aneg, and read_status. + */ +struct phy_info { + u32 phy_id; + char *name; + unsigned int phy_id_mask; + u32 features; + + /* Called to initialize the PHY */ + int (*init)(struct uec_mii_info *mii_info); + + /* Called to suspend the PHY for power */ + int (*suspend)(struct uec_mii_info *mii_info); + + /* Reconfigures autonegotiation (or disables it) */ + int (*config_aneg)(struct uec_mii_info *mii_info); + + /* Determines the negotiated speed and duplex */ + int (*read_status)(struct uec_mii_info *mii_info); + + /* Clears any pending interrupts */ + int (*ack_interrupt)(struct uec_mii_info *mii_info); + + /* Enables or disables interrupts */ + int (*config_intr)(struct uec_mii_info *mii_info); + + /* Clears up any memory if needed */ + void (*close)(struct uec_mii_info *mii_info); +}; + +struct phy_info *get_phy_info(struct uec_mii_info *mii_info); +void write_phy_reg(struct eth_device *dev, int mii_id, int regnum, int value); +int read_phy_reg(struct eth_device *dev, int mii_id, int regnum); +void mii_clear_phy_interrupt(struct uec_mii_info *mii_info); +void mii_configure_phy_interrupt(struct uec_mii_info *mii_info, u32 interrupts); +#endif /* __UEC_PHY_H__ */ diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index 418315bef2..8bc61b63a8 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -69,6 +69,8 @@ typedef struct global_data { #if defined(CONFIG_QE) u32 qe_clk; u32 brg_clk; + uint mp_alloc_base; + uint mp_alloc_top; #endif /* CONFIG_QE */ #if defined (CONFIG_MPC8360) u32 ddr_sec_clk; diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 0ae60618ec..330c3073d2 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -363,6 +363,35 @@ #define CONFIG_NET_MULTI 1 #endif +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "Freescale GETH" +#define CONFIG_PHY_MODE_NEED_CHANGE + +#define CONFIG_UEC_ETH1 /* GETH1 */ + +#ifdef CONFIG_UEC_ETH1 +#define CFG_UEC1_UCC_NUM 0 /* UCC1 */ +#define CFG_UEC1_RX_CLK QE_CLK_NONE +#define CFG_UEC1_TX_CLK QE_CLK9 +#define CFG_UEC1_ETH_TYPE GIGA_ETH +#define CFG_UEC1_PHY_ADDR 0 +#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII +#endif + +#define CONFIG_UEC_ETH2 /* GETH2 */ + +#ifdef CONFIG_UEC_ETH2 +#define CFG_UEC2_UCC_NUM 1 /* UCC2 */ +#define CFG_UEC2_RX_CLK QE_CLK_NONE +#define CFG_UEC2_TX_CLK QE_CLK4 +#define CFG_UEC2_ETH_TYPE GIGA_ETH +#define CFG_UEC2_PHY_ADDR 1 +#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII +#endif + /* * Environment */ diff --git a/include/ioports.h b/include/ioports.h index d7e19e195b..91ca6fb48e 100644 --- a/include/ioports.h +++ b/include/ioports.h @@ -53,3 +53,14 @@ typedef struct { * like the table in the 8260UM (and in the hymod manuals). */ extern const iop_conf_t iop_conf_tab[4][32]; + +typedef struct { + unsigned char port; + unsigned char pin; + int dir; + int open_drain; + int assign; +} qe_iop_conf_t; + +#define QE_IOP_TAB_END (-1) + diff --git a/net/eth.c b/net/eth.c index e8ac251a4f..022d423d59 100644 --- a/net/eth.c +++ b/net/eth.c @@ -54,6 +54,7 @@ extern int scc_initialize(bd_t*); extern int skge_initialize(bd_t*); extern int tsec_initialize(bd_t*, int, char *); extern int npe_initialize(bd_t *); +extern int uec_initialize(int); static struct eth_device *eth_devices, *eth_current; @@ -196,6 +197,12 @@ int eth_initialize(bd_t *bis) tsec_initialize(bis, 3, CONFIG_MPC83XX_TSEC4_NAME); # endif #endif +#if defined(CONFIG_UEC_ETH1) + uec_initialize(0); +#endif +#if defined(CONFIG_UEC_ETH2) + uec_initialize(1); +#endif #if defined(CONFIG_MPC86XX_TSEC1) tsec_initialize(bis, 0, CONFIG_MPC86XX_TSEC1_NAME); #endif -- cgit v1.2.3 From d239d74b1c937984bc519083a8e7de373a390f06 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Fri, 3 Nov 2006 12:00:28 -0600 Subject: mpc83xx: Replace CFG_IMMRBAR with CFG_IMMR Replace all instances of CFG_IMMRBAR with CFG_IMMR, so that the 83xx tree matches the other 8xxx trees. Signed-off-by: Timur Tabi --- board/mpc8349emds/mpc8349emds.c | 10 +++++----- board/mpc8349emds/pci.c | 10 +++++----- board/mpc8349itx/mpc8349itx.c | 8 ++++---- board/mpc8349itx/pci.c | 6 +++--- board/mpc8360emds/mpc8360emds.c | 10 +++++----- board/mpc8360emds/pci.c | 8 ++++---- board/tqm834x/pci.c | 6 +++--- board/tqm834x/tqm834x.c | 4 ++-- cpu/mpc83xx/cpu.c | 14 +++++++------- cpu/mpc83xx/cpu_init.c | 2 +- cpu/mpc83xx/interrupts.c | 2 +- cpu/mpc83xx/qe_io.c | 2 +- cpu/mpc83xx/spd_sdram.c | 4 ++-- cpu/mpc83xx/speed.c | 2 +- cpu/mpc83xx/start.S | 16 ++++++++-------- drivers/tsec.h | 2 +- include/asm-ppc/i2c.h | 8 ++++---- include/configs/MPC8349EMDS.h | 14 +++++++------- include/configs/MPC8349ITX.h | 10 +++++----- include/configs/MPC8360EMDS.h | 10 +++++----- include/configs/TQM834x.h | 14 +++++++------- lib_ppc/board.c | 2 +- 22 files changed, 82 insertions(+), 82 deletions(-) (limited to 'drivers') diff --git a/board/mpc8349emds/mpc8349emds.c b/board/mpc8349emds/mpc8349emds.c index ed7b71d086..873bdd01cd 100644 --- a/board/mpc8349emds/mpc8349emds.c +++ b/board/mpc8349emds/mpc8349emds.c @@ -63,7 +63,7 @@ int board_early_init_f (void) long int initdram (int board_type) { - volatile immap_t *im = (immap_t *)CFG_IMMRBAR; + volatile immap_t *im = (immap_t *)CFG_IMMR; u32 msize = 0; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) @@ -100,7 +100,7 @@ long int initdram (int board_type) ************************************************************************/ int fixed_sdram(void) { - volatile immap_t *im = (immap_t *)CFG_IMMRBAR; + volatile immap_t *im = (immap_t *)CFG_IMMR; u32 msize = 0; u32 ddr_size; u32 ddr_size_log2; @@ -171,7 +171,7 @@ int checkboard (void) void sdram_init(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; + volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile lbus83xx_t *lbc= &immap->lbus; uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; @@ -249,7 +249,7 @@ void sdram_init(void) */ void ecc_print_status(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; + volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ddr83xx_t *ddr = &immap->ddr; printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF"); @@ -324,7 +324,7 @@ void ecc_print_status(void) int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; + volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ddr83xx_t *ddr = &immap->ddr; volatile u32 val; u64 *addr, count, val64; diff --git a/board/mpc8349emds/pci.c b/board/mpc8349emds/pci.c index 908be57546..da49a5d80d 100644 --- a/board/mpc8349emds/pci.c +++ b/board/mpc8349emds/pci.c @@ -146,7 +146,7 @@ pci_init_board(void) u32 dev; struct pci_controller * hose; - immr = (immap_t *)CFG_IMMRBAR; + immr = (immap_t *)CFG_IMMR; clk = (clk83xx_t *)&immr->clk; pci_law = immr->sysconf.pcilaw; pci_pot = immr->ios.pot; @@ -260,8 +260,8 @@ pci_init_board(void) hose->region_count = 4; pci_setup_indirect(hose, - (CFG_IMMRBAR+0x8300), - (CFG_IMMRBAR+0x8304)); + (CFG_IMMR+0x8300), + (CFG_IMMR+0x8304)); pci_register_hose(hose); @@ -356,8 +356,8 @@ pci_init_board(void) hose->region_count = 4; pci_setup_indirect(hose, - (CFG_IMMRBAR+0x8380), - (CFG_IMMRBAR+0x8384)); + (CFG_IMMR+0x8380), + (CFG_IMMR+0x8384)); pci_register_hose(hose); diff --git a/board/mpc8349itx/mpc8349itx.c b/board/mpc8349itx/mpc8349itx.c index 9fce973df0..c0e72c93e1 100644 --- a/board/mpc8349itx/mpc8349itx.c +++ b/board/mpc8349itx/mpc8349itx.c @@ -47,7 +47,7 @@ ************************************************************************/ int fixed_sdram(void) { - volatile immap_t *im = (immap_t *) CFG_IMMRBAR; + volatile immap_t *im = (immap_t *) CFG_IMMR; u32 ddr_size; /* The size of RAM, in bytes */ u32 ddr_size_log2 = 0; @@ -139,7 +139,7 @@ volatile static struct pci_controller hose[] = { void sdram_init(void) { - volatile immap_t *immap = (immap_t *) CFG_IMMRBAR; + volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile lbus83xx_t *lbc = &immap->lbus; #if defined(CFG_BR2_PRELIM) \ @@ -219,7 +219,7 @@ void sdram_init(void) long int initdram(int board_type) { - volatile immap_t *im = (immap_t *) CFG_IMMRBAR; + volatile immap_t *im = (immap_t *) CFG_IMMR; u32 msize = 0; #ifdef CONFIG_DDR_ECC volatile ddr83xx_t *ddr = &im->ddr; @@ -328,7 +328,7 @@ int misc_init_f(void) 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 }; - volatile immap_t *immap = (immap_t *) CFG_IMMRBAR; + volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile lbus83xx_t *lbus = &immap->lbus; lbus->bank[3].br = CFG_BR3_PRELIM; diff --git a/board/mpc8349itx/pci.c b/board/mpc8349itx/pci.c index b4637bc8cd..535cc34afc 100644 --- a/board/mpc8349itx/pci.c +++ b/board/mpc8349itx/pci.c @@ -88,7 +88,7 @@ void pci_init_board(void) u32 dev; struct pci_controller *hose; - immr = (immap_t *) CFG_IMMRBAR; + immr = (immap_t *) CFG_IMMR; clk = (clk83xx_t *) & immr->clk; pci_law = immr->sysconf.pcilaw; pci_pot = immr->ios.pot; @@ -211,7 +211,7 @@ void pci_init_board(void) hose->region_count = 4; pci_setup_indirect(hose, - (CFG_IMMRBAR + 0x8300), (CFG_IMMRBAR + 0x8304)); + (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); pci_register_hose(hose); @@ -302,7 +302,7 @@ void pci_init_board(void) hose->region_count = 4; pci_setup_indirect(hose, - (CFG_IMMRBAR + 0x8380), (CFG_IMMRBAR + 0x8384)); + (CFG_IMMR + 0x8380), (CFG_IMMR + 0x8384)); pci_register_hose(hose); diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c index a9b1d9eb32..ddc1047c61 100644 --- a/board/mpc8360emds/mpc8360emds.c +++ b/board/mpc8360emds/mpc8360emds.c @@ -106,7 +106,7 @@ void sdram_init(void); long int initdram(int board_type) { - volatile immap_t *im = (immap_t *) CFG_IMMRBAR; + volatile immap_t *im = (immap_t *) CFG_IMMR; u32 msize = 0; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) @@ -141,7 +141,7 @@ long int initdram(int board_type) ************************************************************************/ int fixed_sdram(void) { - volatile immap_t *im = (immap_t *) CFG_IMMRBAR; + volatile immap_t *im = (immap_t *) CFG_IMMR; u32 msize = 0; u32 ddr_size; u32 ddr_size_log2; @@ -196,7 +196,7 @@ int checkboard(void) void sdram_init(void) { - volatile immap_t *immap = (immap_t *) CFG_IMMRBAR; + volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile lbus83xx_t *lbc = &immap->lbus; uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE; @@ -267,7 +267,7 @@ void sdram_init(void) */ void ecc_print_status(void) { - volatile immap_t *immap = (immap_t *) CFG_IMMRBAR; + volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile ddr83xx_t *ddr = &immap->ddr; printf("\nECC mode: %s\n\n", @@ -347,7 +347,7 @@ void ecc_print_status(void) int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { - volatile immap_t *immap = (immap_t *) CFG_IMMRBAR; + volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile ddr83xx_t *ddr = &immap->ddr; volatile u32 val; u64 *addr; diff --git a/board/mpc8360emds/pci.c b/board/mpc8360emds/pci.c index c81e7a64ed..a013ba3d43 100644 --- a/board/mpc8360emds/pci.c +++ b/board/mpc8360emds/pci.c @@ -63,7 +63,7 @@ void pci_init_board(void) volatile pcictrl83xx_t *pci_ctrl; volatile pciconf83xx_t *pci_conf; - immr = (immap_t *) CFG_IMMRBAR; + immr = (immap_t *) CFG_IMMR; pci_law = immr->sysconf.pcilaw; pci_pot = immr->ios.pot; pci_ctrl = immr->pci_ctrl; @@ -89,7 +89,7 @@ void pci_init_board(void) hose[0].first_busno = 0; hose[0].last_busno = 0xff; pci_setup_indirect(&hose[0], - (CFG_IMMRBAR + 0x8300), (CFG_IMMRBAR + 0x8304)); + (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); reg16 = 0xff; pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), @@ -131,7 +131,7 @@ void pci_init_board(void) u32 val32; u32 dev; - immr = (immap_t *) CFG_IMMRBAR; + immr = (immap_t *) CFG_IMMR; clk = (clk83xx_t *) & immr->clk; pci_law = immr->sysconf.pcilaw; pci_pot = immr->ios.pot; @@ -274,7 +274,7 @@ void pci_init_board(void) hose[0].region_count = 4; pci_setup_indirect(&hose[0], - (CFG_IMMRBAR + 0x8300), (CFG_IMMRBAR + 0x8304)); + (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); pci_register_hose(hose); diff --git a/board/tqm834x/pci.c b/board/tqm834x/pci.c index d01277f808..d896f17aad 100644 --- a/board/tqm834x/pci.c +++ b/board/tqm834x/pci.c @@ -78,7 +78,7 @@ pci_init_board(void) u32 reg32; struct pci_controller * hose; - immr = (immap_t *)CFG_IMMRBAR; + immr = (immap_t *)CFG_IMMR; clk = (clk83xx_t *)&immr->clk; pci_law = immr->sysconf.pcilaw; pci_pot = immr->ios.pot; @@ -186,8 +186,8 @@ pci_init_board(void) hose->region_count = 3; pci_setup_indirect(hose, - (CFG_IMMRBAR+0x8300), - (CFG_IMMRBAR+0x8304)); + (CFG_IMMR+0x8300), + (CFG_IMMR+0x8304)); pci_register_hose(hose); diff --git a/board/tqm834x/tqm834x.c b/board/tqm834x/tqm834x.c index 41b34cc6fa..36d901f094 100644 --- a/board/tqm834x/tqm834x.c +++ b/board/tqm834x/tqm834x.c @@ -69,7 +69,7 @@ static void set_cs_config(short cs, long config); static void set_ddr_config(void); /* Local variable */ -static volatile immap_t *im = (immap_t *)CFG_IMMRBAR; +static volatile immap_t *im = (immap_t *)CFG_IMMR; /************************************************************************** * Board initialzation after relocation to RAM. Used to detect the number @@ -147,7 +147,7 @@ int checkboard (void) volatile immap_t * immr; u32 w, f; - immr = (immap_t *)CFG_IMMRBAR; + immr = (immap_t *)CFG_IMMR; if (!(immr->reset.rcwh & RCWH_PCIHOST)) { printf("PCI: NOT in host mode..?!\n"); return 0; diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 3d8ca772c6..0bd05330de 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -49,7 +49,7 @@ int checkcpu(void) u32 spridr; char buf[32]; - immr = (immap_t *)CFG_IMMRBAR; + immr = (immap_t *)CFG_IMMR; if ((pvr & 0xFFFF0000) != PVR_83xx) { puts("Not MPC83xx Family!!!\n"); @@ -141,7 +141,7 @@ int checkcpu(void) void upmconfig (uint upm, uint *table, uint size) { #if defined(CONFIG_MPC834X) - volatile immap_t *immap = (immap_t *) CFG_IMMRBAR; + volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile lbus83xx_t *lbus = &immap->lbus; volatile uchar *dummy = NULL; const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */ @@ -188,7 +188,7 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) ulong addr; #endif - volatile immap_t *immap = (immap_t *) CFG_IMMRBAR; + volatile immap_t *immap = (immap_t *) CFG_IMMR; #ifdef MPC83xx_RESET /* Interrupts and MMU off */ @@ -259,7 +259,7 @@ void watchdog_reset (void) int re_enable = disable_interrupts(); /* Reset the 83xx watchdog */ - volatile immap_t *immr = (immap_t *) CFG_IMMRBAR; + volatile immap_t *immr = (immap_t *) CFG_IMMR; immr->wdt.swsrr = 0x556c; immr->wdt.swsrr = 0xaa39; @@ -311,7 +311,7 @@ ft_cpu_setup(void *blob, bd_t *bd) #if defined(CONFIG_DDR_ECC) void dma_init(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; + volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile dma83xx_t *dma = &immap->dma; volatile u32 status = swab32(dma->dmasr0); volatile u32 dmamr0 = swab32(dma->dmamr0); @@ -342,7 +342,7 @@ void dma_init(void) uint dma_check(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; + volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile dma83xx_t *dma = &immap->dma; volatile u32 status = swab32(dma->dmasr0); volatile u32 byte_count = swab32(dma->dmabcr0); @@ -361,7 +361,7 @@ uint dma_check(void) int dma_xfer(void *dest, u32 count, void *src) { - volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; + volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile dma83xx_t *dma = &immap->dma; volatile u32 dmamr0; diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index eb8f8c042f..4f80f4a094 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -219,7 +219,7 @@ void cpu_init_f (volatile immap_t * im) int cpu_init_r (void) { #ifdef CONFIG_QE - uint qe_base = CFG_IMMRBAR + 0x00100000; /* QE immr base */ + uint qe_base = CFG_IMMR + 0x00100000; /* QE immr base */ qe_init(qe_base); qe_reset(); #endif diff --git a/cpu/mpc83xx/interrupts.c b/cpu/mpc83xx/interrupts.c index 5a0babfcbb..98fccff227 100644 --- a/cpu/mpc83xx/interrupts.c +++ b/cpu/mpc83xx/interrupts.c @@ -45,7 +45,7 @@ struct irq_action { int interrupt_init_cpu (unsigned *decrementer_count) { - volatile immap_t *immr = (immap_t *) CFG_IMMRBAR; + volatile immap_t *immr = (immap_t *) CFG_IMMR; *decrementer_count = (gd->bus_clk / 4) / CFG_HZ; diff --git a/cpu/mpc83xx/qe_io.c b/cpu/mpc83xx/qe_io.c index 11cf3722bd..ebe3487112 100644 --- a/cpu/mpc83xx/qe_io.c +++ b/cpu/mpc83xx/qe_io.c @@ -34,7 +34,7 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) u32 pin_2bit_assign; u32 pin_1bit_mask; u32 tmp_val; - volatile immap_t *im = (volatile immap_t *)CFG_IMMRBAR; + volatile immap_t *im = (volatile immap_t *)CFG_IMMR; volatile gpio83xx_t *par_io =(volatile gpio83xx_t *)&im->gpio; /* Caculate pin location and 2bit mask and dir */ diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index b91c6130e7..dc8f6790a6 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -112,7 +112,7 @@ static void spd_debug(spd_eeprom_t *spd) long int spd_sdram() { - volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; + volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ddr83xx_t *ddr = &immap->ddr; volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0]; spd_eeprom_t spd; @@ -562,7 +562,7 @@ static __inline__ unsigned long get_tbms (void) /* #define CONFIG_DDR_ECC_INIT_VIA_DMA */ void ddr_enable_ecc(unsigned int dram_size) { - volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; + volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ddr83xx_t *ddr= &immap->ddr; unsigned long t_start, t_end; register u64 *p; diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c index 1e082a7868..213e7180a7 100644 --- a/cpu/mpc83xx/speed.c +++ b/cpu/mpc83xx/speed.c @@ -94,7 +94,7 @@ corecnf_t corecnf_tab[] = { */ int get_clocks(void) { - volatile immap_t *im = (immap_t *) CFG_IMMRBAR; + volatile immap_t *im = (immap_t *) CFG_IMMR; u32 pci_sync_in; u8 spmf; u8 clkin_div; diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index c43835c8dc..0f27bb61f8 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -104,9 +104,9 @@ version_string: #ifndef CONFIG_DEFAULT_IMMR #error CONFIG_DEFAULT_IMMR must be defined #endif /* CFG_DEFAULT_IMMR */ -#ifndef CFG_IMMRBAR -#define CFG_IMMRBAR CONFIG_DEFAULT_IMMR -#endif /* CFG_IMMRBAR */ +#ifndef CFG_IMMR +#define CFG_IMMR CONFIG_DEFAULT_IMMR +#endif /* CFG_IMMR */ /* * After configuration, a system reset exception is executed using the @@ -152,8 +152,8 @@ boot_cold: /* time t 3 */ nop boot_warm: /* time t 5 */ mfmsr r5 /* save msr contents */ - lis r3, CFG_IMMRBAR@h - ori r3, r3, CFG_IMMRBAR@l + lis r3, CFG_IMMR@h + ori r3, r3, CFG_IMMR@l stw r3, IMMRBAR(r4) /* Initialise the E300 processor core */ @@ -226,7 +226,7 @@ in_flash: GET_GOT /* initialize GOT access */ /* r3: IMMR */ - lis r3, CFG_IMMRBAR@h + lis r3, CFG_IMMR@h /* run low-level CPU init code (in Flash)*/ bl cpu_init_f @@ -446,7 +446,7 @@ init_e300_core: /* time t 10 */ mtspr SRR1, r3 /* Make SRR1 match MSR */ - lis r3, CFG_IMMRBAR@h + lis r3, CFG_IMMR@h #if defined(CONFIG_WATCHDOG) /* Initialise the Wathcdog values and reset it (if req) */ /*------------------------------------------------------*/ @@ -1201,7 +1201,7 @@ map_flash_by_law1: /* When booting from ROM (Flash or EPROM), clear the */ /* Address Mask in OR0 so ROM appears everywhere */ /*----------------------------------------------------*/ - lis r3, (CFG_IMMRBAR)@h /* r3 <= CFG_IMMRBAR */ + lis r3, (CFG_IMMR)@h /* r3 <= CFG_IMMR */ lwz r4, OR0@l(r3) li r5, 0x7fff /* r5 <= 0x00007FFFF */ and r4, r4, r5 diff --git a/drivers/tsec.h b/drivers/tsec.h index 4aa331c458..cee30037db 100644 --- a/drivers/tsec.h +++ b/drivers/tsec.h @@ -30,7 +30,7 @@ #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) #define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET) #elif defined(CONFIG_MPC83XX) - #define TSEC_BASE_ADDR (CFG_IMMRBAR + CFG_TSEC1_OFFSET) + #define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET) #endif diff --git a/include/asm-ppc/i2c.h b/include/asm-ppc/i2c.h index 8afdda2ce2..37847666db 100644 --- a/include/asm-ppc/i2c.h +++ b/include/asm-ppc/i2c.h @@ -79,19 +79,19 @@ typedef struct i2c #endif #define I2C_TIMEOUT (CFG_HZ/4) -#ifndef CFG_IMMRBAR -#error CFG_IMMRBAR is not defined in /include/configs/${BOARD}.h +#ifndef CFG_IMMR +#error CFG_IMMR is not defined in /include/configs/${BOARD}.h #endif #ifndef CFG_I2C_OFFSET #error CFG_I2C_OFFSET is not defined in /include/configs/${BOARD}.h #endif -#define I2C_1 ((i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET)) +#define I2C_1 ((i2c_t*)(CFG_IMMR + CFG_I2C_OFFSET)) /* Optional support for second I2C bus */ #ifdef CFG_I2C2_OFFSET -#define I2C_2 ((i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET)) +#define I2C_2 ((i2c_t*)(CFG_IMMR + CFG_I2C2_OFFSET)) #endif /* CFG_I2C2_OFFSET */ #define I2C_READ 1 diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index e68c41accf..4a5b4bc4a7 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -73,7 +73,7 @@ #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ -#define CFG_IMMRBAR 0xE0000000 +#define CFG_IMMR 0xE0000000 #undef CFG_DRAM_TEST /* memory test, takes time */ #define CFG_MEMTEST_START 0x00000000 /* memtest region */ @@ -311,8 +311,8 @@ #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} -#define CFG_NS16550_COM1 (CFG_IMMRBAR+0x4500) -#define CFG_NS16550_COM2 (CFG_IMMRBAR+0x4600) +#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) +#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) /* Use the HUSH parser */ #define CFG_HUSH_PARSER @@ -345,9 +345,9 @@ /* TSEC */ #define CFG_TSEC1_OFFSET 0x24000 -#define CFG_TSEC1 (CFG_IMMRBAR+CFG_TSEC1_OFFSET) +#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) #define CFG_TSEC2_OFFSET 0x25000 -#define CFG_TSEC2 (CFG_IMMRBAR+CFG_TSEC2_OFFSET) +#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) /* USB */ #define CFG_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ @@ -641,8 +641,8 @@ #endif /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ -#define CFG_IBAT5L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT5U (CFG_IMMRBAR | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ #define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index aaf4d101dc..c74e63a4d4 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -128,7 +128,7 @@ #endif #endif -#define CFG_IMMRBAR 0xE0000000 /* The IMMR is relocated to here */ +#define CFG_IMMR 0xE0000000 /* The IMMR is relocated to here */ #undef CFG_DRAM_TEST /* memory test, takes time */ #define CFG_MEMTEST_START 0x00003000 /* memtest region */ @@ -374,8 +374,8 @@ #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} -#define CFG_NS16550_COM1 (CFG_IMMRBAR + 0x4500) -#define CFG_NS16550_COM2 (CFG_IMMRBAR + 0x4600) +#define CFG_NS16550_COM1 (CFG_IMMR + 0x4500) +#define CFG_NS16550_COM2 (CFG_IMMR + 0x4600) /* Use the HUSH parser */ #define CFG_HUSH_PARSER @@ -653,8 +653,8 @@ #endif /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ -#define CFG_IBAT5L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT5U (CFG_IMMRBAR | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ #define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index feb9cf22f2..a8f2df911e 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -92,7 +92,7 @@ /* * IMMR new address */ -#define CFG_IMMRBAR 0xE0000000 +#define CFG_IMMR 0xE0000000 /* * DDR Setup @@ -306,8 +306,8 @@ #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} -#define CFG_NS16550_COM1 (CFG_IMMRBAR+0x4500) -#define CFG_NS16550_COM2 (CFG_IMMRBAR+0x4600) +#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) +#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) /* Use the HUSH parser */ #define CFG_HUSH_PARSER @@ -515,9 +515,9 @@ #define CFG_DBAT0U CFG_IBAT0U /* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CFG_IBAT1L (CFG_IMMRBAR | BATL_PP_10 | \ +#define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT1U (CFG_IMMRBAR | BATU_BL_4M | BATU_VS | BATU_VP) +#define CFG_IBAT1U (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) #define CFG_DBAT1L CFG_IBAT1L #define CFG_DBAT1U CFG_IBAT1U diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 727094b203..b0b0673cff 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -41,7 +41,7 @@ #define CONFIG_TQM834X 1 /* TQM834X board specific */ /* IMMR Base Addres Register, use Freescale default: 0xff400000 */ -#define CFG_IMMRBAR 0xff400000 +#define CFG_IMMR 0xff400000 /* System clock. Primary input clock when in PCI host mode */ #define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */ @@ -210,8 +210,8 @@ extern int tqm834x_num_flash_banks; #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} -#define CFG_NS16550_COM1 (CFG_IMMRBAR + 0x4500) -#define CFG_NS16550_COM2 (CFG_IMMRBAR + 0x4600) +#define CFG_NS16550_COM1 (CFG_IMMR + 0x4500) +#define CFG_NS16550_COM2 (CFG_IMMR + 0x4600) /* * I2C @@ -248,9 +248,9 @@ extern int tqm834x_num_flash_banks; #define CONFIG_MII #define CFG_TSEC1_OFFSET 0x24000 -#define CFG_TSEC1 (CFG_IMMRBAR + CFG_TSEC1_OFFSET) +#define CFG_TSEC1 (CFG_IMMR + CFG_TSEC1_OFFSET) #define CFG_TSEC2_OFFSET 0x25000 -#define CFG_TSEC2 (CFG_IMMRBAR + CFG_TSEC2_OFFSET) +#define CFG_TSEC2 (CFG_IMMR + CFG_TSEC2_OFFSET) #if defined(CONFIG_TSEC_ENET) @@ -473,8 +473,8 @@ extern int tqm834x_num_flash_banks; #endif /* IMMRBAR */ -#define CFG_IBAT6L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT6U (CFG_IMMRBAR | BATU_BL_1M | BATU_VS | BATU_VP) +#define CFG_IBAT6L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT6U (CFG_IMMR | BATU_BL_1M | BATU_VS | BATU_VP) /* FLASH */ #define CFG_IBAT7L (CFG_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) diff --git a/lib_ppc/board.c b/lib_ppc/board.c index 844bbc9003..1866dc5cf0 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -511,7 +511,7 @@ void board_init_f (ulong bootflag) bd->bi_mbar_base = CFG_MBAR; /* base of internal registers */ #endif #if defined(CONFIG_MPC83XX) - bd->bi_immrbar = CFG_IMMRBAR; + bd->bi_immrbar = CFG_IMMR; #endif #if defined(CONFIG_MPC8220) bd->bi_mbar_base = CFG_MBAR; /* base of internal registers */ -- cgit v1.2.3 From be5e61815d5a1fac290ce9c0ef09cb6a8e4288fa Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Fri, 3 Nov 2006 19:15:00 -0600 Subject: mpc83xx: Update 83xx to use fsl_i2c.c Update the 83xx tree to use I2C support in drivers/fsl_i2c.c. Delete cpu/mpc83xx/i2c.c, include/asm-ppc/i2c.h, and all references to those files. Added multiple I2C bus support to fsl_i2c.c. Signed-off-by: Timur Tabi --- README | 11 ++ board/mpc8349emds/pci.c | 7 +- board/mpc8349itx/mpc8349itx.c | 47 ++--- board/mpc8349itx/pci.c | 5 +- board/mpc8360emds/pci.c | 13 +- cpu/mpc83xx/Makefile | 2 +- cpu/mpc83xx/cpu.c | 4 +- cpu/mpc83xx/i2c.c | 423 ------------------------------------------ drivers/fsl_i2c.c | 113 +++++++---- include/asm-ppc/i2c.h | 100 ---------- include/asm-ppc/immap_83xx.h | 4 +- include/configs/MPC8349EMDS.h | 1 + include/configs/MPC8349ITX.h | 49 +++-- include/configs/MPC8360EMDS.h | 3 +- include/configs/TQM834x.h | 1 + 15 files changed, 163 insertions(+), 620 deletions(-) delete mode 100644 cpu/mpc83xx/i2c.c delete mode 100644 include/asm-ppc/i2c.h (limited to 'drivers') diff --git a/README b/README index 5c907c8f07..d03862b3ef 100644 --- a/README +++ b/README @@ -1342,6 +1342,17 @@ The following options need to be configured: will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1 + CFG_SPD_BUS_NUM + + If defined, then this indicates the I2C bus number for DDR SPD. + If not defined, then U-Boot assumes that SPD is on I2C bus 0. + + CONFIG_FSL_I2C + + Define this option if you want to use Freescale's I2C driver in + drivers/fsl_i2c.c. + + - SPI Support: CONFIG_SPI Enables SPI driver (so far only tested with diff --git a/board/mpc8349emds/pci.c b/board/mpc8349emds/pci.c index da49a5d80d..bb60e730bc 100644 --- a/board/mpc8349emds/pci.c +++ b/board/mpc8349emds/pci.c @@ -74,9 +74,7 @@ pib_init(void) */ /* Switch temporarily to I2C bus #2 */ orig_i2c_bus = i2c_get_bus_num(); - - if(orig_i2c_bus != 2) - i2c_set_bus_num(2); + i2c_set_bus_num(1); val8 = 0; i2c_write(0x23, 0x6, 1, &val8, 1); @@ -122,8 +120,7 @@ pib_init(void) printf("PCI2: 32-bit on PMC3\n"); #endif /* Reset to original I2C bus */ - if(orig_i2c_bus != 2) - i2c_set_bus_num(orig_i2c_bus); + i2c_set_bus_num(orig_i2c_bus); } /************************************************************************** diff --git a/board/mpc8349itx/mpc8349itx.c b/board/mpc8349itx/mpc8349itx.c index c0e72c93e1..097bb370e7 100644 --- a/board/mpc8349itx/mpc8349itx.c +++ b/board/mpc8349itx/mpc8349itx.c @@ -134,8 +134,7 @@ volatile static struct pci_controller hose[] = { }; #endif /* CONFIG_PCI */ -/* If MPC8349E-mITX is soldered with SDRAM, then initialize it. -*/ +/* If MPC8349E-mITX is soldered with SDRAM, then initialize it. */ void sdram_init(void) { @@ -255,32 +254,12 @@ long int initdram(int board_type) int checkboard(void) { -#ifdef CONFIG_HARD_I2C - u8 i2c_data; -#endif - - puts("Board: Freescale MPC8349E-mITX"); - -#ifdef CONFIG_HARD_I2C - i2c_set_bus_num(2); - if (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == - 0) - printf(" %u.%u (PCF8475A)", (i2c_data & 0x02) >> 1, - i2c_data & 0x01); - else if (i2c_read(CFG_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) - == 0) - printf(" %u.%u (PCF8475)", (i2c_data & 0x02) >> 1, - i2c_data & 0x01); - else - printf(" ?.?"); -#endif - - puts("\n"); + puts("Board: Freescale MPC8349E-mITX\n"); return 0; } -/** +/* * Implement a work-around for a hardware problem with compact * flash. * @@ -347,7 +326,7 @@ int misc_init_f(void) return 0; } -/** +/* * Make sure the EEPROM has the HRCW correctly programmed. * Make sure the RTC is correctly programmed. * @@ -366,7 +345,8 @@ int misc_init_r(void) #ifdef CONFIG_HARD_I2C - uchar orig_bus = i2c_get_bus_num();; + unsigned int orig_bus = i2c_get_bus_num();; + u8 i2c_data; #ifdef CFG_I2C_RTC_ADDR char ds1339_data[17]; @@ -381,8 +361,21 @@ int misc_init_r(void) }; u8 data[sizeof(eeprom_data)]; +#endif + printf("Board revision: "); i2c_set_bus_num(1); + if (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0) + printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01); + else if (i2c_read(CFG_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0) + printf("%u.%u (PCF8475)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01); + else { + printf("Unknown\n"); + rc = 1; + } + +#ifdef CFG_I2C_EEPROM_ADDR + i2c_set_bus_num(0); if (i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) { if (memcmp(data, eeprom_data, sizeof(data)) != 0) { @@ -400,7 +393,7 @@ int misc_init_r(void) #endif #ifdef CFG_I2C_RTC_ADDR - i2c_set_bus_num(2); + i2c_set_bus_num(1); if (i2c_read(CFG_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data)) == 0) { diff --git a/board/mpc8349itx/pci.c b/board/mpc8349itx/pci.c index 535cc34afc..e81ad27356 100644 --- a/board/mpc8349itx/pci.c +++ b/board/mpc8349itx/pci.c @@ -29,6 +29,9 @@ #include #include #include +#if defined(CONFIG_OF_FLAT_TREE) +#include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -105,7 +108,7 @@ void pci_init_board(void) udelay(2000); #ifdef CONFIG_HARD_I2C - i2c_set_bus_num(2); + i2c_set_bus_num(1); /* Read the PCI_M66EN jumper setting */ if ((i2c_read(CFG_I2C_8574_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0) || (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0)) { diff --git a/board/mpc8360emds/pci.c b/board/mpc8360emds/pci.c index a013ba3d43..15a48dcf40 100644 --- a/board/mpc8360emds/pci.c +++ b/board/mpc8360emds/pci.c @@ -19,7 +19,7 @@ #include #include -#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -200,9 +200,7 @@ void pci_init_board(void) /* Switch temporarily to I2C bus #2 */ orig_i2c_bus = i2c_get_bus_num(); - - if(orig_i2c_bus != 2) - i2c_set_bus_num(2); + i2c_set_bus_num(1); val8 = 0; i2c_write(0x23, 0x6, 1, &val8, 1); @@ -231,12 +229,7 @@ void pci_init_board(void) asm("eieio"); /* Reset to original I2C bus */ - if(orig_i2c_bus != 2) - i2c_set_bus_num(orig_i2c_bus); - - /* Reset to original I2C bus */ - if(orig_i2c_bus != 2) - i2c_set_bus_num(orig_i2c_bus); + i2c_set_bus_num(orig_i2c_bus); /* * Release PCI RST Output signal diff --git a/cpu/mpc83xx/Makefile b/cpu/mpc83xx/Makefile index e254ef98f6..4b9dcc8180 100644 --- a/cpu/mpc83xx/Makefile +++ b/cpu/mpc83xx/Makefile @@ -29,7 +29,7 @@ LIB = $(obj)lib$(CPU).a START = start.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ - i2c.o spd_sdram.o qe_io.o + spd_sdram.o qe_io.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 0bd05330de..1d169bab22 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -111,7 +111,7 @@ int checkcpu(void) } -/** +/* * Program a UPM with the code supplied in the table. * * The 'dummy' variable is used to increment the MAD. 'dummy' is @@ -137,7 +137,7 @@ int checkcpu(void) * upm: 0=UPMA, 1=UPMB, 2=UPMC * table: Pointer to an array of values to program * size: Number of elements in the array. Must be 64 or less. -*/ + */ void upmconfig (uint upm, uint *table, uint size) { #if defined(CONFIG_MPC834X) diff --git a/cpu/mpc83xx/i2c.c b/cpu/mpc83xx/i2c.c deleted file mode 100644 index ce78491616..0000000000 --- a/cpu/mpc83xx/i2c.c +++ /dev/null @@ -1,423 +0,0 @@ -/* - * (C) Copyright 2006 Freescale Semiconductor, Inc. - * - * (C) Copyright 2003,Motorola Inc. - * Xianghua Xiao - * Adapted for Motorola 85xx chip. - * - * (C) Copyright 2003 - * Gleb Natapov - * Some bits are taken from linux driver writen by adrian@humboldt.co.uk - * - * Hardware I2C driver for MPC107 PCI bridge. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Change log: - * - * 20050101: Eran Liberty (liberty@freescale.com) - * Initial file creating (porting from 85XX & 8260) - * 20060601: Dave Liu (daveliu@freescale.com) - * Unified variable names for mpc83xx - */ - -#include -#include -#include - -#ifdef CONFIG_HARD_I2C -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* Initialize the bus pointer to whatever one the SPD EEPROM is on. - * Default is bus 1. This is necessary because the DDR initialization - * runs from ROM, and we can't switch buses because we can't modify - * the i2c_dev variable. Everything gets straightened out once i2c_init - * is called from RAM. */ - -#ifndef CFG_SPD_BUS_NUM -#define CFG_SPD_BUS_NUM 1 -#endif - -static unsigned int i2c_bus_num = CFG_SPD_BUS_NUM; - -#if CFG_SPD_BUS_NUM == 1 -static volatile i2c_t *i2c_dev = I2C_1; -#else -static volatile i2c_t *i2c_dev = I2C_2; -#endif - -static int i2c_bus_speed[2] = {0, 0}; - -/* - * Map the frequency divider to the FDR. This data is taken from table 17-5 - * of the MPC8349EA reference manual, with duplicates removed. - */ -static struct { - unsigned int divider; - u8 fdr; -} i2c_speed_map[] = -{ - {0, 0x20}, - {256, 0x20}, - {288, 0x21}, - {320, 0x22}, - {352, 0x23}, - {384, 0x24}, - {416, 0x01}, - {448, 0x25}, - {480, 0x02}, - {512, 0x26}, - {576, 0x27}, - {640, 0x28}, - {704, 0x05}, - {768, 0x29}, - {832, 0x06}, - {896, 0x2A}, - {1024, 0x2B}, - {1152, 0x08}, - {1280, 0x2C}, - {1536, 0x2D}, - {1792, 0x2E}, - {1920, 0x0B}, - {2048, 0x2F}, - {2304, 0x0C}, - {2560, 0x30}, - {3072, 0x31}, - {3584, 0x32}, - {3840, 0x0F}, - {4096, 0x33}, - {4608, 0x10}, - {5120, 0x34}, - {6144, 0x35}, - {7168, 0x36}, - {7680, 0x13}, - {8192, 0x37}, - {9216, 0x14}, - {10240, 0x38}, - {12288, 0x39}, - {14336, 0x3A}, - {15360, 0x17}, - {16384, 0x3B}, - {18432, 0x18}, - {20480, 0x3C}, - {24576, 0x3D}, - {28672, 0x3E}, - {30720, 0x1B}, - {32768, 0x3F}, - {36864, 0x1C}, - {40960, 0x1D}, - {49152, 0x1E}, - {61440, 0x1F}, - {-1, 0x1F} -}; - -#define NUM_I2C_SPEEDS (sizeof(i2c_speed_map) / sizeof(i2c_speed_map[0])) - -static int set_speed(unsigned int speed) -{ - unsigned long i2c_clk; - unsigned int divider, i; - u8 fdr = 0x3F; - - i2c_clk = (i2c_bus_num == 2) ? gd->i2c2_clk : gd->i2c1_clk; - - divider = i2c_clk / speed; - - /* Scan i2c_speed_map[] for the closest matching divider.*/ - - for (i = 0; i < NUM_I2C_SPEEDS-1; i++) { - /* Locate our divider in between two entries in i2c_speed_map[] */ - if ((divider >= i2c_speed_map[i].divider) && - (divider <= i2c_speed_map[i+1].divider)) { - /* Which one is closer? */ - if ((divider - i2c_speed_map[i].divider) < (i2c_speed_map[i+1].divider - divider)) { - fdr = i2c_speed_map[i].fdr; - } else { - fdr = i2c_speed_map[i+1].fdr; - } - break; - } - } - - writeb(fdr, &i2c_dev->fdr); - i2c_bus_speed[i2c_bus_num - 1] = speed; - - return 0; -} - - -static void _i2c_init(int speed, int slaveadd) -{ - /* stop I2C controller */ - writeb(0x00 , &i2c_dev->cr); - - /* set clock */ - set_speed(speed); - - /* set default filter */ - writeb(IC2_FDR,&i2c_dev->dfsrr); - - /* write slave address */ - writeb(slaveadd, &i2c_dev->adr); - - /* clear status register */ - writeb(I2C_CR_MTX, &i2c_dev->sr); - - /* start I2C controller */ - writeb(I2C_CR_MEN, &i2c_dev->cr); -} - -void i2c_init(int speed, int slaveadd) -{ - /* Set both interfaces to the same speed and slave address */ - /* Note: This function gets called twice - before and after - * relocation to RAM. The first time it's called, we are unable - * to change buses, so whichever one 'i2c_dev' was initialized to - * gets set twice. When run from RAM both buses get set properly */ - - i2c_set_bus_num(1); - _i2c_init(speed, slaveadd); -#ifdef CFG_I2C2_OFFSET - i2c_set_bus_num(2); - _i2c_init(speed, slaveadd); - i2c_set_bus_num(1); -#endif /* CFG_I2C2_OFFSET */ -} - -static __inline__ int -i2c_wait4bus (void) -{ - ulong timeval = get_timer (0); - while (readb(&i2c_dev->sr) & I2C_SR_MBB) { - if (get_timer (timeval) > I2C_TIMEOUT) { - return -1; - } - } - return 0; -} - -static __inline__ int -i2c_wait (int write) -{ - u32 csr; - ulong timeval = get_timer(0); - do { - csr = readb(&i2c_dev->sr); - - if (!(csr & I2C_SR_MIF)) - continue; - - writeb(0x0, &i2c_dev->sr); - - if (csr & I2C_SR_MAL) { - debug("i2c_wait: MAL\n"); - return -1; - } - - if (!(csr & I2C_SR_MCF)) { - debug("i2c_wait: unfinished\n"); - return -1; - } - - if (write == I2C_WRITE && (csr & I2C_SR_RXAK)) { - debug("i2c_wait: No RXACK\n"); - return -1; - } - - return 0; - } while (get_timer (timeval) < I2C_TIMEOUT); - - debug("i2c_wait: timed out\n"); - return -1; -} - -static __inline__ int -i2c_write_addr (u8 dev, u8 dir, int rsta) -{ - writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX | - (rsta?I2C_CR_RSTA:0), - &i2c_dev->cr); - - writeb((dev << 1) | dir, &i2c_dev->dr); - - if (i2c_wait (I2C_WRITE) < 0) - return 0; - return 1; -} - -static __inline__ int -__i2c_write (u8 *data, int length) -{ - int i; - - writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX, - &i2c_dev->cr); - - for (i=0; i < length; i++) { - writeb(data[i], &i2c_dev->dr); - - if (i2c_wait (I2C_WRITE) < 0) - break; - } - return i; -} - -static __inline__ int -__i2c_read (u8 *data, int length) -{ - int i; - - writeb(I2C_CR_MEN | I2C_CR_MSTA | - ((length == 1) ? I2C_CR_TXAK : 0), - &i2c_dev->cr); - - /* dummy read */ - readb(&i2c_dev->dr); - - for (i=0; i < length; i++) { - if (i2c_wait (I2C_READ) < 0) - break; - - /* Generate ack on last next to last byte */ - if (i == length - 2) - writeb(I2C_CR_MEN | I2C_CR_MSTA | - I2C_CR_TXAK, - &i2c_dev->cr); - - /* Generate stop on last byte */ - if (i == length - 1) - writeb(I2C_CR_MEN | I2C_CR_TXAK, &i2c_dev->cr); - - data[i] = readb(&i2c_dev->dr); - } - return i; -} - -int -i2c_read (u8 dev, uint addr, int alen, u8 *data, int length) -{ - int i = 0; - u8 *a = (u8*)&addr; - - if (i2c_wait4bus () < 0) - goto exit; - - if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) - goto exit; - - if (__i2c_write (&a[4 - alen], alen) != alen) - goto exit; - - if (i2c_write_addr (dev, I2C_READ, 1) == 0) - goto exit; - - i = __i2c_read (data, length); - - exit: - writeb(I2C_CR_MEN, &i2c_dev->cr); - return !(i == length); -} - -int -i2c_write (u8 dev, uint addr, int alen, u8 *data, int length) -{ - int i = 0; - u8 *a = (u8*)&addr; - - if (i2c_wait4bus () < 0) - goto exit; - - if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) - goto exit; - - if (__i2c_write (&a[4 - alen], alen) != alen) - goto exit; - - i = __i2c_write (data, length); - - exit: - writeb(I2C_CR_MEN, &i2c_dev->cr); - return !(i == length); -} - -int i2c_probe (uchar chip) -{ - int tmp; - - /* - * Try to read the first location of the chip. The underlying - * driver doesn't appear to support sending just the chip address - * and looking for an back. - */ - udelay(10000); - return i2c_read (chip, 0, 1, (uchar *)&tmp, 1); -} - -uchar i2c_reg_read (uchar i2c_addr, uchar reg) -{ - uchar buf[1]; - - i2c_read (i2c_addr, reg, 1, buf, 1); - - return (buf[0]); -} - -void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val) -{ - i2c_write (i2c_addr, reg, 1, &val, 1); -} - -int i2c_set_bus_num(unsigned int bus) -{ - if(bus == 1) - { - i2c_dev = I2C_1; - } -#ifdef CFG_I2C2_OFFSET - else if(bus == 2) - { - i2c_dev = I2C_2; - } -#endif - else - { - return -1; - } - i2c_bus_num = bus; - return 0; -} - -int i2c_set_bus_speed(unsigned int speed) -{ - return set_speed(speed); -} - -unsigned int i2c_get_bus_num(void) -{ - return i2c_bus_num; -} - -unsigned int i2c_get_bus_speed(void) -{ - return i2c_bus_speed[i2c_bus_num - 1]; -} -#endif /* CONFIG_HARD_I2C */ diff --git a/drivers/fsl_i2c.c b/drivers/fsl_i2c.c index 65c27439e3..0e39213487 100644 --- a/drivers/fsl_i2c.c +++ b/drivers/fsl_i2c.c @@ -28,29 +28,49 @@ #include /* HW definitions */ #define I2C_TIMEOUT (CFG_HZ / 4) -#define I2C ((struct fsl_i2c *)(CFG_IMMR + CFG_I2C_OFFSET)) +/* Initialize the bus pointer to whatever one the SPD EEPROM is on. + * Default is bus 0. This is necessary because the DDR initialization + * runs from ROM, and we can't switch buses because we can't modify + * the global variables. + */ +#ifdef CFG_SPD_BUS_NUM +static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CFG_SPD_BUS_NUM; +#else +static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0; +#endif + +static volatile struct fsl_i2c *i2c_dev[2] = { + (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET), +#ifdef CFG_I2C2_OFFSET + (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET) +#endif +}; void i2c_init(int speed, int slaveadd) { - /* stop I2C controller */ - writeb(0x0, &I2C->cr); - - /* set clock */ - writeb(0x3f, &I2C->fdr); - - /* set default filter */ - writeb(0x10, &I2C->dfsrr); - - /* write slave address */ - writeb(slaveadd, &I2C->adr); - - /* clear status register */ - writeb(0x0, &I2C->sr); - - /* start I2C controller */ - writeb(I2C_CR_MEN, &I2C->cr); + volatile struct fsl_i2c *dev; + + dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET); + + writeb(0, &dev->cr); /* stop I2C controller */ + writeb(0x3F, &dev->fdr); /* set bus speed */ + writeb(0x3F, &dev->dfsrr); /* set default filter */ + writeb(slaveadd, &dev->adr); /* write slave address */ + writeb(0x0, &dev->sr); /* clear status register */ + writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ + +#ifdef CFG_I2C2_OFFSET + dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET); + + writeb(0, &dev->cr); /* stop I2C controller */ + writeb(0x3F, &dev->fdr); /* set bus speed */ + writeb(0x3F, &dev->dfsrr); /* set default filter */ + writeb(slaveadd, &dev->adr); /* write slave address */ + writeb(0x0, &dev->sr); /* clear status register */ + writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ +#endif /* CFG_I2C2_OFFSET */ } static __inline__ int @@ -58,7 +78,7 @@ i2c_wait4bus(void) { ulong timeval = get_timer(0); - while (readb(&I2C->sr) & I2C_SR_MBB) { + while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) { if (get_timer(timeval) > I2C_TIMEOUT) { return -1; } @@ -74,11 +94,11 @@ i2c_wait(int write) ulong timeval = get_timer(0); do { - csr = readb(&I2C->sr); + csr = readb(&i2c_dev[i2c_bus_num]->sr); if (!(csr & I2C_SR_MIF)) continue; - writeb(0x0, &I2C->sr); + writeb(0x0, &i2c_dev[i2c_bus_num]->sr); if (csr & I2C_SR_MAL) { debug("i2c_wait: MAL\n"); @@ -107,9 +127,9 @@ i2c_write_addr (u8 dev, u8 dir, int rsta) { writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX | (rsta ? I2C_CR_RSTA : 0), - &I2C->cr); + &i2c_dev[i2c_bus_num]->cr); - writeb((dev << 1) | dir, &I2C->dr); + writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr); if (i2c_wait(I2C_WRITE) < 0) return 0; @@ -123,10 +143,10 @@ __i2c_write(u8 *data, int length) int i; writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX, - &I2C->cr); + &i2c_dev[i2c_bus_num]->cr); for (i = 0; i < length; i++) { - writeb(data[i], &I2C->dr); + writeb(data[i], &i2c_dev[i2c_bus_num]->dr); if (i2c_wait(I2C_WRITE) < 0) break; @@ -141,10 +161,10 @@ __i2c_read(u8 *data, int length) int i; writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0), - &I2C->cr); + &i2c_dev[i2c_bus_num]->cr); /* dummy read */ - readb(&I2C->dr); + readb(&i2c_dev[i2c_bus_num]->dr); for (i = 0; i < length; i++) { if (i2c_wait(I2C_READ) < 0) @@ -153,13 +173,13 @@ __i2c_read(u8 *data, int length) /* Generate ack on last next to last byte */ if (i == length - 2) writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK, - &I2C->cr); + &i2c_dev[i2c_bus_num]->cr); /* Generate stop on last byte */ if (i == length - 1) - writeb(I2C_CR_MEN | I2C_CR_TXAK, &I2C->cr); + writeb(I2C_CR_MEN | I2C_CR_TXAK, &i2c_dev[i2c_bus_num]->cr); - data[i] = readb(&I2C->dr); + data[i] = readb(&i2c_dev[i2c_bus_num]->dr); } return i; @@ -178,7 +198,7 @@ i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) i = __i2c_read(data, length); } - writeb(I2C_CR_MEN, &I2C->cr); + writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); if (i == length) return 0; @@ -198,7 +218,7 @@ i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) i = __i2c_write(data, length); } - writeb(I2C_CR_MEN, &I2C->cr); + writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); if (i == length) return 0; @@ -237,5 +257,34 @@ i2c_reg_write(uchar i2c_addr, uchar reg, uchar val) i2c_write(i2c_addr, reg, 1, &val, 1); } +int i2c_set_bus_num(unsigned int bus) +{ +#ifdef CFG_I2C2_OFFSET + if (bus > 1) { +#else + if (bus > 0) { +#endif + return -1; + } + + i2c_bus_num = bus; + + return 0; +} + +int i2c_set_bus_speed(unsigned int speed) +{ + return -1; +} + +unsigned int i2c_get_bus_num(void) +{ + return i2c_bus_num; +} + +unsigned int i2c_get_bus_speed(void) +{ + return 0; +} #endif /* CONFIG_HARD_I2C */ #endif /* CONFIG_FSL_I2C */ diff --git a/include/asm-ppc/i2c.h b/include/asm-ppc/i2c.h deleted file mode 100644 index 37847666db..0000000000 --- a/include/asm-ppc/i2c.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Freescale I2C Controller - * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2003, Motorola, Inc. - * author: Eran Liberty (liberty@freescale.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ASM_I2C_H_ -#define _ASM_I2C_H_ - -#include - -typedef struct i2c -{ - u8 adr; /**< I2C slave address */ -#define I2C_ADR 0xFE -#define I2C_ADR_SHIFT 1 -#define I2C_ADR_RES ~(I2C_ADR) - u8 res0[3]; - u8 fdr; /**< I2C frequency divider register */ -#define IC2_FDR 0x3F -#define IC2_FDR_SHIFT 0 -#define IC2_FDR_RES ~(IC2_FDR) - u8 res1[3]; - u8 cr; /**< I2C control redister */ -#define I2C_CR_MEN 0x80 -#define I2C_CR_MIEN 0x40 -#define I2C_CR_MSTA 0x20 -#define I2C_CR_MTX 0x10 -#define I2C_CR_TXAK 0x08 -#define I2C_CR_RSTA 0x04 -#define I2C_CR_BCST 0x01 - u8 res2[3]; - u8 sr; /**< I2C status register */ -#define I2C_SR_MCF 0x80 -#define I2C_SR_MAAS 0x40 -#define I2C_SR_MBB 0x20 -#define I2C_SR_MAL 0x10 -#define I2C_SR_BCSTM 0x08 -#define I2C_SR_SRW 0x04 -#define I2C_SR_MIF 0x02 -#define I2C_SR_RXAK 0x01 - u8 res3[3]; - u8 dr; /**< I2C data register */ -#define I2C_DR 0xFF -#define I2C_DR_SHIFT 0 -#define I2C_DR_RES ~(I2C_DR) - u8 res4[3]; - u8 dfsrr; /**< I2C digital filter sampling rate register */ -#define I2C_DFSRR 0x3F -#define I2C_DFSRR_SHIFT 0 -#define I2C_DFSRR_RES ~(I2C_DR) - u8 res5[3]; - u8 res6[0xE8]; -} i2c_t; - -#ifndef CFG_HZ -#error CFG_HZ is not defined in /include/configs/${BOARD}.h -#endif -#define I2C_TIMEOUT (CFG_HZ/4) - -#ifndef CFG_IMMR -#error CFG_IMMR is not defined in /include/configs/${BOARD}.h -#endif - -#ifndef CFG_I2C_OFFSET -#error CFG_I2C_OFFSET is not defined in /include/configs/${BOARD}.h -#endif - -#define I2C_1 ((i2c_t*)(CFG_IMMR + CFG_I2C_OFFSET)) - -/* Optional support for second I2C bus */ -#ifdef CFG_I2C2_OFFSET -#define I2C_2 ((i2c_t*)(CFG_IMMR + CFG_I2C2_OFFSET)) -#endif /* CFG_I2C2_OFFSET */ - -#define I2C_READ 1 -#define I2C_WRITE 0 - -#endif /* _ASM_I2C_H_ */ diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index 09e08ba0a4..2a76a05c6c 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -39,7 +39,7 @@ #include #include -#include +#include /* * Local Access Window. @@ -2007,7 +2007,7 @@ typedef struct immap { qesba83xx_t qesba; /* QE Secondary Bus Access Windows */ #endif ddr83xx_t ddr; /* DDR Memory Controller Memory */ - i2c_t i2c[2]; /* I2C1 Controller */ + fsl_i2c_t i2c[2]; /* I2C Controllers */ u8 res2[0x1300]; duart83xx_t duart[2]; /* DUART */ #if defined (CONFIG_MPC8349) diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 4a5b4bc4a7..5bed2d0a29 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -335,6 +335,7 @@ /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_FSL_I2C #define CONFIG_I2C_MULTI_BUS #define CONFIG_I2C_CMD_TREE #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index c74e63a4d4..8dc96352a1 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -41,14 +41,14 @@ Align. Board Bus Addr Part No. Description Length Location ---------------------------------------------------------------- - I2C1 0x50 M24256-BWMN6P Board EEPROM 2 U64 + I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 - I2C2 0x20 PCF8574 I2C Expander 0 U8 - I2C2 0x21 PCF8574 I2C Expander 0 U10 - I2C2 0x38 PCF8574A I2C Expander 0 U8 - I2C2 0x39 PCF8574A I2C Expander 0 U10 - I2C2 0x51 (DDR) DDR EEPROM 1 U1 - I2C2 0x68 DS1339 RTC 1 U68 + I2C1 0x20 PCF8574 I2C Expander 0 U8 + I2C1 0x21 PCF8574 I2C Expander 0 U10 + I2C1 0x38 PCF8574A I2C Expander 0 U8 + I2C1 0x39 PCF8574A I2C Expander 0 U10 + I2C1 0x51 (DDR) DDR EEPROM 1 U1 + I2C1 0x68 DS1339 RTC 1 U68 Note that a given board has *either* a pair of 8574s or a pair of 8574As. */ @@ -77,19 +77,20 @@ #define CONFIG_MISC_INIT_F #define CONFIG_MISC_INIT_R +#define CONFIG_FSL_I2C #define CONFIG_I2C_MULTI_BUS #define CONFIG_I2C_CMD_TREE #define CFG_I2C_OFFSET 0x3000 #define CFG_I2C2_OFFSET 0x3100 -#define CFG_SPD_BUS_NUM 2 +#define CFG_SPD_BUS_NUM 1 /* The I2C bus for SPD */ -#define CFG_I2C_8574_ADDR1 0x20 /* I2C2, PCF8574 */ -#define CFG_I2C_8574_ADDR2 0x21 /* I2C2, PCF8574 */ -#define CFG_I2C_8574A_ADDR1 0x38 /* I2C2, PCF8574A */ -#define CFG_I2C_8574A_ADDR2 0x39 /* I2C2, PCF8574A */ -#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C1, Board EEPROM */ -#define CFG_I2C_RTC_ADDR 0x68 /* I2C2, DS1339 RTC*/ -#define SPD_EEPROM_ADDRESS 0x51 /* I2C2, DDR */ +#define CFG_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ +#define CFG_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ +#define CFG_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ +#define CFG_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ +#define CFG_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ +#define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F @@ -175,6 +176,7 @@ #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ #define CFG_FLASH_SIZE 16 /* FLASH size in MB */ +#define CFG_FLASH_EMPTY_INFO #define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V) #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ @@ -610,7 +612,7 @@ #define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ #define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ #define CFG_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ -#define CFG_SCCR_TSEC2CM 1 /* TSEC2 & I2C1 clock mode (0-3) */ +#define CFG_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count */ /* System IO Config */ @@ -708,6 +710,19 @@ #define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02 #endif +#if 1 +#define CONFIG_IPADDR 10.82.19.159 +#define CONFIG_SERVERIP 10.82.48.106 +#define CONFIG_GATEWAYIP 10.82.19.254 +#define CONFIG_NETMASK 255.255.252.0 +#define CONFIG_NETDEV eth0 + +#define CONFIG_HOSTNAME mpc8349emitx +#define CONFIG_ROOTPATH /nfsroot0/u/timur/itx-ltib/rootfs +#define CONFIG_BOOTFILE timur/uImage + +#define CONFIG_UBOOTPATH timur/u-boot.bin +#else #define CONFIG_IPADDR 192.168.1.253 #define CONFIG_SERVERIP 192.168.1.1 #define CONFIG_GATEWAYIP 192.168.1.1 @@ -719,6 +734,8 @@ #define CONFIG_BOOTFILE uImage #define CONFIG_UBOOTPATH u-boot.bin +#endif + #define CONFIG_UBOOTSTART fe700000 #define CONFIG_UBOOTEND fe77ffff diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index a8f2df911e..2ff5f48980 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -330,7 +330,8 @@ /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 0x3F /* I2C speed and slave address */ +#define CONFIG_FSL_I2C +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x52} /* Don't probe these addrs */ #define CFG_I2C_OFFSET 0x3000 diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index b0b0673cff..728083b304 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -218,6 +218,7 @@ extern int tqm834x_num_flash_banks; */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_FSL_I2C #define CFG_I2C_SPEED 400000 /* I2C speed: 400KHz */ #define CFG_I2C_SLAVE 0x7F /* slave address */ #define CFG_I2C_OFFSET 0x3000 -- cgit v1.2.3 From 1aa934c81b77f2080d3ca4b226eab67b17a33961 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Tue, 28 Nov 2006 23:28:33 -0600 Subject: Eliminate gcc 4 'used uninitialized' warnings in drivers/qe/uccf.c give initial values for reg_num, shift, p_cmxucr in ucc_set_clk_src since they are passed by reference to ucc_get_cmxucr_reg and assigned. --- drivers/qe/uccf.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/qe/uccf.c b/drivers/qe/uccf.c index 25f74826c0..013aa543db 100644 --- a/drivers/qe/uccf.c +++ b/drivers/qe/uccf.c @@ -100,9 +100,9 @@ static void ucc_get_cmxucr_reg(int ucc_num, volatile u32 **p_cmxucr, static int ucc_set_clk_src(int ucc_num, qe_clock_e clock, comm_dir_e mode) { - volatile u32 *p_cmxucr; - u8 reg_num; - u8 shift; + volatile u32 *p_cmxucr = NULL; + u8 reg_num = 0; + u8 shift = 0; u32 clockBits; u32 clockMask; int source = -1; -- cgit v1.2.3 From 14198bf768fdc958e3c1afd2404e5262208e98d7 Mon Sep 17 00:00:00 2001 From: Joakim Tjernlund Date: Tue, 28 Nov 2006 16:17:18 -0600 Subject: Fix I2C master address initialization. Signed-off-by: Timur Tabi --- drivers/fsl_i2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/fsl_i2c.c b/drivers/fsl_i2c.c index 0e39213487..f00e8026bc 100644 --- a/drivers/fsl_i2c.c +++ b/drivers/fsl_i2c.c @@ -57,7 +57,7 @@ i2c_init(int speed, int slaveadd) writeb(0, &dev->cr); /* stop I2C controller */ writeb(0x3F, &dev->fdr); /* set bus speed */ writeb(0x3F, &dev->dfsrr); /* set default filter */ - writeb(slaveadd, &dev->adr); /* write slave address */ + writeb(slaveadd << 1, &dev->adr); /* write slave address */ writeb(0x0, &dev->sr); /* clear status register */ writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ -- cgit v1.2.3 From 1939d969443ccf316cab2bf32ab1027d4db5ba1a Mon Sep 17 00:00:00 2001 From: Joakim Tjernlund Date: Tue, 28 Nov 2006 16:17:27 -0600 Subject: Make fsl-i2c not conflict with SOFT I2C Signed-off-by: Timur Tabi --- drivers/fsl_i2c.c | 17 ++++++++++------- include/asm-ppc/fsl_i2c.h | 4 ---- 2 files changed, 10 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/fsl_i2c.c b/drivers/fsl_i2c.c index f00e8026bc..c92909608a 100644 --- a/drivers/fsl_i2c.c +++ b/drivers/fsl_i2c.c @@ -29,6 +29,9 @@ #define I2C_TIMEOUT (CFG_HZ / 4) +#define I2C_READ_BIT 1 +#define I2C_WRITE_BIT 0 + /* Initialize the bus pointer to whatever one the SPD EEPROM is on. * Default is bus 0. This is necessary because the DDR initialization * runs from ROM, and we can't switch buses because we can't modify @@ -110,7 +113,7 @@ i2c_wait(int write) return -1; } - if (write == I2C_WRITE && (csr & I2C_SR_RXAK)) { + if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) { debug("i2c_wait: No RXACK\n"); return -1; } @@ -131,7 +134,7 @@ i2c_write_addr (u8 dev, u8 dir, int rsta) writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr); - if (i2c_wait(I2C_WRITE) < 0) + if (i2c_wait(I2C_WRITE_BIT) < 0) return 0; return 1; @@ -148,7 +151,7 @@ __i2c_write(u8 *data, int length) for (i = 0; i < length; i++) { writeb(data[i], &i2c_dev[i2c_bus_num]->dr); - if (i2c_wait(I2C_WRITE) < 0) + if (i2c_wait(I2C_WRITE_BIT) < 0) break; } @@ -167,7 +170,7 @@ __i2c_read(u8 *data, int length) readb(&i2c_dev[i2c_bus_num]->dr); for (i = 0; i < length; i++) { - if (i2c_wait(I2C_READ) < 0) + if (i2c_wait(I2C_READ_BIT) < 0) break; /* Generate ack on last next to last byte */ @@ -192,9 +195,9 @@ i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) u8 *a = (u8*)&addr; if (i2c_wait4bus() >= 0 - && i2c_write_addr(dev, I2C_WRITE, 0) != 0 + && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0 && __i2c_write(&a[4 - alen], alen) == alen - && i2c_write_addr(dev, I2C_READ, 1) != 0) { + && i2c_write_addr(dev, I2C_READ_BIT, 1) != 0) { i = __i2c_read(data, length); } @@ -213,7 +216,7 @@ i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) u8 *a = (u8*)&addr; if (i2c_wait4bus() >= 0 - && i2c_write_addr(dev, I2C_WRITE, 0) != 0 + && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0 && __i2c_write(&a[4 - alen], alen) == alen) { i = __i2c_write(data, length); } diff --git a/include/asm-ppc/fsl_i2c.h b/include/asm-ppc/fsl_i2c.h index 76b1c4309b..4f71341327 100644 --- a/include/asm-ppc/fsl_i2c.h +++ b/include/asm-ppc/fsl_i2c.h @@ -83,8 +83,4 @@ typedef struct fsl_i2c { u8 res6[0xE8]; } fsl_i2c_t; - -#define I2C_READ 1 -#define I2C_WRITE 0 - #endif /* _ASM_I2C_H_ */ -- cgit v1.2.3