From d9cefd38d3bae229ef7b22184e429a9aa4be2bd8 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 13 Jun 2016 07:31:09 +0200 Subject: dts: update to v4.6-rc6 Signed-off-by: Sascha Hauer --- dts/Bindings/arc/archs-pct.txt | 2 +- dts/Bindings/arc/pct.txt | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'dts/Bindings/arc') diff --git a/dts/Bindings/arc/archs-pct.txt b/dts/Bindings/arc/archs-pct.txt index 1ae98b87c6..e4b9dcee6d 100644 --- a/dts/Bindings/arc/archs-pct.txt +++ b/dts/Bindings/arc/archs-pct.txt @@ -2,7 +2,7 @@ The ARC HS can be configured with a pipeline performance monitor for counting CPU and cache events like cache misses and hits. Like conventional PCT there -are 100+ hardware conditions dynamically mapped to upto 32 counters. +are 100+ hardware conditions dynamically mapped to up to 32 counters. It also supports overflow interrupts. Required properties: diff --git a/dts/Bindings/arc/pct.txt b/dts/Bindings/arc/pct.txt index 7b9588444f..4e874d9a38 100644 --- a/dts/Bindings/arc/pct.txt +++ b/dts/Bindings/arc/pct.txt @@ -2,7 +2,7 @@ The ARC700 can be configured with a pipeline performance monitor for counting CPU and cache events like cache misses and hits. Like conventional PCT there -are 100+ hardware conditions dynamically mapped to upto 32 counters +are 100+ hardware conditions dynamically mapped to up to 32 counters Note that: * The ARC 700 PCT does not support interrupts; although HW events may be -- cgit v1.2.3