From 604ad71929a1deabe77b7ab9c3655d82002d79c9 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 21 Oct 2014 13:11:04 +0200 Subject: dts: update to v3.18-rc1 Signed-off-by: Sascha Hauer --- dts/Bindings/arm/altera/socfpga-sdram-edac.txt | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 dts/Bindings/arm/altera/socfpga-sdram-edac.txt (limited to 'dts/Bindings/arm/altera') diff --git a/dts/Bindings/arm/altera/socfpga-sdram-edac.txt b/dts/Bindings/arm/altera/socfpga-sdram-edac.txt new file mode 100644 index 0000000000..d0ce01da5c --- /dev/null +++ b/dts/Bindings/arm/altera/socfpga-sdram-edac.txt @@ -0,0 +1,15 @@ +Altera SOCFPGA SDRAM Error Detection & Correction [EDAC] +The EDAC accesses a range of registers in the SDRAM controller. + +Required properties: +- compatible : should contain "altr,sdram-edac"; +- altr,sdr-syscon : phandle of the sdr module +- interrupts : Should contain the SDRAM ECC IRQ in the + appropriate format for the IRQ controller. + +Example: + sdramedac { + compatible = "altr,sdram-edac"; + altr,sdr-syscon = <&sdr>; + interrupts = <0 39 4>; + }; -- cgit v1.2.3