From 5f3e773ca4830daf71c7b5eee0c6b1dfe4d09c08 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 27 Jan 2022 11:22:53 +0100 Subject: dts: update to v5.17-rc1 Signed-off-by: Sascha Hauer --- dts/Bindings/arm/arm-dsu-pmu.txt | 27 --------------------------- 1 file changed, 27 deletions(-) delete mode 100644 dts/Bindings/arm/arm-dsu-pmu.txt (limited to 'dts/Bindings/arm/arm-dsu-pmu.txt') diff --git a/dts/Bindings/arm/arm-dsu-pmu.txt b/dts/Bindings/arm/arm-dsu-pmu.txt deleted file mode 100644 index 6efabba530..0000000000 --- a/dts/Bindings/arm/arm-dsu-pmu.txt +++ /dev/null @@ -1,27 +0,0 @@ -* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU) - -ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores -with a shared L3 memory system, control logic and external interfaces to -form a multicore cluster. The PMU enables to gather various statistics on -the operations of the DSU. The PMU provides independent 32bit counters that -can count any of the supported events, along with a 64bit cycle counter. -The PMU is accessed via CPU system registers and has no MMIO component. - -** DSU PMU required properties: - -- compatible : should be one of : - - "arm,dsu-pmu" - -- interrupts : Exactly 1 SPI must be listed. - -- cpus : List of phandles for the CPUs connected to this DSU instance. - - -** Example: - -dsu-pmu-0 { - compatible = "arm,dsu-pmu"; - interrupts = ; - cpus = <&cpu_0>, <&cpu_1>; -}; -- cgit v1.2.3