From a9c5f6b9ec883ee9dafd6d393600acc6fd263043 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 27 Feb 2018 09:40:19 +0100 Subject: dts: update to v4.16-rc1 Also includeded: ARM: dts: am33xx: do not delete no longer existing clocks Several clocks are removed from the am33xx dts files with v4.16-rc1. Remove the corresponding /delete-node/ directives aswell to avoid dtc breakage. Also included: ARM: dts: imx6qdl: SolidRun: Fix upstream include Upstream dts file way renamed, so change include name accordingly. Signed-off-by: Sascha Hauer --- dts/Bindings/arm/arm-dsu-pmu.txt | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 dts/Bindings/arm/arm-dsu-pmu.txt (limited to 'dts/Bindings/arm/arm-dsu-pmu.txt') diff --git a/dts/Bindings/arm/arm-dsu-pmu.txt b/dts/Bindings/arm/arm-dsu-pmu.txt new file mode 100644 index 0000000000..6efabba530 --- /dev/null +++ b/dts/Bindings/arm/arm-dsu-pmu.txt @@ -0,0 +1,27 @@ +* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU) + +ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores +with a shared L3 memory system, control logic and external interfaces to +form a multicore cluster. The PMU enables to gather various statistics on +the operations of the DSU. The PMU provides independent 32bit counters that +can count any of the supported events, along with a 64bit cycle counter. +The PMU is accessed via CPU system registers and has no MMIO component. + +** DSU PMU required properties: + +- compatible : should be one of : + + "arm,dsu-pmu" + +- interrupts : Exactly 1 SPI must be listed. + +- cpus : List of phandles for the CPUs connected to this DSU instance. + + +** Example: + +dsu-pmu-0 { + compatible = "arm,dsu-pmu"; + interrupts = ; + cpus = <&cpu_0>, <&cpu_1>; +}; -- cgit v1.2.3