From abef60363d8ecac66e45853f328afa8eeb9e00fd Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 23 Jun 2020 12:14:59 +0200 Subject: dts: update to v5.8-rc1 Signed-off-by: Sascha Hauer --- dts/Bindings/arm/calxeda/l2ecc.yaml | 42 +++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 dts/Bindings/arm/calxeda/l2ecc.yaml (limited to 'dts/Bindings/arm/calxeda/l2ecc.yaml') diff --git a/dts/Bindings/arm/calxeda/l2ecc.yaml b/dts/Bindings/arm/calxeda/l2ecc.yaml new file mode 100644 index 0000000000..a9fe01238a --- /dev/null +++ b/dts/Bindings/arm/calxeda/l2ecc.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/calxeda/l2ecc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Calxeda Highbank L2 cache ECC + +description: | + Binding for the Calxeda Highbank L2 cache controller ECC device. + This does not cover the actual L2 cache controller control registers, + but just the error reporting functionality. + +maintainers: + - Andre Przywara + +properties: + compatible: + const: "calxeda,hb-sregs-l2-ecc" + + reg: + maxItems: 1 + + interrupts: + items: + - description: single bit error interrupt + - description: double bit error interrupt + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + sregs@fff3c200 { + compatible = "calxeda,hb-sregs-l2-ecc"; + reg = <0xfff3c200 0x100>; + interrupts = <0 71 4>, <0 72 4>; + }; -- cgit v1.2.3