From 00ce25c6dcdae5582ae4be37147ab33678adc995 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 25 Apr 2014 11:22:32 +0200 Subject: Add devicetree source files as of Linux-3.15-rc2 This adds the Linux dts files to barebox. The dts files are generated from Ian Campbells device-tree-rebasing.git: git://xenbits.xen.org/people/ianc/device-tree-rebasing.git The dts are found in dts/ in the barebox repository and will be updated from upstream regularly, probably for each upstream -rc. To keep the synchronization with upstream easy no changes to the original files are allowed under dts/. Instead changes to upstream dts files will be done using overlays in arch/$ARCH/dts/. Signed-off-by: Sascha Hauer --- dts/Bindings/arm/calxeda/combophy.txt | 17 +++++++++++++++++ dts/Bindings/arm/calxeda/l2ecc.txt | 15 +++++++++++++++ dts/Bindings/arm/calxeda/mem-ctrlr.txt | 16 ++++++++++++++++ 3 files changed, 48 insertions(+) create mode 100644 dts/Bindings/arm/calxeda/combophy.txt create mode 100644 dts/Bindings/arm/calxeda/l2ecc.txt create mode 100644 dts/Bindings/arm/calxeda/mem-ctrlr.txt (limited to 'dts/Bindings/arm/calxeda') diff --git a/dts/Bindings/arm/calxeda/combophy.txt b/dts/Bindings/arm/calxeda/combophy.txt new file mode 100644 index 0000000000..6622bdb2e8 --- /dev/null +++ b/dts/Bindings/arm/calxeda/combophy.txt @@ -0,0 +1,17 @@ +Calxeda Highbank Combination Phys for SATA + +Properties: +- compatible : Should be "calxeda,hb-combophy" +- #phy-cells: Should be 1. +- reg : Address and size for Combination Phy registers. +- phydev: device ID for programming the combophy. + +Example: + + combophy5: combo-phy@fff5d000 { + compatible = "calxeda,hb-combophy"; + #phy-cells = <1>; + reg = <0xfff5d000 0x1000>; + phydev = <31>; + }; + diff --git a/dts/Bindings/arm/calxeda/l2ecc.txt b/dts/Bindings/arm/calxeda/l2ecc.txt new file mode 100644 index 0000000000..94e642a33d --- /dev/null +++ b/dts/Bindings/arm/calxeda/l2ecc.txt @@ -0,0 +1,15 @@ +Calxeda Highbank L2 cache ECC + +Properties: +- compatible : Should be "calxeda,hb-sregs-l2-ecc" +- reg : Address and size for ECC error interrupt clear registers. +- interrupts : Should be single bit error interrupt, then double bit error + interrupt. + +Example: + + sregs@fff3c200 { + compatible = "calxeda,hb-sregs-l2-ecc"; + reg = <0xfff3c200 0x100>; + interrupts = <0 71 4 0 72 4>; + }; diff --git a/dts/Bindings/arm/calxeda/mem-ctrlr.txt b/dts/Bindings/arm/calxeda/mem-ctrlr.txt new file mode 100644 index 0000000000..049675944b --- /dev/null +++ b/dts/Bindings/arm/calxeda/mem-ctrlr.txt @@ -0,0 +1,16 @@ +Calxeda DDR memory controller + +Properties: +- compatible : Should be: + - "calxeda,hb-ddr-ctrl" for ECX-1000 + - "calxeda,ecx-2000-ddr-ctrl" for ECX-2000 +- reg : Address and size for DDR controller registers. +- interrupts : Interrupt for DDR controller. + +Example: + + memory-controller@fff00000 { + compatible = "calxeda,hb-ddr-ctrl"; + reg = <0xfff00000 0x1000>; + interrupts = <0 91 4>; + }; -- cgit v1.2.3